KR101347207B1 - Driving circuit of LCD - Google Patents

Abstract

The present invention relates to a liquid crystal display device, and more particularly, to a driving circuit of a liquid crystal display device in which a gamma circuit for generating only a gamma voltage (GMA) corresponding to one gamma curve is applied to liquid crystal panels having different driving modes. will be.

According to the present invention, a gamma curve can be inverted by inverting a data signal input to a decoder that selects a gamma voltage in response to a selection signal. Accordingly, liquid crystals of different driving modes can be inverted only by a gamma circuit implementing one gamma curve. Applicable to the panel.

Accordingly, by managing only one gamma curve, the loss of wrong gamma use can be reduced, and standardized management can be performed. In particular, one type of data driver corresponding to liquid crystal panels of normally white and normally black modes can be combined. There is an advantage to that.

Normally White mode, Normally Black mode, TN (Twisted nematic) mode, In Plane Switching (IPS) mode, Gamma Curve

Description

Driving circuit of liquid crystal display device

1 is a block diagram schematically illustrating a configuration of a general liquid crystal display device.

2A and 2B are graphs showing the shapes of the positive and negative gamma curves when the driving mode of the liquid crystal panel is normally white mode, respectively.

3A and 3B are graphs showing the shapes of the positive and negative gamma curves when the driving mode of the liquid crystal panel is normally black mode, respectively.

4 is a block diagram schematically illustrating a structure of a data driver among driving circuits of a liquid crystal display according to an exemplary embodiment of the present invention.

5 is an equivalent circuit diagram of a gamma reference unit, a P-decoder unit, and a P-inverting unit among the data driver components of a liquid crystal display according to an exemplary embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

SSC, SSP, POL: Control signal data: Data signal

P / N-GMA: Positive / Negative Gamma Voltage 150: Data Driver

151 control unit 152 shift register unit

153: latch portion 154: gamma reference

155: DAC 156, 157: P / N-decoder section

158: mux part 159: output buffer part

166, 167: P / N-inverted DL: data line

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, a driving circuit of a liquid crystal display device which can apply a gamma circuit that generates only a gamma voltage (GMA) corresponding to one gamma curve to liquid crystal panels having different driving modes. It is about.

Liquid crystal displays have low power consumption and are capable of thinning and realizing large screens. Therefore, LCDs are in the spotlight as next-generation advanced display devices with high added value as display devices such as notebook computers and large screen TVs.

In the field of liquid crystal display devices, active matrix liquid crystal displays (AMLCDs) are mainstream. In this AMLCD, one thin film transistor (TFT) defines one pixel, and one TFT controls the voltage level of the pixel as a switching element to change the light transmittance of the pixel to display an image.

FIG. 1 is a block diagram schematically illustrating a configuration of a general liquid crystal display, and a thin film transistor T is provided in a matrix form at a point where a plurality of gate lines GL and data lines DL intersect to display an image. A liquid crystal panel 10, a timing controller 20 receiving a control signal and a data signal from the outside, and controlling the driving circuit of the liquid crystal panel 10 in response to the signals; A gate driver 30 for supplying a gate signal to the panel 10 and a data driver 50 for supplying a data signal to the liquid crystal panel 10. The gamma voltage GMA is also applied to the data driver 50. And a common voltage circuit 70 for supplying a common voltage Vcom to the liquid crystal panel 10.

In particular, the liquid crystal panel 10 is formed by bonding the first and second substrates with the liquid crystal layer interposed therebetween, and controls the light transmittance of the liquid crystal according to the magnitude of the electric field formed by the voltage difference between the two substrates. In detail, a gray scale voltage corresponding to an image signal is applied to one of the two substrates, and a common voltage Vcom is applied to the other substrate to form an electric field by the voltage difference between the two signals. The light transmittance is controlled.

Hereinafter, the operation of a general liquid crystal display device will be described.

The liquid crystal panel 10 displays an image by controlling the light transmittance of the liquid crystal capacitor Clc through the on / off operation of the plurality of thin film transistors T arranged in a matrix form.

The timing controller 20 receives a control signal from the outside, generates a gate control signal for driving the gate driver and a data control signal for driving the data driver, and supplies the control signal to each driving circuit.

In addition, the timing controller 20 receives a data signal from the outside, rearranges the data signal into a form that the data driver 50 can process, and supplies the data signal to the data driver 50.

In response to the gate control signal supplied from the timing controller 20, the gate driver 30 sequentially outputs the gate driving signal Vg by one horizontal line for one frame through each gate line GL. To 10).

The data driver 50 receives a digital data signal from the timing controller 20 and converts the digital signal into an analog video signal corresponding to a reference voltage, and converts the video signal of one horizontal line through all the data lines DL. At the same time, it is supplied to the liquid crystal panel.

In more detail the digital-analog conversion process of the data signal described above, the data driver 50 includes a digital-to-analog converter (DAC), which is a gamma circuit 60. Is supplied with a plurality of gamma voltages (GMA). The DAC divides the gamma voltage GMA in response to the digital data signal, converts the gamma voltage GMA into a video signal as a reference signal, and supplies the same to the liquid crystal panel 10 through the data line DL.

2A and 2B are graphs showing positive and negative gamma curves when the driving mode of the liquid crystal panel is normally white mode, and FIGS. 3A and 3B are graphs when the driving mode of the liquid crystal panel is normally black mode, respectively. , Graphs showing positive and negative gamma curves.

As shown, the positive and negative gamma curves used in the liquid crystal panel of the normally white mode are applied to the liquid crystal panel of the TN mode as the absolute value of the gamma voltage increases as the data signal increases. The positive and negative gamma curves used in the liquid crystal panel are applied to the liquid crystal panel of the IPS mode as the absolute value of the gamma voltage decreases as the data signal increases.

As shown, the gamma curve of the normally white mode is a form in which the gamma curve (b) of the normally black mode and the left and right are inverted from each other.

Accordingly, liquid crystal panels having different driving modes require gamma circuits having different types of gamma curves.

It is an object of the present invention to provide a driving circuit of a liquid crystal display device in which a gamma circuit having one gamma curve is applied to liquid crystal panels of different driving modes.

In order to achieve the above object, the driving apparatus of the liquid crystal display according to the embodiment of the present invention, the control unit for outputting a data signal in response to a control signal input from the outside; A shift register unit sequentially outputting the data signal; A latch for storing the data signal output from the shift register; An inversion unit for inverting and outputting the data signal stored in the latch unit in response to a selection signal; A gamma reference unit for supplying a plurality of gamma voltages; A decoder unit for selecting and outputting one of the plurality of gamma voltages in response to the data signal output from the inverting unit; A multiplexer for selecting a polarity of a signal output from the decoder; And an output buffer unit for outputting a signal of a polarity selected from the mux portion to a signal line.

The absolute value of the gamma voltage increases as the data signal increases.

The absolute value of the gamma voltage decreases as the data signal increases.

The inverting unit and the decoder unit are each provided with two so as to process a positive polarity signal and a negative polarity signal.

The inverting unit includes an n-th input terminal configured to receive an n-bit data signal; First and second input parts connected to the n-th input terminal and including N-channel and P-channel transistors for receiving a 1-bit non-inverting signal and an inverting signal of the data signal, respectively; The N-channel and P-channel transistors may be turned on / off by the selection signal.

개의 스위칭소자와; 상기 스위칭소자를 통해 출력되는 상기 감마전압을 외부로 출력하는 버퍼부를 포함하는 것을 특징으로 한다.The decoder unit may include first and second input lines connected to the first and second input units, respectively, to receive n-th bits of the data signal; Respectively connected to the first and second input lines to output one of n gamma voltages

Switching elements; And a buffer unit configured to output the gamma voltage output through the switching device to the outside.

The buffer unit is characterized in that the output terminal is OP-AMP is a voltage follower structure connected to the inverting stage.

The gamma reference unit may include a plurality of resistors for dividing a plurality of input first and second voltages.

The following description focuses on the data driver, which is the biggest feature of the present invention, and other components of the liquid crystal display device have the same structure as before. Referring to the drawings, a driving circuit of a liquid crystal display according to an exemplary embodiment of the present invention will be described.

4 is a block diagram schematically illustrating a structure of a data driver among driving circuits of a liquid crystal display according to an exemplary embodiment of the present invention.

As illustrated, the data driver 150 receives a control signal and a data signal input from a timing controller (not shown) to control each circuit, and the latch unit 153 sequentially latches the data signal. A shift register section 152 for storing the data signal, a latch section 153 for storing data signals corresponding to one horizontal line and outputting the same to the DAC section 155, and a gamma reference section for receiving and dividing a gamma voltage. 154, a DAC unit 155 for converting the data signal in an analog form into a digital form and outputting it to an output buffer unit 159, and converting the digital data signal into a data line DL as an image signal. It consists of an output buffer part 159 to output.

In addition, the DAC unit 155 divides the data signal stored in the latch unit 153 into positive and negative, and refers to one of a plurality of gamma voltages supplied from a gamma circuit (not shown) in response to the data signal. P-decoder and N-decoder sections 156 and 157 which are selected as signals, and P-inverting sections which are provided at input terminals of the P-decoder section and N-decoder sections 156 and 157 to invert the gamma voltage. And a mux part for selectively outputting reference signals of the P-decoder part and the N-decoder parts 156 and 157 to the output buffer part under the control of the N-inverting parts 166 and 167 and the control part 151. 158).

Hereinafter, the operation of the data driver of the driving circuit of the liquid crystal display according to the embodiment of the present invention will be described with reference to the drawings.

First, when the source start pulse SSP is applied from the timing controller (not shown) to the controller 151, the latch unit 153 sequentially sequentially stores data signals having R, G, and B information supplied from the outside. Save it.

This storage operation is performed from the shift register unit 152. In other words, the shift register unit 152 sequentially activates the latch unit 153 in synchronization with the source sampling clock SSC applied to the control unit 151. The data signal data may be sequentially stored in the latch unit 153.

When the data signal data corresponding to one horizontal line is stored in the latch unit 153, the data signal data is supplied to the DAC 155.

The P-decoder unit 156 and the N-decoder unit 157 of the DAC 155 receive the data signal data supplied from the latch unit 153.

In addition, the P-decoder section 156 and the N-decoder section 157 are positive gamma voltages supplied from the gamma reference section 154 under the control of the P-inverting section 166 and the N-inverting section 167. P-GMA) and negative gamma voltage (N-GMA).

In more detail, the P-inverting unit 166 and the N-inverting unit 167 are circuits for determining whether the plurality of gamma voltages GMA input from the gamma reference unit 154 is inverted. The gamma voltage input to the P-decoder section 156 and the N-decoder section 157 is inverted according to (SEL).

In addition, the P-decoder 156 and the N-decoder 157 select the positive gamma voltage P-GMA and the negative gamma voltage N-GMA corresponding to the data signal, respectively. Output as a signal.

Thereafter, the mux unit 158 selects the P-decoder unit 156 and the N-decoder unit 157 in synchronization with the polarity inversion signal POL applied to the control unit 151, and selects one of these. The video signal is supplied to the output buffer unit 159.

The output buffer unit 159 supplies the supplied image signal to the liquid crystal panel (not shown) through the data line DL.

Through this operation, the data driver 150 which is a driving circuit of the liquid crystal display according to the exemplary embodiment of the present invention supplies an analog image signal to the liquid crystal panel.

개의 감마전압(GMA)을 공급하는 감마레퍼런스부(154)와, 이를 선택하기 위한 n비트 디코터(156)는, n값이 2(n=2)인 8개의 감마전압(GMA0 내지 GMA7)중 하나를 선택하는 3비트 디코더의 예로서 설명하며, 실제 회로에서는 이보다 많은 감마전압(GMA) 및 많은 비트를 처리하는 디코더가 사용될 수 있다.Hereinafter, the structures of the gamma reference unit 154, the P-decoder unit 156, and the P-inverting unit 166 will be described in detail with reference to FIG. 5. 4 illustrates an example of the P-decoder unit 156 and the P-inverting unit 166 for convenience. The N-decoder 157 and the N-inverting unit 167 have the same structure, but the input voltage Only the values are different. Also

The gamma reference unit 154 for supplying the gamma voltages GMA and the n-bit decoder 156 for selecting the same are among the eight gamma voltages GMA0 to GMA7 having n values of 2 (n = 2). As an example of a 3-bit decoder that selects one, an actual circuit may use a decoder that processes more gamma voltages (GMAs) and more bits.

5 is an equivalent circuit diagram of a gamma reference unit, a P-decoder unit, and a P-inverting unit among the data driver components of a liquid crystal display according to an exemplary embodiment of the present invention.

The gamma reference unit 154 includes a plurality of resistors R that receive the first and second voltages VH and VL and divide them into a plurality of voltage levels.

The P-decoder 156 divides the n-bit signal into inverted and non-inverted signals by 2n input lines, that is, six input lines L1 to L6 for processing 3-bit signals, and the six inputs. A plurality of switching elements T are enabled through the lines L1 to L6, and four, third, and third switching elements T are provided on the first and second input lines L1 and L2, respectively. Four input lines L3 and L4 are respectively connected, and one fifth and sixth input lines L5 and L6 are respectively connected.

This structure is a structure in which four of the eight gamma voltages GMA1 to GMA8 are selected as the first bit, two as the second bit, and one gamma voltage as the third bit.

In addition, the output terminal of the P-decoder 156 is provided with an OP-AMP (BF) of a voltage follower connection serving as an output buffer.

The P-inverting unit 166 includes n input terminals each receiving n-bit data signals input from the outside, that is, first to third input terminals In1 to In3 respectively receiving three-bit data signals. A plurality of N-channels and Ps for supplying non-inverting or inverting data signals one by one to the first to sixth input lines L1 to L6 of the P-decoder unit 156 according to the first to second selection signals SEL. It is connected to the channel transistors NT and PT. In addition, the N-channel and P-channel transistors NT and PT are connected to each of the first to sixth input lines L1 to L6.

This structure is a structure in which a switching element T provided in the P-decoder 156 is hierarchically connected between a plurality of resistors of the gamma reference unit 154 to select one divided voltage and output the same.

For example, if the gamma reference unit 154 generates the first to eighth gamma voltages GMA1 to GMA8, and the input data signal selects the gamma voltage GMA6, the value of the input data signal is 101. Therefore, a high signal, a low signal, and a high signal are input to the first to third input terminals In1 to In3, respectively.

In this case, when the gamma inversion driving is not performed, the selection signal SEL is at a low level. Therefore, the inversion and non-inversion signals f and fb of the first input terminal In1 are high and low, respectively. It becomes a low signal, a low signal is input to the first connection line L1, and a high signal is input to the second connection line L2. Accordingly, the second, fourth, sixth, and eighth gamma voltages GMA2, 4, 6, and 8 are selected.

In addition, the inverted and non-inverted signals s and sb of the second input terminal In2 become a low signal and a high signal, respectively, and a high signal is input to the third connection line L3. The low signal is input to the fourth connection line L4. Accordingly, the second and sixth gamma voltages GMA2 and 6 are selected.

Finally, the inverted and non-inverted signals t and tb of the third input terminal In1 become a high signal and a low signal, respectively, and a low signal is provided to the fifth connection line L5. A high signal is input to the sixth connection line L6. Accordingly, the sixth gamma voltage GMA6 is selected.

In this operation, when the gamma inversion driving is performed, the selection signal SEL is at a low level, and the input data signal becomes 010 which is an inversion of 101. The sixth gamma voltage GMA is performed through the above-described operation. The third gamma voltage (GMA), which is the inversion of, may be easily found.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims. It can be understood that

Therefore, the driving circuit of the liquid crystal display device according to the embodiment of the present invention can invert the gamma curve by inverting the data signal input to the decoder unit for selecting the gamma voltage in response to the selection signal. Only a gamma circuit that implements a curve can be applied to liquid crystal panels of different driving modes.

Accordingly, by managing only one gamma curve, the loss of wrong gamma use can be reduced, and standardized management can be performed. In particular, one type of data driver corresponding to the liquid crystal panel of the white and black driving modes can be obtained. have.

Claims (8)

A control unit which outputs a data signal in response to a control signal input from the outside; A shift register unit sequentially outputting the data signal; A latch for storing the data signal output from the shift register; An inversion unit for inverting and outputting the data signal stored in the latch unit in response to a selection signal; A gamma reference unit for supplying a plurality of gamma voltages; A decoder unit for selecting and outputting one of the plurality of gamma voltages in response to the data signal output from the inverting unit; A multiplexer for selecting a polarity of a signal output from the decoder; An output buffer unit for outputting a signal of a polarity selected from the mux portion to a signal line, The driving circuit of the liquid crystal display device comprising a. The method of claim 1, And the absolute value of the gamma voltage increases as the data signal increases. The method of claim 1, And the absolute value of the gamma voltage decreases as the data signal increases. The method of claim 1, And two inverting units and two decoder units, respectively, for processing a signal of positive polarity and a signal of negative polarity. The method of claim 1, The inverting unit includes an n-th input terminal configured to receive an n-bit data signal; First and second input parts connected to the n-th input terminal and including N-channel and P-channel transistors for receiving a 1-bit non-inverting signal and an inverting signal of the data signal, respectively; And the N-channel and P-channel transistors are turned on / off by the selection signal. 6. The method of claim 5, The decoder unit, First and second input lines connected to the first and second input units, respectively, to receive n-th bits of the data signal; Respectively connected to the first and second input lines to output one of n gamma voltages

Switching elements; A buffer unit configured to output the gamma voltage output through the switching device to the outside; The driving circuit of the liquid crystal display device comprising a. The method of claim 6, The buffer unit is a driving circuit of the liquid crystal display device, characterized in that the output terminal is OP-AMP having a voltage follower structure connected to the inverting stage. The method of claim 1, And the gamma reference unit includes a plurality of resistors for dividing a plurality of input first and second voltages into a plurality of resistors.

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