KR20080012046A - Lcd and drive method thereof - Google Patents

Abstract

An LCD device and a driving method thereof are provided to minimize the distortion of a common voltage by adjusting the inverse amplification rate of a feedback common voltage according to the position of display data. An LCD(Liquid Crystal Display) device includes a liquid crystal panel(110), a common voltage generator(150), a timing controller(140), and a common voltage compensator(160). The common voltage generator supplies a common voltage supplied to the liquid crystal panel. The timing controller generates amplification rate control signals according to the position of display data in the liquid crystal panel. The common voltage compensator adjusts the inverse amplification rate of a feedback common voltage from the liquid crystal panel according to the position of the display data in the liquid crystal panel with respect to the common voltage in response to the amplification rate control signals and supplies the adjusted inverse amplification rate to the liquid crystal panel.

Description

Liquid crystal display and driving method thereof

1 is a view schematically showing a liquid crystal display device in a general IPS mode.

2 is a diagram showing the structure of common voltage signal wiring;

3A is a view showing a specific pattern displayed by the dot inversion driving method.

FIG. 3B is a drive waveform diagram for the specific pattern shown in FIG. 3A. FIG.

4 is a waveform diagram illustrating that the common voltage is shaken in the positive direction or the negative direction in units of a horizontal period (H).

5 and 6 are views for explaining horizontal crosstalk in a peripheral screen extending in a horizontal direction by a specific pattern in a liquid crystal panel driven by a dot inversion method.

7 is a waveform diagram illustrating that the distortion of the common voltage is intensified toward the lower side of the liquid crystal panel.

8 is a configuration diagram of a liquid crystal display device according to the present invention.

9 is a circuit diagram illustrating a common voltage compensator of a liquid crystal display according to a first exemplary embodiment of the present invention.

10 is a circuit diagram illustrating a common voltage compensator of a liquid crystal display according to a second exemplary embodiment of the present invention.

11 is a block diagram illustrating a common voltage compensator of a liquid crystal display according to a third exemplary embodiment of the present invention.

12 to 14 show changes in inverting amplification ratios of feedback common voltages according to positions of liquid crystal panels of display data.

<Description of Symbols for Main Parts of Drawings>

110: liquid crystal panel 120: data driving circuit

130: gate driving circuit 140: timing controller

150: common voltage generator 160: common voltage compensator

162, 262, 362: Amplification conversion unit 164, 264, 364: Inverted amplification unit

170: common voltage signal wiring

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a driving method thereof. In particular, a liquid crystal display device and a drive thereof capable of minimizing distortion of the common voltage by differently adjusting the inverted amplification factor of the feedback common voltage according to the position of the display data in the liquid crystal panel. It is about a method.

Conventional liquid crystal display devices display an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display device includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix, and a driving circuit for driving the liquid crystal panel.

In the liquid crystal panel, gate lines and data lines are arranged to cross each other, and liquid crystal cells are positioned at intersections of the gate lines and the data lines. Each of the liquid crystal cells is provided with pixel electrodes and a common electrode for applying an electric field. Each of the pixel electrodes is connected to one of the data lines via a thin film transistor which is a switching element. The gate terminal of the thin film transistor is connected to any one of the gate lines through which the pixel voltage signal is applied to the pixel electrodes of one line. As a result, the liquid crystal array between the pixel electrode and the common electrode is changed according to the pixel voltage signal for each liquid crystal cell, thereby adjusting the light transmittance, thereby displaying an image.

The driving circuit includes a gate driving circuit for driving the gate lines, a data driving circuit for driving the data lines, and a common voltage generator for driving the common electrode. The gate driving circuit sequentially supplies the scanning signal, that is, the gate signal to the gate lines, to sequentially drive the liquid crystal cells on the liquid crystal panel by one line. The data driving circuit supplies a pixel voltage signal to each of the data lines whenever a gate signal is supplied to any one of the gate lines. The common voltage generator supplies a common voltage signal to the common electrode.

Such liquid crystal display devices are roughly classified into twisted nematic (TN) mode in which a vertical electric field is applied and in plane switch (IPS) mode in which a horizontal electric field is applied according to the direction of the electric field driving the liquid crystal.

The TN mode is a mode in which a liquid crystal is driven by a vertical electric field between a pixel electrode and a common electrode disposed to face the upper and lower substrates, and has a large aperture ratio but a narrow viewing angle. The IPS mode is a mode in which a liquid crystal is driven by a horizontal electric field between a pixel electrode and a common electrode arranged side by side on the lower substrate, and has a large viewing angle, but a small aperture ratio.

FIG. 1 is a diagram schematically showing a liquid crystal display device in a general IPS mode, and FIG. 2 is a diagram illustrating a structure of a common voltage signal line.

The liquid crystal display of the IPS mode shown in FIG. 1 includes a thin film transistor TFT formed at each intersection of a plurality of data lines DLm and gate lines GLn, a thin film transistor TFT, and a common voltage line VcomLn. And a liquid crystal cell connected between each other.

The gate lines GLn and the data lines DLm cross each other. The plurality of common voltage lines VcomL1 to VcomLn are arranged side by side alternately with the gate lines GL0 to GLn-1 (not shown). The gate lines GLn supply a scan signal, and the data lines DLm supply a data signal. The common voltage lines VcomLn supply a reference voltage to each liquid crystal cell. To this end, the common voltage lines VcomLn are commonly connected to the common voltage signal wiring 20 formed on the left and right sides of the liquid crystal panel 40 as shown in FIG. 2. The thin film transistor TFT causes the liquid crystal cell to charge a data signal from any one of the data lines DLm in response to a scan signal from any one of the gate lines GLn. The liquid crystal cell Clc includes a liquid crystal capacitor Clc composed of a pixel electrode Ep and a common electrode Ec formed on a lower substrate. The pixel electrode Ep is connected to the thin film transistor TFT, and the common electrode Ec is connected to any one of the common voltage lines VcomLn. The liquid crystal cell includes a storage capacitor Cst formed at an overlapping portion of the pixel electrode Ep and the previous gate line with an insulating layer therebetween. The storage capacitor Cst maintains the data signal charged in the liquid crystal capacitor Clc for one frame. The liquid crystal cell implements gradation by controlling the light transmittance by varying the arrangement state of the liquid crystal having dielectric anisotropy according to the charged data signal.

The liquid crystal display device is driven in an inversion method in which the polarity of the data signal is inverted at regular intervals to prevent deterioration and afterimage of the liquid crystal cell. Inversion methods include a dot inversion method, a line inversion method, and a frame inversion method.

The frame inversion scheme reverses the polarity of the data signal supplied to the liquid crystal cells whenever the frame is changed. The line inversion method inverts the polarities of the data signals supplied to the liquid crystal cells in line (low line or column line) units and inverts them in frame units. The dot inversion method inverts the data signals supplied to the liquid crystal cells in dot units and inverts them in frame units. Among them, the dot inversion method has an advantage of providing an image of excellent image quality compared to other methods. However, the dot inversion driving method has a disadvantage in that the horizontal crosstalk phenomenon occurs when the specific pattern shown in FIG. 3A is displayed, thereby degrading the image quality.

3A is a view showing a specific pattern displayed by the dot inversion driving method, and FIG. 3B is a driving waveform diagram for the specific pattern shown in FIG. 3A.

Each of the liquid crystal cells illustrated in FIG. 3A corresponds to each of the red, green, and blue liquid crystal cells (R, G, and B). The red, green, and blue liquid crystal cells R, G, and B are arranged side by side in a stripe shape. As the liquid crystal cells R, G, and B are driven in a dot inversion method, polarities of data signals between adjacent liquid cells in a horizontal direction and a vertical direction are reversed. In particular, the liquid crystal cells R, G, and B display a specific pattern, that is, a vertical stripe pattern in which white gray (for example, 255 gray) and black gray alternate in a column line unit in a normal black mode.

To this end, as illustrated in FIG. 3B, the i-th horizontal line Hi has the polarity of the data signal Vd_255 corresponding to 255 gray and the data signal Vd_0 corresponding to black gray based on the common voltage Vcom. Alternately supplied. In addition, as shown in FIG. 3B, the i + 1 th horizontal line Hi + 1 also has a data signal Vd_255 corresponding to 255 gray and a data signal Vd_0 corresponding to black gray as shown in FIG. 3B. Are alternately supplied with different polarities. Here, the data signal Vd supplied to the i + 1 th horizontal line Hi + 1 has a polarity opposite to that of the data signal Vd supplied to the i th horizontal line Hi.

In this case, since the average level of the data signal supplied to the i-th horizontal line Hi is larger in the positive polarity than in the negative polarity based on the common voltage Vcom, the common voltage Vcom signal is shown in FIG. 4. Is increased with the peak value in the positive direction due to the effect of capacitor coupling with the positive data signal. In addition, since the average level of the data signal supplied to the i + 1th horizontal line Hi + 1 is greater in the negative polarity than in the positive polarity based on the common voltage Vcom, the common voltage is shown in FIG. 4. The (Vcom) signal is lowered with a peak value in the negative direction due to a capacitor coupling effect with the negative data signal. When the data signal for displaying a specific pattern is supplied in a horizontal unit, the common voltage Vcom is in the positive direction or the negative direction in units of the horizontal period H as shown in FIG. 4 according to the average level of the data signal. Ripple phenomenon will occur. The common voltage Vcom ripple also affects the peripheral screen extending in the horizontal direction as shown in FIG. 5 to generate horizontal crosstalk in the peripheral screen.

FIG. 5 is a diagram for describing horizontal crosstalk in a peripheral screen extending in a horizontal direction by a specific pattern in a liquid crystal panel driven by a dot inversion method.

Referring to FIG. 5, when a window B displaying a vertical stripe pattern, which is a specific pattern, is displayed on a portion of the liquid crystal panel image display unit 60, the peripheral screen C extending in the horizontal direction of the window B is also vertical. It can be seen that a horizontal crosstalk pattern in the form of stripes occurs. This is because the common voltage fluctuates toward the positive or negative polarity according to the average level of the data signal in units of horizontal periods even in the peripheral screen due to the vertical stripe pattern displayed in the window B. FIG.

For example, when the average level of the data signal in the i-th horizontal line Hi is large due to the vertical stripe pattern displayed in the window B, the common voltage is shaken with a peak toward the positive polarity. This ripple phenomenon of the common voltage level affects the i-th horizontal line Hi extending to the area outside the window B as shown in FIG. 6. In FIG. 6, the voltage difference between the positive data signal Vdo and the common voltage Vcom is relatively reduced by the common voltage Vcom which is charged toward the positive polarity in the odd-numbered liquid crystal cell charged with the positive data signal Vdo. As it becomes darker in normal black mode. On the contrary, in the even-numbered liquid crystal cell in which the negative data signal Vde is charged, the voltage difference between the negative data signal Vde and the common voltage Vcom is relatively increased due to the common voltage Vcom shaking toward the positive polarity. It will look brighter.

In addition, when the average level of the data signal is negative in the i + 1th horizontal line Hi + 1 due to the vertical stripe pattern displayed in the window B, the common voltage is shaken with a peak value toward the negative polarity. This ripple of the common voltage level is affected as shown in FIG. 6 in the i + 1th horizontal line Hi + 1 extending to the outside area of the window B. FIG. In FIG. 6, the voltage difference between the negative data signal Vdo and the common voltage Vcom is relatively reduced by the common voltage Vcom that is charged toward the negative polarity in the odd-numbered liquid crystal cell in which the negative data signal Vdo is charged. As it becomes darker in normal black mode. In contrast, in the even-numbered liquid crystal cell in which the positive data signal Vde is charged, the voltage difference between the positive data signal Vde and the common voltage Vcom is relatively increased due to the common voltage Vcom shaking toward the negative polarity. It will look brighter.

As a result, even when the data signal of the same gray level is applied to all the areas A and C except the window B, the common voltage ripple phenomenon due to the vertical stripe pattern displayed in the window B is applied to the horizontal direction of the window B. As it affects the peripheral screen (region C), a luminance difference is generated between the odd-numbered liquid crystal cell and the even-numbered liquid crystal cell in the "C" region as described above. As a result, as shown in FIG. 4, horizontal crosstalk patterns such as vertical stripes are generated in the peripheral screen (region C) of the window B, thereby degrading image quality.

In addition, the problem in which the horizontal crosstalk phenomenon occurs is aggravated due to an increase in the line resistance of the common voltage signal wiring 20 toward the " D " direction (lower direction of the liquid crystal panel) in FIG. This is because the current component of the common voltage signal decreases in proportion to the increased line resistance, so that the common voltage signal is more easily distorted according to the average level of the data signal as it goes downward toward the liquid crystal panel as shown in FIG. 7.

Accordingly, an object of the present invention is to provide a liquid crystal display device and a driving method thereof which can minimize distortion of the common voltage by supplying the liquid crystal panel by differently adjusting the inverted amplification factor of the feedback common voltage according to the position of the display data on the liquid crystal panel. It is.

In order to achieve the above object, the liquid crystal display device according to the present invention comprises a liquid crystal panel; A common voltage generator for generating a common voltage supplied to the liquid crystal panel; A timing controller for generating a different amplification rate control signal according to the position of the display data in the liquid crystal panel; And a common voltage compensator configured to adjust the inverted amplification factor of the feedback common voltage from the liquid crystal panel to the liquid crystal panel according to the position of the display data on the liquid crystal panel based on the common voltage in response to the amplification rate control signal. Equipped.

The common voltage compensator may include: an inverting amplifier configured to differentially amplify a feedback common voltage from the liquid crystal panel and a common voltage from the common voltage generator, and to reverse a phase of the differentially amplified signal; And an amplification ratio converter for converting the amplification ratio of the inversion amplifier in response to an amplification ratio control signal from the timing controller.

The inverting amplifier may be a differential amplifier having an inverting input terminal for inputting the feedback common voltage and a non-inverting input terminal for inputting a common voltage.

The liquid crystal panel includes a color filter array substrate and a thin film transistor array substrate facing the color filter array substrate, and the feedback common voltage is fed back from a common voltage signal line formed on one side of the thin film transistor array substrate.

The common voltage signal lines are formed to be separated from each other in the vertical direction on the left and right sides of the thin film transistor substrate, and the feedback common voltage includes first and second feedback common voltages fed back from both lower ends of the common voltage signal lines, respectively. .

The amplification factor converting unit may include: a first input resistor connected to the inverting input terminals of the differential amplifier in parallel with each other, and a second input resistor applied with the first feedback common voltage and the second feedback common voltage; First to sixth negative feedback resistors connected in series between an inverting input terminal of the differential amplifier and an output terminal of the differential amplifier; And first to sixth switches connected in parallel with the first to sixth negative feedback resistors, respectively, and switched in response to an amplification rate control signal from the timing controller to determine the combined resistance values of the negative feedback resistors. .

The amplification rate control signal is a 6 bit digital signal.

Resistance values of the first to sixth negative feedback resistors are different from each other.

The amplification factor converting unit may include: a third input resistor connected in parallel to the inverting input terminal of the differential amplifier, and a fourth input resistor to which the first feedback common voltage is applied and the second feedback common voltage to be applied; Seventh to twelfth negative feedback resistors connected in parallel between an inverting input terminal of the differential amplifier and an output terminal of the differential amplifier; And seventh to twelve signals connected in series between the seventh to twelfth negative feedback resistors and the output terminals of the differential amplifiers to switch in response to an amplification rate control signal from the timing controller, thereby determining a combined resistance value of the negative feedback resistors. And a twelfth switch.

Resistance values of the seventh to twelfth negative feedback resistors are different from each other.

The amplification factor converting unit may include: a fifth input resistor connected to the inverting input terminals of the differential amplifier in parallel with each other, the fifth input resistor to which the first feedback common voltage is applied, and the sixth input resistor to which the second feedback common voltage is applied; A memory for storing a plurality of switch control signals corresponding to the amplification rate control signal; A register for storing an amplification rate control signal from the timing controller and generating a switch control signal corresponding thereto; A decoder for decoding the switch control signal from the register; A plurality of switch elements switched according to the decoded switch control signal; And a resistor string including a plurality of resistors connected in series between the inverting input terminal of the differential amplifier and the output terminal of the differential amplifier and having a combined resistance value determined according to the switching of the switching unit.

The amplification rate control signal and the switch control signal are 7-bit digital signals.

The output pin of the decoder is 128, and the plurality of switch elements are composed of thin film transistors.

Gates of the thin film transistors are connected one-to-one with the output pins of the decoder, drains are commonly connected to the inverting input terminal of the differential amplifier, and sources are connected to the resistor string.

Resistors constituting the resistor string are disposed one by one between a source and a source of the thin film transistors adjacent to the resistor string.

The resistance values of the resistors are the same.

The common voltage compensator further includes an interface circuit for changing the plurality of switch control signals stored in the memory according to external data.

In addition, a method of driving a liquid crystal display according to the present invention may include: a first step of supplying a common voltage to a liquid crystal panel and feeding back a feedback common voltage from the liquid crystal panel; Generating a second amplification rate control signal according to a position of display data in the liquid crystal panel; And a third step of adjusting an inverted amplification factor of the feedback common voltage to the liquid crystal panel according to the position of the display data on the liquid crystal panel based on the common voltage in response to the amplification rate control signal.

In the third step, the inverted amplification factor is converted in response to the amplification rate control signal, and the feedback common voltage is inverted and amplified based on the common voltage according to the converted amplification factor and then supplied to the liquid crystal panel together with the display data. do.

The amplification rate control signal is a digital signal whose number of bits increases in proportion to the size of the liquid crystal panel.

Other objects and features of the present invention in addition to the above object will be apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 8 to 14.

8 is a configuration diagram of a liquid crystal display according to the present invention.

Referring to FIG. 8, the liquid crystal display of the present invention includes a liquid crystal panel 110, a data driving circuit 120 for driving data lines DL1 to DLm of the liquid crystal panel 110, and a liquid crystal panel 110. Gate driving circuit 130 for driving the gate lines GL0 to GLn of FIG. 3), a common voltage generator 150 for generating a common voltage Vcom supplied to the liquid crystal panel 110, and a liquid crystal panel ( The liquid crystal panel 110 uses the feedback common voltage Vcom-F / B from the 110, the common voltage Vcom from the common voltage generator 150, and the amplification factor control signal Φ from the timing controller 140. Control the timing of the common voltage compensation unit 160 and the data driving circuit 120 and the gate driving circuit 130 that adjust the inverted amplification ratio of the feedback common voltage Vcom-F / B differently according to the up and down positions of In addition, a timing controller 140 for generating an amplification rate control signal.

The liquid crystal panel 110 includes a thin film transistor TFT formed at an intersection of the plurality of gate lines GL0 to GLn and the plurality of data lines DL1 to DLm, and a plurality of common voltages with the thin film transistor TFT. The liquid crystal cells Clc connected to any one of the lines VcomL1 to VcomLn and arranged in a matrix form, and the common voltage signal wiring 170 formed at right and left sides of the liquid crystal panel 110 are provided.

The gate lines GL0 to GLn and the data lines DL1 to DLm cross each other. The plurality of common voltage lines VcomL1 to VcomLn are arranged side by side alternately with the gate lines GL0 to GLn-1. The gate lines GL1 through GLn supply a scan signal, and the data lines DL1 through DLm supply a data signal. Unlike the other gate lines GL1 to GLn, the first gate line GL0 is for forming the storage capacitor Cst and supplies a gate low voltage. The common voltage lines VcomL1 to VcomLn supply reference voltages to the liquid crystal cells Clc. To this end, the common voltage lines VcomL1 to VcomLn are commonly connected to the common voltage signal line 170 formed at the left and right sides of the liquid crystal panel 110. The thin film transistor TFT causes the liquid crystal cell to charge a data signal from any one of the data lines DL1 to DLm in response to a scan signal from any one of the gate lines GL1 to GLn. The liquid crystal cell Clc includes a liquid crystal capacitor Clc composed of a pixel electrode Ep and a common electrode Ec formed on a lower substrate. The pixel electrode Ep is connected to the thin film transistor TFT, and the common electrode Ec is connected to any one of the common voltage lines VcomL1 to VcomLn. The liquid crystal cell Clc includes a storage capacitor Cst formed at an overlapping portion of the pixel electrode Ep and the previous gate line with an insulating layer therebetween. The storage capacitor Cst maintains the data signal charged in the liquid crystal capacitor Clc for one frame.

The timing controller 140 relays the digital video data R, G, and B from the graphics card (not shown) and supplies the data to the data driving circuit 120. In addition, the timing controller 140 controls the gate control signal GDC and the data driving circuit 120 to control the gate driving circuit 130 by using the vertical / horizontal synchronization signals V and H and the clock CLK. The data control signal DDC for controlling and the amplification rate control signal Φ for controlling the inversion amplification rate of the common voltage compensator 160 are generated. The data control signal DDC includes a source start pulse SSP, a source shift clock SSC, a source output signal SOE, a polarity signal POL, and the like. The gate control signal GDC includes a gate shift clock GSC, a gate output signal GOE, a gate start pulse GSP, and the like. The amplification rate control signal Φ is composed of a digital signal which varies according to the position of the liquid crystal cell to which the display data signal is supplied so that the inverted amplification rate of the feedback common voltage is different depending on the up and down positions of the liquid crystal panel. The amplification rate control signal Φ is determined to be different depending on the size of the liquid crystal panel and the distortion degree of the common voltage according to the up and down positions of the liquid crystal panel. In the case of the liquid crystal panel, two or three bits may be determined. In contrast, in the case of a large liquid crystal panel having a relatively large distortion of the common voltage according to the upper and lower positions of the liquid crystal panel, the liquid crystal panel may be 6 bits as shown in FIGS. It may be determined as 7 bits as in.

The data driving circuit 120 converts the digital data signal from the timing controller 140 into an analog data signal according to the data control signal DDC so that a gate high signal is supplied to the gate lines GL1 to GLn. An analog data signal for one horizontal line is supplied to the data lines DL1 to DLm each time.

The gate driving circuit 130 sequentially supplies scan signals to the gate lines GL1 to GLn in response to the gate control signal GDC from the timing controller 140.

The common voltage generator 150 receives a high potential power voltage to generate a common voltage Vcom and supplies the common voltage Vcom to the liquid crystal panel 110 and the common voltage compensator 160.

The common voltage compensator 160 controls the feedback common voltage Vcom-F / B from the liquid crystal panel 110, the common voltage Vcom from the common voltage generator 150, and the amplification factor from the timing controller 140. The inverted amplification factor of the feedback common voltage Vcom-F / B is differently adjusted according to the up and down positions of the liquid crystal panel 110 using the signal. The feedback common voltage Vcom-F / B fed back from the liquid crystal panel 110 has a horizontal period due to a capacitor coupling effect with a data signal when driven in a dot inversion manner as described above in the conventional art. It is shaken in the positive or negative direction in (H) units. In addition, as the common voltage line VcomL is farther from the data driving circuit 120, the current component of the common voltage supplied thereto is gradually decreased due to an increase in the line resistance of the common voltage signal wiring 170, and thus is supplied to the corresponding liquid crystal cell. The common voltage is relatively shaken up and down more than the common voltage supplied to the liquid crystal cell close to the data driving circuit 120 (see FIG. 7). Thus, the common voltage compensator 160 is positioned at the position of the display data. In response to the amplification factor control signal Φ from the timing controller 140 determined according to the feedback common voltage Vcom-F / B fed back from one lower end of the liquid crystal panel 110, the magnitude is the same and the phase is opposite in common. The voltage compensation signal Vcom 'is generated and supplied to the liquid crystal panel 110 through the common voltage signal line 170 to stabilize the common voltage. Here, the feedback common voltage Vcom-F / B may be fed back from the lower left and right sides of the liquid crystal panel 110 or may be fed back through a separate feedback dedicated line (not shown). The common voltage compensator 160 may be implemented in various forms. Hereinafter, the common voltage compensator 160 will be described in detail with reference to FIGS. 9 to 11.

9 is a circuit diagram illustrating a common voltage compensator of a liquid crystal display according to a first exemplary embodiment of the present invention.

Referring to FIG. 9, the common voltage compensator 160 of the liquid crystal display according to the first exemplary embodiment may include feedback common voltages Vcom-FB-R and Vcom-FB from the lower left and right sides of the liquid crystal panel 110. An inverting amplifier 164 for differentially amplifying the common voltage Vcom from the common voltage generator 150 and inverting the phase of the differential amplified signal to generate the common voltage compensation signal Vcom '. And an amplification factor converter 162 for converting the amplification factor of the inversion amplifier 164 in response to the amplification factor control signal Φ from the timing controller 140.

The inverting amplifier 164 is common from the inverting (−) input terminal and the common voltage generator 150 to which the feedback common voltages Vcom-FB-R and Vcom-FB-L are input from the lower left and right sides of the liquid crystal panel 110. Comprising a differential amplifier (OP-AMP) having a non-inverting (+) input terminal to which the voltage (Vcom) is input. At this time, the feedback common voltages Vcom-FB-R and Vcom-FB-L input to the negative input terminal swing up and down based on the common voltage Vcom by capacitor coupling with the data signal. It will have an alternating current wave. Actually, the feedback common voltage Vcom-FB input to the negative input terminal is obtained from the first feedback common voltage Vcom-FB-L from the lower left portion of the liquid crystal panel 110 and the lower right portion of the liquid crystal panel 110. An average value of the second feedback common voltages Vcom-FB-R. Meanwhile, the feedback common voltage Vcom-FB may be a voltage value fed back from one side of the liquid crystal panel 110 rather than both sides of the lower end portion. The common voltage Vcom from the common voltage generator 150 input to the positive input terminal is a direct current. The inverting amplifier 164 receives the feedback common voltages Vcom-FB-R and Vcom-FB-L and the common voltage Vcom from the common voltage generator 150 from the lower left and right sides of the liquid crystal panel 110. The differential amplification and inverting the phase of the differential amplified signal generate a common voltage compensation signal Vcom '.

The amplification factor converter 162 includes first and second input resistors R1 and R2 connected in parallel to the negative input terminal of the inverting amplifier 164, the negative input terminal and the output terminal of the inverting amplifier 164. The first to sixth negative feedback resistors Rf1 to Rf6 and the first to sixth negative feedback resistors Rf1 to Rf6 connected in series between (n1) are respectively connected in parallel to each other from the timing controller 140. The first to sixth switches S1 to S6 are shorted by switching in response to the amplification rate control signal.

The first common capacitor is connected between the first input resistor R1 and the input terminal of the feedback common voltage Vcom-F / BR to couple the feedback common voltage Vcom-F / BR to the first input resistor, thereby providing a feedback common voltage. Remove the DC noise included in (Vcom-F / BR). A second capacitor is connected between the second input resistor R2 and the input terminal of the feedback common voltage Vcom-F / BL to couple the feedback common voltage Vcom-F / BL and the second input resistor to provide feedback common. Remove the DC noise included in the voltage (Vcom-F / BL).

The first to sixth negative feedback resistors Rf1 to Rf6 are connected between the first negative feedback resistor Rf1 connected between the output terminal n1 and the node a and between the node a and the node b. The second negative feedback resistor Rf2, the third negative feedback resistor Rf3 connected between the node b and the node c, and the fourth negative feedback connected between the node c and the node d. A resistor Rf4 and a fifth negative feedback resistor Rf5 connected between the node d and the node e and a negative terminal connected between the node e and the negative input terminal of the inversion amplifier 150. It consists of six negative feedback resistors (Rf6). The resistance values of the first to sixth negative feedback resistors Rf1 to Rf6 have different weight values to implement various amplification rates. The first to sixth switches S1 to S6 include a first switch S1 connected to both ends of the first negative feedback resistor Rf1, and a second switch connected to both ends of the second negative feedback resistor Rf2. S2), the third switch S3 connected to both ends of the third negative feedback resistor Rf3, the fourth switch S4 connected to both ends of the fourth negative feedback resistor Rf4, and the fifth negative feedback. The fifth switch S5 is connected to both ends of the resistor Rf5, and the sixth switch S6 is connected to both ends of the sixth negative feedback resistor Rf6. The first to sixth switches S1 to S6 are switched in response to the amplification rate control signal .phi. From the timing controller 140 to short each end of each resistor. The amplification rate control signal? Can be set to a six bit digital signal in this embodiment, each bit corresponding to D1 to D6 shown in FIG. The 6-bit digital signal is embedded in the timing controller 140 with 64 different values depending on the vertical position of the liquid crystal panel. When the logic value of the digital signal is "1", the switch is closed and both ends of the corresponding resistor are shorted, and when "0", the switch is opened to form a current path through the resistor. For example, when the logic value of the digital signal is “111111”, all of the first to sixth switches S1 to S6 are closed, and both ends of the first to sixth negative feedback resistors Rf1 to Rf6 are shorted. If the logic value of the digital signal is "000000", all of the first to sixth switches S1 to S6 are opened. In addition, when the logic value of the digital signal is "011111", only the sixth switch S6 is opened and the first to fifth switches S1 to S5 are closed. Here, the value of the first negative feedback resistor Rf1 is 100 kV, the value of the second negative feedback resistor Rf2 is 200 kV, the third negative feedback resistor Rf3 is 400 kV, the fourth negative feedback resistor Rf4 is 800 kV, If the fifth negative feedback resistor Rf5 is 1600 kV and the sixth negative feedback resistor Rf6 is 3200 kV, the first to sixth negative feedback resistors Rf1 to Rf6 are set when the logic value of the digital signal is "111111". When the combined resistance value of 0 is 0 Ω and the logical value of the digital signal is “000000”, the combined resistance value of the first to sixth negative feedback resistors Rf1 to Rf6 is 6300 ,, and the logical value of the digital signal is “011111”. In this case, the combined resistance values of the first to sixth negative feedback resistors Rf1 to Rf6 are 3200 kW. The synthesized resistance value determines the inversion amplification rate of the common voltage compensator 160 and is determined differently depending on the vertical position of the liquid crystal panel 110. That is, in the above example, the synthetic resistance value is 0 에는 when the data signal is supplied to the liquid crystal cells in the horizontal direction positioned at the top end of the liquid crystal panel 110, and the horizontal resistance is positioned in the center of the liquid crystal panel 110. When the data signal is supplied to the liquid crystal cells, the data signal may be determined to be 3200 Hz, and 6300 Hz when the data signal is supplied to the liquid crystal cells in the horizontal direction positioned at the lowermost portion of the liquid crystal panel 110. The timing controller 140 determines the position of the display data using the vertical / horizontal synchronization signals V and H and the clock CLK, and compensates the common voltage for the 6-bit amplification rate control signal Φ corresponding to the determination result. Supply to the unit 160. The first to sixth switches S1 to S6 are switched according to the amplification rate control signal Φ, and the negative feedback resistance value is determined according to the position of the display data in the liquid crystal panel 110 as in the above-described example. In addition, the feedback common voltage Vcom-F / B is inverted and amplified according to the determined negative feedback resistance value and supplied to the upper left and right ends of the liquid crystal panel 110 through the common voltage signal line 170 to be varied according to the position of the display data. The distortion of the common voltage Vcom may be minimized.

10 is a circuit diagram illustrating a common voltage compensator of a liquid crystal display according to a second exemplary embodiment of the present invention.

Referring to FIG. 10, the common voltage compensator 160 of the liquid crystal display according to the second exemplary embodiment may include feedback common voltages Vcom-FB-R and Vcom-FB from the lower left and right sides of the liquid crystal panel 110. An inverting amplifier 264 for differentially amplifying the common voltage Vcom from the common voltage generator 150 and inverting the phase of the differential amplified signal to generate the common voltage compensation signal Vcom '. And an amplification factor converter 262 for converting the amplification factor of the inversion amplifier 264 in response to the amplification factor control signal? From the timing controller 140.

The inversion amplifier 264 has a common voltage from the negative input terminal and the common voltage generator 150 to which the feedback common voltages Vcom-FB-R and Vcom-FB-L are input from the lower left and right sides of the liquid crystal panel 110. It consists of a differential amplifier (OP-AMP) having a positive input terminal to which (Vcom) is input. At this time, the feedback common voltages Vcom-FB-R and Vcom-FB-L input to the (-) input terminal swing up and down based on the common voltage Vcom by capacitor coupling with the data signal. It will have an alternating current wave. Actually, the feedback common voltage Vcom-FB input to the negative input terminal is obtained from the first feedback common voltage Vcom-FB-L from the lower left portion of the liquid crystal panel 110 and the lower right portion of the liquid crystal panel 110. An average value of the second feedback common voltages Vcom-FB-R. Meanwhile, the feedback common voltage Vcom-FB may be a voltage value fed back from one side of the liquid crystal panel 110 rather than both sides of the lower end portion. The common voltage Vcom from the common voltage generator 150 input to the positive input terminal is a direct current. The inverting amplifier 264 controls the feedback common voltages Vcom-FB-R and Vcom-FB-L and the common voltage Vcom from the common voltage generator 150 from the lower left and right sides of the liquid crystal panel 110. The differential amplification and inverting the phase of the differential amplified signal generate a common voltage compensation signal Vcom '.

The amplification factor converter 262 includes third and fourth input resistors R3 and R4 connected in parallel to the negative input terminal of the inverting amplifier 264, the negative input terminal and the output terminal of the inverting amplifier 264. The seventh to twelfth negative feedback resistors Rf7 to Rf12 connected in parallel between (n2) and the seventh to twelfth negative feedback resistors Rf7 to Rf12 are connected in series to each other from the timing controller 140. Switching in response to the amplification rate control signal Φ to form or block current paths of the branches a to f respectively formed between the negative input terminal and the output terminal n2 of the inversion amplifier 264; Twelfth switches S7 to S12 are provided.

A third capacitor is connected between the third input resistor R3 and the input terminal of the feedback common voltage Vcom-F / BR to couple the feedback common voltage Vcom-F / BR to the third input resistor to couple the feedback common voltage. Remove the DC noise included in (Vcom-F / BR). A fourth capacitor is connected between the fourth input resistor R4 and the input terminal of the feedback common voltage Vcom-F / BL to couple the feedback common voltage Vcom-F / BL and the fourth input resistor to provide feedback common. Remove the DC noise included in the voltage (Vcom-F / BL).

The seventh to twelfth negative feedback resistors Rf7 to Rf12 include a seventh negative feedback resistor Rf7 and a phase inversion unit connected between the negative input terminal of the inverting amplifier 264 and the seventh switch S7. The eighth negative feedback resistor Rf8 connected between the (-) input terminal of the 264 and the eighth switch S8, and the negative input terminal of the phase inversion unit 264 and the ninth switch S9 The ninth negative feedback resistor Rf9, the tenth negative feedback resistor Rf10 connected between the (-) input terminal of the phase inversion unit 264, and the tenth switch S10, and the phase inversion unit 264 ( The eleventh negative feedback resistor Rf11 connected between the input terminal and the eleventh switch S11, and the twelfth negative feedback connected between the negative input terminal of the phase inversion unit 264 and the twelfth switch S12. It consists of a resistor Rf12. The resistance values of the seventh to twelfth negative feedback resistors Rf7 to Rf12 have different weight values to implement various amplification rates. The seventh to twelfth switches S7 to S12 include a seventh switch S7 connected between the seventh negative feedback resistor Rf7 and the output terminal n2, and an eighth negative feedback resistor Rf8 and the output terminal n2. The eighth switch S8 connected between the ninth switch S9 and the ninth switch S9 connected between the ninth negative feedback resistor Rf9 and the output terminal n2, and the tenth negative feedback resistor Rf10 and the output terminal n2. The eleventh switch S11 connected between the eleventh switch S11 and the eleventh negative feedback resistor Rf11 and the output terminal n2, and the twelfth negative feedback resistor Rf12 and the output terminal n2. It consists of a 12th switch S12 connected between them. The seventh to twelfth switches S7 to S12 are switched in response to the amplification rate control signal Φ from the timing controller 140, respectively, between the negative input terminal and the output terminal n2 of the inversion amplifier 264. It forms or blocks the current path of the branches a to f formed. The amplification rate control signal? Can be set to a six bit digital signal in this embodiment, each bit corresponding to D7 to D12 shown in FIG. The 6-bit digital signal is embedded in the timing controller 140 with 64 different values depending on the vertical position of the liquid crystal panel. When the logic value of the digital signal is "1", the switch is closed to form a current path to the corresponding ground. When "0", the switch is opened to block the current path to the relevant ground. For example, if the logic value of the digital signal is “111111”, all of the seventh to twelfth switches S7 to S12 are closed to form current paths of all branches a to f. If the logic value of the digital signal is "100000", the twelfth switch S12 is closed to form a current path of the branch f, and the seventh to eleventh switches S7 to S11 are opened to open the remaining branches ( The current paths a to e are blocked. In addition, when the logic value of the digital signal is "010000", the eleventh switch S11 is closed to form a current path of the feeder e, and the seventh to tenth and twelfth switches S7 to S10 and S12 are all The current paths of the remaining branches a to d and f are blocked. Here, the seventh negative feedback resistor Rf7 is 100 kV, the eighth negative feedback resistor Rf8 is 200 kV, the ninth negative feedback resistor Rf9 is 400 kV, the tenth negative feedback resistor Rf10 is 800 kV, When the eleventh negative feedback resistor Rf11 is 1600 kV and the twelfth negative feedback resistor Rf12 is 3200 kPa, the seventh to twelfth negative feedback resistors Rf7 to Rf12 are set when the logic value of the digital signal is 111111. The combined resistance value of is about 50.8 kΩ, and when the logic value of the digital signal is "100000", the combined resistance value of the seventh to twelfth negative feedback resistors Rf7 to Rf12 is 3200 kohms, and the logical value of the digital signal is " 010000 ", the combined resistance value of the seventh to twelfth negative feedback resistors Rf7 to Rf12 is 1600 k ?. The synthesized resistance value determines the inversion amplification rate of the common voltage compensator 160 and is determined differently depending on the vertical position of the liquid crystal panel 110. That is, in the above example, the synthetic resistance value is 50.8 에는 when the data signal is supplied to the liquid crystal cells in the horizontal direction positioned at the top end of the liquid crystal panel 110, and the horizontal direction is positioned in the center of the liquid crystal panel 110. In the case of supplying the data signal to the liquid crystal cells of the liquid crystal cell of 1600Ω, the liquid crystal cells of the horizontal direction located in the lowermost portion of the liquid crystal panel 110 may be determined to be 3200Ω. The timing controller 140 determines the position of the display data using the vertical / horizontal synchronization signals V and H and the clock CLK, and compensates the common voltage for the 6-bit amplification rate control signal Φ corresponding to the determination result. Supply to the unit 160. The seventh to twelfth switches S7 to S12 are switched according to the amplification rate control signal Φ, and the negative feedback resistance value is determined according to the position of the display data in the liquid crystal panel 110 as in the above-described example. In addition, the feedback common voltage Vcom-F / B is inverted and amplified according to the determined negative feedback resistance value and supplied to the upper left and right ends of the liquid crystal panel 110 through the common voltage signal line 170 to be varied according to the position of the display data. The distortion of the common voltage Vcom may be minimized.

11 is a block diagram illustrating a common voltage compensator of a liquid crystal display according to a third exemplary embodiment of the present invention.

Referring to FIG. 11, the common voltage compensator 160 of the liquid crystal display according to the third exemplary embodiment may provide feedback common voltages Vcom-FB-R and Vcom-FB from the lower left and right sides of the liquid crystal panel 110. -L) and an inverted amplifier 364 for differentially amplifying the common voltage Vcom from the common voltage generator 150 and inverting the phase of the differential amplified signal to generate the common voltage compensation signal Vcom '. And an amplification factor converter 362 for converting the amplification factor of the inversion amplifier 364 in response to the amplification factor control signal? From the timing controller 140.

The inverting amplifier 364 has a common voltage from the negative input terminal and the common voltage generator 150 to which the feedback common voltages Vcom-FB-R and Vcom-FB-L are input from the lower left and right sides of the liquid crystal panel 110. It consists of a differential amplifier (OP-AMP) having a positive input terminal to which (Vcom) is input. At this time, the feedback common voltages Vcom-FB-R and Vcom-FB-L input to the (-) input terminal swing up and down based on the common voltage Vcom by capacitor coupling with the data signal. It will have an alternating current wave. Actually, the feedback common voltage Vcom-FB input to the negative input terminal is obtained from the first feedback common voltage Vcom-FB-L from the lower left portion of the liquid crystal panel 110 and the lower right portion of the liquid crystal panel 110. An average value of the second feedback common voltages Vcom-FB-R. Meanwhile, the feedback common voltage Vcom-FB may be a voltage value fed back from one side of the liquid crystal panel 110 rather than both sides of the lower end portion. The common voltage Vcom from the common voltage generator 150 input to the positive input terminal is a direct current. The inverting amplifier 364 receives the feedback common voltages Vcom-FB-R and Vcom-FB-L and the common voltage Vcom from the common voltage generator 150 from the lower left and right sides of the liquid crystal panel 110. The differential amplification and inverting the phase of the differential amplified signal generate a common voltage compensation signal Vcom '.

The amplification rate converter 362 stores a amplification rate control signal Φ from the timing controller 140 and generates a plurality of switch control signals Φ ′ corresponding thereto, and an amplification rate control signal Φ. Memory 364 for storing a plurality of switch control signals Φ 'corresponding to the interface, and an interface for changing the plurality of switch control signals Φ' stored in the memory 364 according to external data A0 and A1. The circuit 365, a decoder 366 for selectively switching the plurality of switch elements S0 to S127 in accordance with the switch control signal Φ 'from the register 363, and the plurality of switch elements S0 to S127. The gate G of the kth switch element Sk is connected to the kth output pin Pk of the decoder 366 and the drain D is connected to the common node. the switching unit 367 connected to n0) and the source S connected to the k-th node nk, and a switch element adjacent to each other. Are connected between the source S and the source S of the S0 to S127 and the connected resistors R are connected in series with each other between the negative input terminal and the output terminal n127 of the inverting amplifier 364. Resistor strings 368 connected to each other, and fifth and sixth input resistors R5 and R6 connected in parallel to the negative input terminal of the inverting amplifier 364.

The fifth capacitor is connected between the fifth input resistor R5 and the input terminal of the feedback common voltage Vcom-F / BR to couple the feedback common voltage Vcom-F / BR to the fifth input resistor to couple the feedback common voltage. Remove the DC noise included in (Vcom-F / BR). The sixth capacitor is connected between the sixth input resistor R6 and the input terminal of the feedback common voltage Vcom-F / BL to couple the feedback common voltage Vcom-F / BL and the sixth input resistor to thereby provide a feedback common voltage. Remove the DC noise included in (Vcom-F / BL).

The register 363 stores the serial control data signal SDA and the serial control clock signal SCL, which are the amplification rate control signal Φ supplied from the timing controller 140, and correspond to a plurality of switch control signals Φ ′ corresponding to the serial control data signal SDA. Occurs. To this end, the register 363 is supplied to the memory 364 using the serial control data signal SDA as a read address, and receives a switch control signal Φ ′ output from the memory 364 according to the read address. . In the timing controller 140, a 7-bit control signal Φ that varies according to the up and down positions of the liquid crystal panel 110 in which current data is displayed is embedded. Accordingly, the switch control signal? 'Generated by the register 363 is composed of a 7 bit digital signal.

The memory 364 is a nonvolatile memory capable of updating and erasing data, for example, the position of the display data on the liquid crystal panel, including an electrically erasable programmable read only memory (EEPROM) and / or an extended display identification data ROM (EDID ROM). The amplification rate control signal .phi. That varies according to the &lt; RTI ID = 0.0 &gt; and &lt; / RTI &gt; The stored switch control signal Φ ′ may be updated by electrical signals A0 and A1 applied from an external system through the interface circuit 365.

The interface circuit 365 is designed in accordance with a communication standard protocol standard such as I ² C. The external system can read or modify data stored in the memory 364 through the interface circuit 365. That is, the amplification rate control signal Φ and the switch control signal Φ 'stored in the memory 364 are required to be updated for reasons such as process change and difference between the applied models, and the user wants to update the control data Φ. , 'Is entered through the external system. These control data? And? 'Are converted into electrical signals A0 and A1 by a ROM recorder (not shown) and stored in the memory 364 through the interface circuit 365.

The decoder 366 receives 128 different switch control signals Φ ', that is, 7-bit digital control signals from the register 363 according to the up and down positions of the liquid crystal panel on which display data is located, and decodes the corresponding output pins. Outputs the switching signal through. The decoder 366 includes 128 output pins P0 to P127 to correspond to 7-bit digital control signals. Each of the output pins P0 to P127 is connected one-to-one with gates of the plurality of switch elements S0 to S127 of the switching unit 367. The decoder 366 supplies a switching signal to the gate of the corresponding switch element according to the 7-bit switch control signal .phi. 'So that the switch element is switched.

The switching unit 367 is composed of a plurality of switch elements S0 to S127. In particular, a thin film transistor is used as the switch element. Of the plurality of switch elements S0 to S127, the gate G of the k (k is 0 or more and a natural number of 127 or less) th switch element Sk is connected to the kth output pin Pk of the decoder 366 and drained. (D) is connected to the common node n0 and the source S is connected to the k-th node nk. By the switching action of the switching unit 367, the combined resistance value of the resistance string 368 connected in series between the negative input terminal n0 of the inverting amplifier 364 and the output node n127 is determined. The inversion amplification factor of the common voltage compensator 160 is determined.

The resistor string 368 includes a plurality of resistors R connected in series between the negative input terminal node n0 and the output node n127 of the inverting amplifier 364. Multiple series resistors have the same magnitude. As illustrated in FIG. 11, 126 other nodes n1 to n126 are formed between the resistor R and the resistor R in addition to the node n0 and the output node n127, respectively. It is connected one-to-one with the source S of S126. The negative input terminal node n0 of the inversion amplifier 364 is connected to the source S of the switch element S0, and the output node n127 is connected to the source S of the switch element S127.

 Here, assuming that the resistance value of all the resistors R constituting the resistance string 368 is 10 kV, when the logic value of the digital signal is "1111111", it is switched by the output pin P127 of the decoder 366. When (S127) is turned on and the combined resistance value of the resistor string 368 is determined to be 0Ω, and the logic value of the digital signal is "0000000", the switch S0 is switched by the output pin P0 of the decoder 366. Is turned on and the combined resistance value of the resistor string 368 is determined to be 1270 kV. When the logic value of the digital signal is "0111111", the switch S63 is turned on by the output pin P63 of the decoder 366. Thus, the combined resistance value of the resistance string 368 is determined to be 640 kV. The synthesized resistance value determines the inversion amplification rate of the common voltage compensator 160 and is determined differently depending on the vertical position of the liquid crystal panel 110. That is, in the above example, the synthetic resistance value is 0 에는 when the data signal is supplied to the liquid crystal cells in the horizontal direction positioned at the top end of the liquid crystal panel 110, and the horizontal resistance is positioned in the center of the liquid crystal panel 110. In the case of supplying the data signal to the liquid crystal cells, it may be determined to be 640 mV, and in the case of supplying the data signal to the liquid crystal cells in the horizontal direction positioned at the bottom end of the liquid crystal panel 110. The timing controller 140 determines the position of the display data using the vertical / horizontal synchronization signals V and H and the clock CLK, and compensates the common voltage for the 7-bit amplification rate control signal Φ corresponding to the determination result. Supply to the unit 160. The plurality of switch elements S0 to S127 are switched according to the amplification rate control signal Φ so that the negative feedback resistance value is determined according to the position of the display data in the liquid crystal panel 110 as in the above-described example. In addition, the feedback common voltage Vcom-F / B is inverted and amplified according to the determined negative feedback resistance value and supplied to the upper left and right ends of the liquid crystal panel 110 through the common voltage signal line 170 to be varied according to the position of the display data. The distortion of the common voltage Vcom may be minimized.

12 to 14 illustrate changes in amplification factor according to positions of display data in a liquid crystal panel.

12 shows the inversion amplification factor of the feedback common voltage Vcom-F / B as the display data is positioned below the liquid crystal panel 110 by a plurality of resistors R having the same resistance value as in the third embodiment. This is shown to increase linearly.

FIG. 13 shows a feedback common voltage as display data is positioned below the liquid crystal panel 110 by a plurality of resistors Rf1 to Rf6 and Rf7 to Rf12 having different resistance values as in the first and second embodiments. The inversion amplification ratio of Vcom-F / B is increased, but the inversion amplification ratio is nonlinearly increased in consideration of the structure of the common voltage signal wiring 170 and the distribution of the resistance values.

FIG. 14 illustrates a case in which a separate feedback dedicated line (not shown) is formed on the upper and lower sides of the liquid crystal panel 110 to apply the inverted and amplified feedback common voltage to the upper and lower portions of the liquid crystal panel 110 in the same manner. The change in amplification factor is shown.

Meanwhile, although the embodiment of the present invention has been described using the IPS mode as an example, the technical idea of the present invention is not limited thereto, and the present invention can be applied to a VA (Verticle Alignment) mode, a twisted nematic (TN) mode, and the like. In addition, the technical idea of the present invention is applicable not only to the case of driving by the dot inversion method but also to the case of driving by all inversion methods.

As described above, the liquid crystal display device and the driving method thereof according to the present invention minimize the distortion of the common voltage by supplying to the liquid crystal panel by differently adjusting the inverted amplification factor of the feedback common voltage according to the position of the display data in the liquid crystal panel to minimize the distortion of the common voltage. This deterioration can be prevented.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (22)

A liquid crystal panel; A common voltage generator for generating a common voltage supplied to the liquid crystal panel; A timing controller for generating a different amplification rate control signal according to the position of the display data in the liquid crystal panel; And And a common voltage compensator for adjusting the inverted amplification factor of the feedback common voltage from the liquid crystal panel to the liquid crystal panel according to the position of the display data on the liquid crystal panel based on the common voltage in response to the amplification rate control signal. Liquid crystal display characterized in that. The method of claim 1, The common voltage compensator, An inverting amplifier for differentially amplifying the feedback common voltage from the liquid crystal panel and the common voltage from the common voltage generator and inverting the phase of the differentially amplified signal; And And an amplification ratio converter for converting the amplification ratio of the inversion amplifier in response to the amplification ratio control signal from the timing controller. The method of claim 2, The inversion amplifier, And a differential amplifier for inverting and amplifying the feedback common voltage input through the inverting input terminal based on the common voltage input through the non-inverting input terminal. The method of claim 3, wherein The liquid crystal panel includes a color filter array substrate and a thin film transistor array substrate facing the color filter array substrate, and the feedback common voltage is fed back from a common voltage signal line formed on one side of the thin film transistor array substrate. The method of claim 4, wherein The common voltage signal lines are formed to be separated from each other in the vertical direction on each of the left and right sides of the thin film transistor substrate, and the feedback common voltage includes first and second feedback common voltages fed back from both lower ends of the common voltage signal lines, respectively. Liquid crystal display characterized in that. The method of claim 5, wherein The amplification conversion unit, A first input resistor connected to the inverting input terminals of the differential amplifier in parallel with each other and having a first input resistor to which the first feedback common voltage is applied and a second input resistor to which the second feedback common voltage is applied; First to sixth negative feedback resistors connected in series between an inverting input terminal of the differential amplifier and an output terminal of the differential amplifier; And And first to sixth switches connected in parallel with the first to sixth negative feedback resistors, respectively, and switched in response to an amplification rate control signal from the timing controller to determine the combined resistance values of the negative feedback resistors. A liquid crystal display device. The method of claim 6, And said amplification control signal is a 6-bit digital signal. The method of claim 6, And a resistance value of the first to sixth negative feedback resistors is different from each other. The method of claim 5, wherein The amplification conversion unit, A third input resistor connected in parallel to the inverting input terminals of the differential amplifier and having a third input resistor to which the first feedback common voltage is applied and a fourth input resistor to which the second feedback common voltage is applied; Seventh to twelfth negative feedback resistors connected in parallel between the inverting input terminal of the differential amplifier and the output terminal of the differential amplifier; And Seventh to twelfth to be connected in series between the seventh to twelfth negative feedback resistors and the output terminals of the differential amplifiers to switch in response to an amplification rate control signal from the timing controller to determine a combined resistance value of the negative feedback resistors; 12. A liquid crystal display device comprising the switch. The method of claim 9, And said amplification control signal is a 6-bit digital signal. The method of claim 9, And the resistance values of the seventh to twelfth negative feedback resistors are different from each other. The method of claim 5, wherein The amplification conversion unit, A fifth input resistor connected in parallel to the inverting input terminals of the differential amplifier and to which the first feedback common voltage is applied and the sixth input resistor to which the second feedback common voltage is applied; A memory for storing a plurality of switch control signals corresponding to the amplification rate control signal; A register for storing an amplification rate control signal from the timing controller and generating a switch control signal corresponding thereto; A decoder for decoding the switch control signal from the register; A plurality of switch elements switched according to the decoded switch control signal; And And a resistance string including a plurality of resistors connected in series between the inverting input terminal of the differential amplifier and the output terminal of the differential amplifier and having a combined resistance value determined according to the switching of the switching unit. The method of claim 12, And the amplification control signal and the switch control signal are 7-bit digital signals. The method of claim 13, And 128 output pins of the decoder, wherein the plurality of switch elements comprise thin film transistors. The method of claim 14, Wherein the gates of the thin film transistors are connected one-to-one with the output pins of the decoder, the drains are commonly connected to the inverting input terminal of the differential amplifier, and the sources are connected to the resistor string. The method of claim 15, And one or more resistors constituting the resistor string are disposed between the source and the source of the thin film transistors adjacent to the resistor string. The method of claim 16, And a resistance value of the resistors is the same. The method of claim 12, And an interface circuit for changing the plurality of switch control signals stored in the memory according to external data. Supplying a common voltage to the liquid crystal panel and feeding back a feedback common voltage from the liquid crystal panel; Generating a second amplification rate control signal according to a position of display data in the liquid crystal panel; And And in response to the amplification rate control signal, adjusting the inverted amplification factor of the feedback common voltage to the liquid crystal panel according to the position of the display data on the liquid crystal panel based on the common voltage. A method of driving a liquid crystal display device. The method of claim 19, In the third step, And converting the inverted amplification factor in response to the amplification factor control signal, inverting and amplifying the feedback common voltage based on the common voltage according to the converted amplification factor, and supplying the inverted amplification factor to the liquid crystal panel together with the display data. Method of driving display device. The method of claim 20, And wherein the amplification rate control signal is a digital signal, the bit number of which is increased in proportion to the size of the liquid crystal panel. The method of claim 21, And the amplification control signal is 6 bits or 7 bits.

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