KR20080010128A - Method for manufacturing of semiconductor device - Google Patents

Method for manufacturing of semiconductor device Download PDF

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KR20080010128A
KR20080010128A KR1020060070193A KR20060070193A KR20080010128A KR 20080010128 A KR20080010128 A KR 20080010128A KR 1020060070193 A KR1020060070193 A KR 1020060070193A KR 20060070193 A KR20060070193 A KR 20060070193A KR 20080010128 A KR20080010128 A KR 20080010128A
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South Korea
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region
gate
forming
semiconductor device
manufacturing
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KR1020060070193A
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Korean (ko)
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박지선
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주식회사 하이닉스반도체
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Priority to KR1020060070193A priority Critical patent/KR20080010128A/en
Publication of KR20080010128A publication Critical patent/KR20080010128A/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts

Abstract

A method of manufacturing a semiconductor device is provided to improve a process margin by securing the critical dimension in major axis direction of an active area without an additional process. A method of manufacturing a semiconductor device includes the step of: forming a device isolation film(115) which defines an active area(113) on a semiconductor substrate(111); blocking a predetermined bitline contact area and forming a recess gate area(117) by etching the semiconductor substrate with a photolithography process using a photosensitive film pattern which exposes the area adjacent to the predetermined bit line contact area; and forming a first gate(119b) and a second gate(119c) at the upper part of the recess gate area.

Description

반도체 소자의 제조방법{METHOD FOR MANUFACTURING OF SEMICONDUCTOR DEVICE}Manufacturing method of semiconductor device {METHOD FOR MANUFACTURING OF SEMICONDUCTOR DEVICE}

도 1은 종래기술에 따른 반도체 소자를 도시한 평면도.1 is a plan view showing a semiconductor device according to the prior art.

도 2는 본 발명에 따른 반도체 소자를 도시한 평면도.2 is a plan view showing a semiconductor device according to the present invention.

< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>

111 : 반도체 기판 113 : 활성영역111 semiconductor substrate 113 active region

115 : 소자분리막 117 : 리세스 게이트 영역115: device isolation layer 117: recess gate region

119a, 119b : 게이트119a, 119b: gate

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 리세스 게이트 영역을 형성하기 위한 식각공정시 활성영역 에지부에 가해지는 어택(attack)을 방지할 수 있는 반도체 소자의 제조방법에 관한 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device capable of preventing an attack applied to an edge portion of an active region during an etching process for forming a recess gate region.

반도체 소자 제조에 있어 일반적인 게이트 배선 형성 방법은 게이트를 평탄한 활성영역 위에 형성하는 방법으로, 패턴크기의 축소화에 의해 게이트 채널길이가 점점 작아지고 이온주입 도핑 농도 증가에 따라 전기장 증가에 기인한 접합누설 에 의해 소자의 리프레시 특성을 확보하기가 어렵다.In the manufacture of semiconductor devices, a common gate wiring forming method is to form a gate over a flat active region.As a result, the gate channel length becomes smaller due to the reduction of the pattern size, and the junction leakage due to the electric field increases due to the ion implantation doping concentration. As a result, it is difficult to secure the refresh characteristics of the device.

이를 개선하기 위한 게이트 배선 형성 방법으로 활성영역을 리세스 식각한 후 게이트를 형성하는 리세스 게이트(Recess Gate) 공정이 대안으로 적용될 수 있다.As a gate wiring forming method for improving this, a recess gate process of forming a gate after recess etching the active region may alternatively be applied.

리세스 게이트 공정을 적용하여 채널길이 증가 및 이온주입 도핑농도 감소가 가능하여 소자의 리프레시 특성이 크게 개선된다.By applying the recess gate process, the channel length and the ion implantation doping concentration can be reduced, which greatly improves the refresh characteristics of the device.

도 1은 종래기술에 따른 반도체 소자를 도시한 평면도이다.1 is a plan view showing a semiconductor device according to the prior art.

도 1을 참조하면, 소자분리막(15)에 의해 정의된 반도체 기판(11)의 활성영역(13) 상부에 라인(line) 형태의 제 1 및 제 2 게이트(17b, 17c)가 형성되어 있다. Referring to FIG. 1, first and second gates 17b and 17c having a line shape are formed on an active region 13 of a semiconductor substrate 11 defined by an isolation layer 15.

그리고, 상기 제 1 및 제 2 게이트(17b, 17c) 하부의 상기 활성영역(13)에는 리세스 게이트 영역(미도시)이 상기 제 1 및 제 2 게이트(17b, 17c)와 동일한 라인(line) 형태로 형성되어 있다.In addition, a recess gate region (not shown) has the same line as the first and second gates 17b and 17c in the active region 13 below the first and second gates 17b and 17c. It is formed in the form.

상술한 종래기술에 따른 반도체 소자의 제조방법은, 상기 활성영역(13)의 장축방향에 대한 선폭(Critical Dimension;CD) 확보 및 공정 마진 부족으로 제 3 게이트(17a) 및 제 4 게이트(17d) 하부의 리세스 게이트 영역 형성을 위한 식각공정시 상기 활성영역(13)의 에지부가 어택(attack)을 받는 경우가 발생하는 문제점이 있다. In the above-described method of manufacturing a semiconductor device, the third gate 17a and the fourth gate 17d are secured by securing a critical dimension (CD) in the long axis direction of the active region 13 and lacking a process margin. There is a problem in that an edge portion of the active region 13 receives an attack during an etching process for forming a recessed gate region below.

본 발명은 상기와 같은 문제점을 해결하기 위하여 창출된 것으로, 리세스 게 이트 영역을 링(ring) 형태로 형성함으로써 리세스 게이트 영역을 형성하기 위한 식각공정시 활성영역 에지부에 어택(attack)이 가해지는 현상을 방지할 수 있는 반도체 소자의 제조방법을 제공하는데 그 목적이 있다. The present invention has been made to solve the above problems, and by forming the recess gate region in a ring shape, an attack is formed at the edge of the active region during the etching process for forming the recess gate region. It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of preventing an applied phenomenon.

상기한 목적을 달성하기 위한 본 발명의 반도체 소자의 제조방법은, The semiconductor device manufacturing method of the present invention for achieving the above object,

반도체 기판에 활성영역을 정의하는 소자분리막을 형성하는 단계와,Forming an isolation layer defining an active region on the semiconductor substrate;

비트라인 콘택 예정영역은 차단시키고, 상기 비트라인 콘택 예정영역과 인접한 소정영역을 노출시키는 감광막 패턴을 이용한 사진 식각공정으로 상기 반도체 기판을 식각하여 리세스 게이트 영역을 형성하는 단계와,Forming a recess gate region by etching the semiconductor substrate by a photolithography process using a photoresist pattern that blocks a bit line contact region and exposes a predetermined region adjacent to the bit line contact region;

상기 리세스 게이트 영역 상부에 제 1 게이트, 제 2 게이트를 형성하는 단계Forming a first gate and a second gate on the recess gate region

를 포함하는 것을 특징으로 한다.Characterized in that it comprises a.

그리고, 본 발명은 리세스 게이트 영역은 링(ring) 형태로 형성하는 것과,In the present invention, the recess gate region is formed in a ring shape,

리세스 게이트 영역의 장축방향 선폭(CD)은 활성영역과 제 1 및 제 2 게이트 예정영역이 오버랩(overlap)되는 영역 사이의 거리와 동일하게 형성하는 것The long axis line width CD of the recess gate region is equal to the distance between the active region and the region where the first and second gate predetermined regions overlap.

을 특징으로 한다. It is characterized by.

이하, 첨부한 도면을 참조하여 본 발명의 실시예에 대해 상세히 설명하고자 한다. Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

도 2는 본 발명에 따른 반도체 소자를 도시한 평면도이다.2 is a plan view showing a semiconductor device according to the present invention.

도 2를 참조하면, 반도체 기판(111)에 활성영역(113)을 정의하는 소자분리막(115)을 형성한다. Referring to FIG. 2, an isolation layer 115 defining an active region 113 is formed on a semiconductor substrate 111.

그 다음, 상기 반도체 기판(111) 상부에 감광막(미도시)을 형성한다.Next, a photosensitive film (not shown) is formed on the semiconductor substrate 111.

그 다음, 비트라인 콘택 예정영역은 차단시키고, 상기 비트라인 콘택 예정영역과 인접한 소정영역을 노출시키는 마스크로 상기 감광막을 노광 및 현상하여 감광막 패턴을 형성한다.Next, the bit line contact predetermined region is blocked, and the photosensitive layer is exposed and developed with a mask that exposes a predetermined region adjacent to the bit line contact predetermined region to form a photoresist pattern.

그 다음, 상기 감광막 패턴을 마스크로 상기 반도체 기판(111)을 식각하여 리세스 게이트 영역(117)을 형성한다. Next, the semiconductor substrate 111 is etched using the photoresist pattern as a mask to form a recess gate region 117.

이때, 상기 리세스 게이트 영역(117)은 링(ring) 형태로 형성하는 것이 바람직하다.In this case, the recess gate region 117 may be formed in a ring shape.

그리고, 상기 리세스 게이트 영역(117)의 장축방향 선폭(CD)은 상기 활성영역(113)과 제 1 및 제 2 게이트 예정영역이 오버랩(overlap)되는 영역 사이의 거리와 동일하게 형성하는 것이 바람직하다. In addition, the long axis line width CD of the recess gate region 117 may be equal to the distance between the active region 113 and the region where the first and second gate predetermined regions overlap. Do.

그 다음, 상기 감광막 패턴을 제거한다.Then, the photoresist pattern is removed.

그 다음, 상기 리세스 게이트 영역(117) 상부에 제 1 게이트(119b), 제 2 게이트(119c)를 형성한다.Next, a first gate 119b and a second gate 119c are formed on the recess gate region 117.

상술한 본 발명에 따른 반도체 소자의 제조방법은, 상기 리세스 게이트 영역(117)을 링(ring) 형태로 형성함으로써 제 3 게이트(119a), 제 4 게이트(119d) 하부의 리세스 게이트 영역을 형성하기 위한 식각공정시 상기 활성영역(113)의 에지부에 어택(attack)이 가해지는 현상을 방지할 수 있다. In the above-described method of manufacturing a semiconductor device, the recess gate regions 117a and the fourth gate 119d are formed by forming the recess gate regions 117 in a ring shape. It is possible to prevent a phenomenon in which an attack is applied to the edge portion of the active region 113 during the etching process for forming.

그리고, 추가공정 없이 상기 활성영역(113)의 장축방향 선폭(CD)을 확보할 수 있다.In addition, the long axis line width CD of the active region 113 may be secured without an additional process.

이상에서 살펴본 바와 같이, 본 발명에 따른 반도체 소자의 제조방법은 리세스 게이트 영역을 링(ring) 형태로 형성함으로써 리세스 게이트 영역을 형성하기 위한 식각공정시 활성영역 에지부에 어택(attack)이 가해지는 현상을 방지하고, 추가공정 없이 활성영역의 장축방향 선폭(CD)을 확보할 수 있어 공정마진을 향상시킬 수 있는 효과를 제공한다.As described above, in the method of manufacturing a semiconductor device according to the present invention, an attack is formed at an edge of an active region during an etching process for forming a recess gate region by forming the recess gate region in a ring shape. It is possible to prevent the applied phenomenon and to secure the long axis line width (CD) of the active region without an additional process, thereby providing an effect of improving the process margin.

아울러 본 발명의 바람직한 실시예는 예시의 목적을 위한 것으로, 당업자라면 첨부된 특허청구범위의 기술적 사상과 범위를 통해 다양한 수정, 변경, 대체 및 부가가 가능할 것이며, 이러한 수정 변경 등은 이하의 특허청구범위에 속하는 것으로 보아야 할 것이다. In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (3)

반도체 기판에 활성영역을 정의하는 소자분리막을 형성하는 단계;Forming an isolation layer defining an active region on the semiconductor substrate; 비트라인 콘택 예정영역은 차단시키고, 상기 비트라인 콘택 예정영역과 인접한 소정영역을 노출시키는 감광막 패턴을 이용한 사진 식각공정으로 상기 반도체 기판을 식각하여 리세스 게이트 영역을 형성하는 단계; 및 Forming a recess gate region by etching the semiconductor substrate by a photolithography process using a photoresist pattern that blocks a bit line contact region and exposes a predetermined region adjacent to the bit line contact region; And 상기 리세스 게이트 영역 상부에 제 1 게이트, 제 2 게이트를 형성하는 단계Forming a first gate and a second gate on the recess gate region 를 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.Method of manufacturing a semiconductor device comprising a. 제 1 항에 있어서, 상기 리세스 게이트 영역은 링(ring) 형태로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the recess gate region is formed in a ring shape. 제 1 항에 있어서, 상기 리세스 게이트 영역의 장축방향 선폭(CD)은 상기 활성영역과 제 1 및 제 2 게이트 예정영역이 오버랩(overlap)되는 영역 사이의 거리와 동일하게 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.The long axis line width CD of the recess gate region is equal to a distance between the active region and a region where the first and second gate predetermined regions overlap. Method of manufacturing a semiconductor device.
KR1020060070193A 2006-07-26 2006-07-26 Method for manufacturing of semiconductor device KR20080010128A (en)

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