KR20080009582A - Static random access memory device and method of forming the same - Google Patents

Abstract

An SRAM(Static Random Access Memory) device and a forming method thereof are provided to perform the high integration of the SRAM device by using a transistor as a driving transistor and preventing the voltage inversion of a node inside an SRAM cell. An SRAM device includes a device isolating film(106'), a first gate electrode(114), a first gate insulation film(112), and a first dopant doped area. The device isolating film is arranged on a semiconductor substrate(100), and limits an active area. The first gate electrode crosses the active area and the upper part of a groove(110) formed in the active area. The first gate insulation film is placed between the active area and the first gate electrode. The first dopant doped area is formed in the active area of both sides of the first gate electrode. The first gate electrode fills the groove under the first gate electrode by interposing the first gate insulation film between the groove and the first gate electrode.

Description

SRAM element and method of forming the same {STATIC RANDOM ACCESS MEMORY DEVICE AND METHOD OF FORMING THE SAME}

1 is an equivalent circuit diagram of a typical CMOS type SRAM cell.

2 is a cross-sectional view illustrating an SRAM device according to an exemplary embodiment of the present invention.

3 is a cross-sectional view taken from the direction II ′ of FIG. 2.

4A to 7A and 8 to 10 are cross-sectional views illustrating a method of forming an SRAM device according to an exemplary embodiment of the present invention.

4B-7B are sectional views seen from the direction II-II 'of FIGS. 4A-7A, respectively.

The present invention relates to a semiconductor device and a method of forming the same, and more particularly, to an SRAM device and a method of forming the same.

The unit cell of the SRAM element includes two inverters. The SRAM cell has a flip-flop structure in which output terminals of the two inverters are cross-coupled with each other. In addition, the RAM cell further includes two access transistors. Two access transistors are used for cell selection and data store / erase / read operations. These ESR cells store data by the feedback effect of the flip-flop while power is applied. That is, since the SRAM cell does not require an operation of refreshing a DRAM cell, the SRAM device has an advantage of lower power consumption than a DRAM device.

The SRAM cell can be classified into two types. One is a high resistance type SRAM cell adopting high resistance as a load element, and the other is a CMOS type SRAM cell adopting PMOS transistor as a load element. The CMOS type SRAM cell may implement a lower leakage current and a faster operating speed than the high resistance type SRAM cell. Thus, research on CMOS type SRAM cells has been actively conducted in recent years. The CMOS type SRAM cell will be described in more detail with reference to the equivalent circuit diagram of FIG. 1.

1 is an equivalent circuit diagram of a typical CMOS type SRAM cell.

Referring to FIG. 1, a CMOS type SRAM cell may include first and second driver transistors TD1 and TD2, first and second access transistors TA1 and TA2, and first and second loads. (load) transistors TL1 and TL2. The first and second driving transistors TD1 and TD2 and the first and second access transistors TA1 and TA2 are both NMOS transistors, while the first and second load transistors TL1 and TL2 are each. Are all PMOS transistors.

The first driving transistor TD1 and the first access transistor TA1 are connected in series with each other, a source region of the first driving transistor TD1 is connected with a ground line Vss, and the first access transistor TA1 ) Is connected to the first bit line BL. Similarly, the second driving transistor TD2 and the second access transistor TA2 are also connected in series. The source region of the second driving transistor TD2 is connected to the ground line Vss, and the drain region of the second access transistor TA2 is connected to the second bit line / BL.

A source region and a drain region of the first load transistor TL1 are connected to a power line Vcc and a drain region of the first driving transistor TD1, respectively. Similarly, the source region and the drain region of the second load transistor TL2 are connected to the drain region of the power supply line Vcc and the second driving transistor TD2, respectively. A drain region of the first load transistor TL1, a drain region of the first driving transistor TD1, and a source region of the first transfer transistor TA1 correspond to the first node N1. The drain region of the second load transistor TL2, the drain region of the second driving transistor TD2, and the source region of the second transfer transistor TA2 correspond to the second node N2. The gate electrode of the first driving transistor TD1 and the gate electrode of the first load transistor TL1 are connected to the second node N2, and the gate electrode and the second load transistor of the second driving transistor TD2. The gate electrode of TL2 is connected to the first node N1. In addition, gate electrodes of the first and second access transistors TA1 and TA2 are connected to a word line WL.

The CMOS SRAM cell described above shows a small stand-by current and a large noise margin as compared to the load resistance cell. Therefore, CMOS SRAM cells are widely used in high performance SRAMs requiring low power supply voltages.

The equivalent circuit diagram of the CMOS SRAM cell shown in FIG. 1 may be implemented in a semiconductor substrate in various forms. In particular, a full CMOS SRAM cell has been proposed in which all of the transistors TL1, TL2, TD1, TD2, TA1, and TA2 are formed on a bulk substrate. However, since the full CMOS SRAM cell occupies a large area, there is a big limitation in the high integration of the SRAM element. In particular, the amount of turn-on current of the driving transistors TD1 and TD2 may act as an important factor for the operation of the SRAM device. That is, when the turn-on current amount of the driving transistors TD1 and TD2 is not sufficient, the voltage of the node to which the ground voltage is applied among the nodes N1 and N2 may be changed. In this case, the voltages stored at the nodes N1 and N2 may be reversed by the flip-flop characteristic. Accordingly, data stored in the SRAM device may be contaminated. In order to prevent this, since the driving transistors TD1 and TD2 require a sufficient amount of turn-on current, the planar area of the driving transistors TD1 and TD2 may be increased. As a result, it may be more difficult to integrate the SRAM element higher.

SUMMARY OF THE INVENTION The present invention has been devised to solve the above-mentioned general problems, and a technical object of the present invention is to provide an SRAM device optimized for high integration and a method of forming the same.

Another object of the present invention is to provide an SRAM device capable of increasing the amount of turn-on current of a transistor within a limited area and a method of forming the same.

Provided is an SRAM device for solving the above technical problems. The SRAM device includes an isolation layer disposed on a semiconductor substrate to define an active region; A first gate electrode crossing the active region and an upper portion of a groove formed in the active region; A first gate insulating layer interposed between the active region and the first gate electrode; And a first dopant doped region formed in the active region on both sides of the first gate electrode. The first gate electrode fills the groove under the first gate electrode through the first gate insulating layer.

In detail, the top edge of the groove may have a round shape.

In example embodiments, the SRAM device may include a first interlayer insulating layer covering an entire surface of the semiconductor substrate; A first semiconductor pattern disposed on the first interlayer insulating layer; A second gate electrode crossing the first semiconductor pattern through a second gate insulating layer; Second dopant doped regions formed in the first semiconductor pattern on both sides of the second gate electrode; And a second interlayer insulating layer covering the entire surface of the semiconductor substrate. In this case, the device may further include a node contact plug electrically connected to the first and second dopant doped regions through the second and first interlayer insulating layers.

In example embodiments, the SRAM device may include a second semiconductor pattern on the second interlayer insulating layer; A third gate electrode crossing the second semiconductor pattern through a third gate insulating layer; A third dopant doped region formed in the second semiconductor pattern on both sides of the third gate electrode; And a third interlayer insulating layer covering the entire surface of the semiconductor substrate. In this case, the SRAM device may further include a node contact plug continuously passing through the third, second and first interlayer insulating layers and electrically connected to the first, second and third dopant doped regions. Can be.

Provided is a method of forming an SRAM device for solving the above technical problems. The method includes forming an isolation layer on a semiconductor substrate to define an active region; Forming a groove in the active region; Forming a first gate insulating film on a surface of the active region including a bottom surface and both sides of the groove; Forming a conductive film filling the groove on the gate insulating film; Patterning the gate conductive layer to form a first gate electrode crossing the groove and the active region; And forming a first dopant doped region in the active region on both sides of the first gate electrode.

In example embodiments, the device isolation layer may have a portion protruding higher than an upper surface of the active region. In this case, the forming of the groove may include forming a spacer film substantially conformally on the semiconductor substrate having the device isolation film; Anisotropically etching the spacer layer until the active region is exposed to form sidewall spacers on sidewalls of the protruding portions of the device isolation layer; And etching the exposed active region by using the device isolation layer and the sidewall spacers as a mask to form the grooves.

According to an embodiment, before forming the first gate insulating layer, the method performs a trimming process including an oxidation process and a wet etching process on the semiconductor substrate to round the top edge of the groove. It may further comprise the step of forming.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the spirit of the present invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers (or films) and regions are exaggerated for clarity. In addition, where it is said that a layer (or film) is "on" another layer (or film) or substrate, it may be formed directly on another layer (or film) or substrate or a third layer between them. (Or membrane) may be interposed. Portions denoted by like reference numerals denote like elements throughout the specification.

FIG. 2 is a cross-sectional view illustrating an SRAM device according to an exemplary embodiment of the present invention, and FIG. 3 is a cross-sectional view viewed from the direction II ′ of FIG. 2.

2 and 3, an isolation layer 106 ′ is disposed on the semiconductor substrate 100 to define an active region. The groove 110 is formed in the active region. The groove 110 has a bottom surface and both sides. The bottom surface of the groove 110 is lower than the top surface of the active region, and the side surface of the groove 110 connects the bottom surface of the groove 110 and the top surface of the active region. That is, the surface of the active region is curved due to the groove 110. The surface of the active region includes an upper surface of the active region, a bottom surface and both side surfaces of the groove 110. The groove 110 may be parallel to the active region. The upper edge of the groove 110 is preferably rounded.

The first gate electrode 114 crosses the active region and the groove 110. A first gate insulating layer 112 is interposed between the first gate electrode 114 and the top surface of the active region and between the bottom surface and both side surfaces of the first gate electrode 114 and the groove 110. In this case, the first gate electrode 114 fills the groove 110 under the first gate electrode 114. A first dopant-doped region 118 is formed in the active region on both sides of the first gate electrode 114. The groove 110 may be disposed in the active region on both sides of the first gate electrode 114. Accordingly, the first dopant doped region 118 may be formed in an active region in which the groove 110 is formed on both sides of the first gate electrode 114. The first gate electrode 114 and the first dopant doped region 118 may correspond to a gate and a source / drain of the first driving transistor TD1 of FIG. 1.

A first capping insulation pattern 116 may be disposed on the first gate electrode 114. The first gate insulating layer 112, the first gate electrode 114, and the first capping insulating pattern 116 constitute a first gate pattern. Although not shown, first gate spacers may be disposed on both sidewalls of the first gate pattern.

A first interlayer insulating layer 120 covers the entire surface of the semiconductor substrate 100 including the first gate pattern. Although not shown, an etch stop layer may be disposed under the first interlayer insulating layer 120. The etch stop layer may cover the entire surface of the semiconductor substrate 100 including the first gate electrode 114. The etch stop layer is formed of an insulating material having the etch selectivity of the first interlayer insulating layer 120.

The first semiconductor pattern 126a is disposed on the first interlayer insulating layer 120. The first semiconductor pattern 126a may be formed of the same semiconductor as the semiconductor substrate 100. For example, the semiconductor substrate 100 and the first semiconductor pattern 126a may be formed of silicon. It is preferable that the first semiconductor pattern 126a is in a single crystal state. The second gate pattern 134 crosses the first semiconductor pattern 126a. The second gate pattern 134 includes a second gate insulating layer 128, a second gate electrode 130, and a second capping insulating pattern 134 that are sequentially stacked. A second dopant doped region 136 is formed in the first semiconductor pattern 126a on both sides of the second gate pattern 134. The second dopant doped region 126 may be doped with dopants of the same type as the first dopant doped region 136. Although not shown, second gate spacers may be disposed on both sides of the second gate pattern 134. The second gate electrode 130 and the second dopant doped region 136 may correspond to the gate and source / drain of the first access transistor TA1 of FIG. 1, respectively.

The second interlayer insulating layer 138 covers the entire surface of the semiconductor substrate 100 including the second gate pattern 134. The second semiconductor pattern 144a is disposed on the second interlayer insulating layer 138. The second semiconductor pattern 144a may be formed of the same semiconductor as the semiconductor substrate 100 and the first semiconductor pattern 126a. It is preferable that the second semiconductor pattern 144a is in a single crystal state. The third gate pattern 152 crosses the second semiconductor pattern 144a. The third gate pattern 152 includes a third gate insulating layer 146, a third gate electrode 148, and a third capping insulating pattern 150 that are sequentially stacked. A third dopant doped region 153 is formed in the second semiconductor pattern 144a on both sides of the third gate pattern 152. The third dopant doped region 153 may be doped with different types of dopants from the first and second dopant doped regions 118 and 136. Although not shown, third gate spacers may be disposed on both sides of the third gate pattern 152. The third gate electrode 148 and the third dopant doped region 153 may correspond to the gate and source / drain regions of the first load transistor TL1 of FIG. 1, respectively.

The third interlayer insulating layer 154 covers the entire surface of the semiconductor substrate 100 including the third gate pattern 152. The node contact plug 158 fills the node contact hole 156 that continuously passes through the third, second, and first interlayer insulating layers 154, 138, and 120. The node contact plug 158 is electrically connected to the first, second and third dopant doped regions 118, 136 and 153. The node contact hole 156 may directly expose the first dopant doped region 118. In this case, the node contact plug 158 may directly connect with the first dopant doped region 118. Alternatively, a buffer conductive pattern 124a may be interposed between the node contact plug 158 and the first dopant doped region 118. The buffer conductive pattern 124a may be formed of a semiconductor doped with dopants. The node contact plug 158 is preferably formed of a conductive material except for the doped semiconductor to connect the first, second and third dopant doped regions 118, 136 and 153 doped with different types of dopants. Do.

According to the SRAM device having the above-described structure, the first gate electrode 114 formed on the semiconductor substrate 100 fills the groove 110 disposed below it. As a result, the width of the first channel region under the first gate electrode 114 is increased. That is, the first channel region includes an upper surface of the active region positioned below the first gate electrode 114, and both side surfaces and a bottom surface of the groove 110. Accordingly, the width of the first channel region is increased by the heights of both sides of the groove 110. As a result, within the limited area, the width of the first channel region is increased to increase the amount of turn-on current of the transistor including the first gate electrode 114. As a result, a highly integrated SRAM device may be implemented. In particular, when the transistor including the first gate electrode 114 is a driving transistor as described above, the charges of the node to which the ground voltage is applied in the SRAM cell can be sufficiently discharged to the ground line. As a result, it is possible to prevent the conventional data from being contaminated.

In addition, transistors including the second and third gate patterns 134 and 152, respectively, are stacked over the transistor including the first gate electrode 114. Accordingly, it is possible to implement a highly integrated SRAM device.

In addition, the top edge of the groove 110 is rounded. Accordingly, a phenomenon in which an electric field is concentrated at an upper edge of the groove 110 under the first gate electrode 114 may be minimized.

The transistor having the third gate pattern 152 may be disposed at the same level as the transistor having the second gate pattern 134. In this case, the second semiconductor pattern 144a is disposed on the second interlayer insulating layer 138 and spaced apart from the first semiconductor pattern 126a. Of course, the third gate pattern 152 is also laterally spaced apart from the second gate pattern 134. In this case, the node contact plug 158 may be electrically connected to the first and second dopant doped regions 118 and 136 by continuously passing through the second and first interlayer insulating layers 138 and 120. Even in this case, the buffer conductive pattern 124a may exist.

Meanwhile, the groove 110 according to the present invention may also be applied to a fully CMOS type SRAM cell in which driving, access, and load transistors are all formed to be spaced apart on the semiconductor substrate 100 sideways. In this case, the transistor including the first gate electrode 114 on the groove 110 may be one of driving, accessing and load transistors. In particular, the groove 110 may be disposed in all of the channel regions of the driving, accessing and load transistors. Even in this embodiment, the width of the channel regions of the drive, access and / or load transistors is increased within the area limited by the groove 110. Therefore, a highly integrated SRAM device can be implemented.

4A to 7A and 8 to 10 are cross-sectional views illustrating a method of forming an SRAM element according to an embodiment of the present invention, and FIGS. 4B to 7B are II-II 'of FIGS. 4A to 7A, respectively. Sectional view from the direction of.

4A and 4B, the hard mask pattern 102 is formed on the semiconductor substrate 100. The hard mask pattern 102 may include a material having an etch selectivity with respect to the semiconductor substrate 100. For example, the hard mask pattern 102 may include a nitride film. In addition, the hard mask pattern 102 may include an oxide film and a nitride film that are sequentially stacked.

Using the hard mask pattern 102 as a mask, the semiconductor substrate 100 is etched to form a trench 104 defining an active region. Next, an insulating film filling the trench 104 is formed on the entire surface of the semiconductor substrate 100, and the insulating film is planarized until the hard mask pattern 102 is exposed to form the device isolation film 106. The device isolation layer 106 may be formed of an oxide layer.

5A and 5B, the hard mask pattern 102 is removed to expose the active region. In this case, the device isolation layer 106 includes a portion protruding higher than the top surface of the active region. That is, the upper portion of the isolation layer 106 corresponds to the protruding portion, and the lower portion of the isolation layer 106 fills the trench 104.

Subsequently, a spacer film is substantially conformally formed on the entire surface of the semiconductor substrate 100, and the spacer film is anisotropically etched until the active region is exposed, and then formed on the sidewall of the protruding portion of the device isolation layer 106. Sidewall spacers 108 are formed. The sidewall spacers 108 may be formed of a material having an etch line tack ratio with respect to the semiconductor substrate 100. For example, the sidewall spacers 108 may be formed of an oxide film or a nitride film.

6A and 6B, the groove 110 is formed by etching the active region using the device isolation layer 106 and the sidewall spacers 108 as masks. The groove 110 has a bottom surface and both sides. Both side surfaces of the groove 110 connect the bottom surface and the top surface of the active region. The groove 110 may be parallel to the active region. Dotted line “101” in FIG. 6A represents the top surface of the active region. That is, the top surface of the semiconductor substrate 100 of FIG. 6A corresponds to the bottom surface of the groove 110.

7A and 7B, the sidewall spacers 108 are removed. The sidewall spacers 108 may be removed by wet etching. When the sidewall spacers 108 are formed of an oxide layer, the device isolation layer 106 may also be etched. Reference numeral 106 'denotes the etched device isolation film 106'. When the sidewall spacers 108 are formed of a nitride film, after removing the sidewall spacers 108 with phosphoric acid, a wet etching process of lowering the height of the device isolation layer 106 may be performed.

It is preferable to perform a trimming process including a wet etching process for removing an oxidation process (particularly, a thermal oxidation process) and an oxide film (particularly, a thermal oxide film) to the semiconductor substrate 100. The top edge of the groove 110 may be formed in a round shape by the trimming process. The trimming process may be performed one or more times.

A first gate insulating layer 112 is formed on the semiconductor substrate 100 having the groove 110, and a conductive layer filling the groove is formed on the first gate insulating layer 112. A first capping insulating film is formed on the conductive film. The first capping insulating layer and the conductive layer are successively patterned to form a first gate electrode 114 and a first capping insulating pattern 116 which are sequentially stacked. In this case, the first gate electrode 114 fills the groove 110 under the first gate electrode 114 via the first gate insulating layer 112.

The first gate insulating layer 112 may be formed of an oxide layer, particularly, a thermal oxide layer. The first gate electrode 114 may include at least one selected from a doped semiconductor, a metal (ex, tungsten or molybdenum, etc.), a conductive metal nitride (ex, titanium nitride or tantalum nitride, etc.), and a metal silicide (ex, tungsten silicide, etc.). It may include one. The first capping insulation pattern 116 may be formed of an oxide film, a nitride film, or an oxynitride film. The first gate insulating layer 112 on both sides of the gate electrode 114 may be removed by a cleaning process or the like. The first gate electrode 114 and the first capping insulation pattern 116 are included in the first gate pattern.

Referring to FIG. 8, a first dopant doped region 118 is formed by implanting first dopant ions using the first gate electrode 114 and the first capping insulation pattern 116 as a mask. Subsequently, a first interlayer insulating layer 120 is formed on the entire surface of the semiconductor substrate 100. The first interlayer insulating layer 120 may be formed of an oxide film. Before forming the first interlayer insulating layer 120, an etch stop layer (not shown) that is substantially conformal may be formed on the entire surface of the semiconductor substrate 100. The first interlayer insulating layer 120 is patterned to form a first contact hole 122 exposing the first dopant doped region 118.

A first semiconductor plug 124 filling the first contact hole 122 and a first semiconductor layer 126 covering the entire surface of the first interlayer insulating layer 120 are formed. One method of forming the first semiconductor plug 124 and the first semiconductor layer 126 will be described. An epitaxial growth process is performed on the semiconductor substrate having the exposed first dopant doped region 118 to form a first semiconductor plug 124 that fills the first contact hole 122. In this case, the first semiconductor plug 124 is formed in a single crystal state. The first semiconductor plug 124 may be doped in-situ by dopants of the same type as the first dopant doped region 118. Subsequently, an amorphous semiconductor layer is formed on the entire surface of the semiconductor substrate 100. The amorphous semiconductor layer is in contact with the first semiconductor plug 124. Subsequently, heat treatment is performed on the amorphous semiconductor layer. By the heat treatment, the semiconductor layer in the amorphous state is formed of the first semiconductor layer 126 in the single crystal state.

Alternatively, the first semiconductor plug 124 and the first semiconductor layer 126 may be formed. Specifically, an epitaxial growth process is performed on the semiconductor substrate 100 having the first contact hole 122 to fill the first contact hole 122 to cover the entire surface of the first interlayer insulating layer 120. An epitaxial layer is formed. Of course, the epitaxial layer is formed in a single crystal state. Subsequently, a process of planarizing an upper surface of the epitaxial layer is performed. In this case, a portion filling the first contact hole 122 of the planarized epitaxial layer corresponds to the first semiconductor plug 124, and on the first interlayer insulating layer 120 of the planarized epitaxial layer. The disposed portion corresponds to the first semiconductor layer 126.

Referring to FIG. 9, the first semiconductor layer 126 is patterned to form the first semiconductor pattern 126a. The first semiconductor pattern 126a is in contact with the first semiconductor plug 124.

Subsequently, a second gate pattern 134 that crosses the first semiconductor pattern 126a is formed. The second gate pattern 134 includes a second gate insulating layer 128, a second gate electrode 130, and a second capping insulating pattern 132 that are sequentially stacked. The second gate insulating layer 128 may be formed of a thermal oxide layer. The second gate electrode 130 is at least selected from a doped semiconductor, a metal (ex, tungsten or molybdenum, etc.), a conductive metal nitride (ex, titanium nitride or tantalum nitride, etc.) and a metal silicide (ex, tungsten silicide, etc.) It may include one. The second capping insulation pattern 132 may be formed of an oxide film, a nitride film, or an oxynitride film.

The second dopant doped region 136 is formed in the first semiconductor pattern 126a on both sides of the second gate pattern 134 by implanting second dopant ions using the second gate pattern 134 as a mask. .

A second interlayer insulating layer 138 is formed on the entire surface of the semiconductor substrate 100. The second interlayer insulating layer 138 may be formed of an oxide film. The second interlayer insulating layer 138 is patterned to form a second contact hole 140 exposing the second dopant doped region 136. A second semiconductor plug 142 filling the second contact hole 140 and a second semiconductor layer 144 disposed on the second interlayer insulating layer 138 and in contact with the second semiconductor plug 142 are formed. do. The second semiconductor plug 142 and the second semiconductor layer 144 may be in a single crystal state. The method of forming the second semiconductor plug 142 and the second semiconductor layer 144 may be the same as the method of forming the first semiconductor plug 124 and the first semiconductor layer 126. However, the second semiconductor plug 142 may not be doped by the dopant.

Referring to FIG. 10, the second semiconductor layer 144 is patterned to form a second semiconductor pattern 144a. A third gate pattern 152 that crosses the second semiconductor pattern 144a is formed. The third gate pattern 152 includes a third gate insulating layer 146, a third gate electrode 148, and a third capping insulating pattern 150 that are sequentially stacked. The third gate insulating layer 146 may be formed of an oxide layer. The third gate electrode 148 may include at least one selected from a doped semiconductor, a metal (ex, tungsten or molybdenum, etc.), a conductive metal nitride (ex, titanium nitride or tantalum nitride, etc.), and a metal silicide (ex, tungsten silicide, etc.). It may include one. The third capping insulation pattern 150 may be formed of an oxide film, a nitride film, or an oxynitride film.

A third dopant doped region 153 is formed in the second semiconductor pattern 144a by implanting third dopant ions using the third gate pattern 152 as a mask. Subsequently, a third interlayer insulating layer 154 is formed on the entire surface of the semiconductor substrate 100. The third interlayer insulating layer 154 may be formed of an oxide film.

Subsequently, the third, second, and first interlayer insulating layers 154, 138, and 120 are successively patterned to form the node contact hole 156 of FIG. 2. In this case, the first and second dopant doping regions 136 and 153 are exposed on the side surface of the node contact hole 156. In particular, when the interlayer insulating layers 154, 138, and 120 are patterned, the first and second dopant doped regions 136 and 153 positioned in the region where the node contact hole 156 is formed may also be etched. In addition, an upper portion of the first semiconductor plug 124 may also be etched. The node contact hole 156 may expose the etched first semiconductor plug 124a. In this case, the etched first semiconductor plug 124a is defined as a buffer conductive pattern 124a. Alternatively, the node contact hole 156 may directly expose the first dopant doped region 118. Subsequently, the node contact plug 158 of FIG. 2 filling the node contact hole 156 is formed. As a result, the SRAM device illustrated in FIGS. 2 and 3 may be implemented.

In the above-described method of forming the SRAM device, the width of the channel region under the first gate electrode 114 is increased by the groove 110 within a limited area. The groove 110 is also defined by the sidewall spacers 108. That is, a photolithography process is not required when forming the groove 110. Accordingly, the groove 110 may be formed to have a smaller width than the minimum line width that can be defined by the photolithography process.

As described above, the SRAM cell according to the present invention includes a transistor formed in an active region defined in a semiconductor substrate. In this case, a groove is formed in the active region, and the gate electrode of the transistor crosses the groove and extends downward to fill the groove. Thus, the width of the channel region is increased within the limited area. As a result, it is possible to reduce the planar area of the transistor and increase the amount of turn-on current of the transistor. In particular, the transistor can be used as a driving transistor. As a result, a phenomenon in which the voltage of the node in the SRAM cell is reversed can be prevented. In addition, second and / or third transistors may be stacked on the transistor. As a result, the SRAM element can be further integrated.

Claims (12)

An isolation layer disposed on the semiconductor substrate to define an active region; A first gate electrode crossing the active region and an upper portion of a groove formed in the active region; A first gate insulating layer interposed between the active region and the first gate electrode; And And a first dopant doped region formed in the active region on both sides of the first gate electrode, wherein the first gate electrode fills the groove under the first gate electrode through the first gate insulating layer. The method of claim 1, The upper edge of the groove is a round SRAM device. The method according to claim 1 or 2, A first interlayer insulating layer covering an entire surface of the semiconductor substrate; A first semiconductor pattern disposed on the first interlayer insulating layer; A second gate electrode crossing the first semiconductor pattern through a second gate insulating layer; Second dopant doped regions formed in the first semiconductor pattern on both sides of the second gate electrode; And And a second interlayer insulating film covering the entire surface of the semiconductor substrate. The method of claim 3, wherein The second and first interlayer insulating films further include a node contact plug electrically connected to the first and second dopant doped regions continuously. The method of claim 3, wherein A second semiconductor pattern disposed on the second interlayer insulating layer; A third gate electrode crossing the second semiconductor pattern through a third gate insulating layer; A third dopant doped region formed in the second semiconductor pattern on both sides of the third gate electrode; And And a third interlayer insulating film covering the entire surface of the semiconductor substrate. The method of claim 5, wherein And a node contact plug electrically connected to the first, second and third dopant doped regions through the third, second and first interlayer insulating layers. Forming an isolation layer on the semiconductor substrate to define an active region; Forming a groove in the active region; Forming a first gate insulating film on a surface of the active region including a bottom surface and both sides of the groove; Forming a conductive film filling the groove on the gate insulating film; Patterning the gate conductive layer to form a first gate electrode crossing the groove and the active region; And Forming a first dopant doped region in the active region on both sides of the first gate electrode. The method of claim 7, wherein The device isolation layer has a portion protruding higher than the upper surface of the active region, Forming the grooves, Forming a spacer film substantially conformally on the semiconductor substrate having the device isolation film; Anisotropically etching the spacer layer until the active region is exposed to form sidewall spacers on sidewalls of the protruding portions of the device isolation layer; And And etching the exposed active region using the device isolation layer and the sidewall spacers as a mask to form the groove. The method of claim 7, wherein Before forming the first gate insulating film, And forming a top edge of the groove in a round shape by performing a trimming process including an oxidation process and a wet etching process on the semiconductor substrate. The method according to any one of claims 7 to 9, Forming an interlayer insulating film covering an entire surface of the semiconductor substrate; Forming a contact hole penetrating the interlayer insulating layer to expose the first dopant doped region; Forming a semiconductor plug filling the contact hole and a semiconductor pattern disposed on the interlayer insulating layer and in contact with the semiconductor plug; Forming a second gate insulating film on a surface of the semiconductor pattern; And And forming a second gate electrode on the second gate insulating layer to cross the semiconductor pattern. The method of claim 10, Forming the semiconductor plug and the semiconductor pattern, Performing an epitaxial growth process on the semiconductor substrate to form the semiconductor plug filling the contact hole; Forming an amorphous semiconductor layer on the interlayer insulating film; Thermally treating the amorphous semiconductor layer to form a single crystal semiconductor layer; And And forming the semiconductor pattern by patterning the semiconductor layer in the single crystal state. The method of claim 10, Forming the semiconductor plug and the semiconductor pattern, Performing an epitaxial growth process on the semiconductor substrate to form an epitaxial layer filling the contact hole and covering the entire surface of the interlayer insulating film; Planarizing an upper surface of the epitaxial layer; And Patterning the planarized epitaxial layer on the interlayer insulating film, wherein the epitaxial layer filling the contact hole corresponds to the semiconductor plug, and the patterned epitaxial layer on the interlayer insulating film corresponds to the semiconductor pattern. Method of forming an SRAM element.

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