KR20080002595A - Method of fabricating the landing plug contact in semicondutor device - Google Patents

Method of fabricating the landing plug contact in semicondutor device Download PDF

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KR20080002595A
KR20080002595A KR1020060061492A KR20060061492A KR20080002595A KR 20080002595 A KR20080002595 A KR 20080002595A KR 1020060061492 A KR1020060061492 A KR 1020060061492A KR 20060061492 A KR20060061492 A KR 20060061492A KR 20080002595 A KR20080002595 A KR 20080002595A
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plug contact
landing plug
film
region
forming
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KR1020060061492A
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KR100811265B1 (en
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이원모
황경호
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
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Abstract

A method of fabricating a landing plug contact in a semiconductor device is provided to improve productivity by uniformly maintaining a removal rate of a cell area and a peripheral area to secure precise planarization and a process margin. A method of fabricating a landing plug contact in a semiconductor device includes the steps of: forming a gate stack(120) including a gate conductive film(121) and a hard mask film(122) isolated by an interlayer insulating film(140) on a semiconductor substrate(100) having a first area with a relatively high pattern density and a second area with a relatively low pattern density; implanting ions by using a barrier film exposing the first area; forming a landing plug contact hole exposing the semiconductor substrate between the gate stacks of the first area by removing a part of the interlayer insulating film in the first area; forming a material film for the landing plug contact on a front surface of the first and second areas; and forming a contact plug by planarizing the material film for the landing plug contact. Further, the hard mask film is a nitride film, and silicon or germanium ion is used in the step of implanting ions.

Description

반도체 소자의 랜딩 플러그 컨택 형성 방법 {Method of fabricating the landing plug contact in semicondutor device}Method of fabricating the landing plug contact in semicondutor device

도 1 내지 도 4는 본 발명에 따른 반도체 소자의 랜딩 플러그 컨택 형성 방법을 설명하기 위해 나타내 보인 도면들이다. 1 to 4 are views illustrating a method of forming a landing plug contact of a semiconductor device according to the present invention.

본 발명은 반도체 소자의 랜딩 플러그 컨택 형성 밥법에 관한 것으로, 패턴 밀도 차이로 인한 연마율의 차이를 개선한 반도체 소자의 랜딩 플러그 컨택 형성 방법에 관한 것이다.The present invention relates to a method of forming a landing plug contact of a semiconductor device, and more particularly, to a method of forming a landing plug contact of a semiconductor device in which a difference in polishing rate due to a difference in pattern density is improved.

최근 반도체 소자의 회로 선폭이 점차 미세화됨에 따라 반도체 소자의 셀 영역에는 점점 더 조밀하게 패턴이 형성되고 있다. 이에 따라 후속 평탄화 공정 수행시 패턴이 밀집된 지역과 그렇지 않은 지역, 예를 들어 셀 영역 및 주변 영역으로 구분되어 평탄화 정도 차이가 발생한다. 즉, 화학적 기계적 평탄화 방법을 이용하여 평탄화 공정을 진행하는 경우 특히, 랜딩 플러그 컨택을 형성하는 과정에서 게이트 패턴이 고밀도로 이루어져 연마율(removal rete)이 느린 셀 영영과 게이트 패턴이 저밀도로 이루어져 연마율이 빠른 주변 영역에 있어서 연마율 차이가 발생한 다. 다시 말하면 랜딩 플러그의 평탄화 공정 수행시 셀 영역의 게이트 하드마스크막이 노출될 때까지 평탄화 공정을 수행하는 경우, 셀 영역의 랜딩 플러그 컨택 물질막 및 하드마스크막이 제거되는 속도보다 주변영역의 랜딩 플러그 컨택 물질막 및 하드마스크막이 제거되는 속도가 빠르다. 이에 따라 셀 영역을 타겟으로 평탄화 공정을 수행하면 주변 영역은 더 빠른 연마율로 인해 주변 영역의 하드 마스크막이 더 많이 제거된다. 더욱이 주변 영역에 기존의 연마율을 넘는 오버 연마(over polsihing)가 발생하여 하드마스크막 하부의 게이트 금속막이 노출되는 문제가 발생한다. 이러한 연마율 차이로 인해 셀 영역의 제거되지 않는 하드마스크막과 주변영역의 하드마스크막의 단차를 없애기 위한 후속 과정이 필요하다. 따라서 이러한 문제점이 해결되지 않는 상태에서 후속 공정을 진행하면 빠른 리플레시(reflash) 특성 및 고집적 소자를 구현하는데 있어서 많은 문제점이 발생한다. As circuit widths of semiconductor devices become smaller in recent years, patterns are increasingly formed in cell regions of semiconductor devices. As a result, when the subsequent planarization process is performed, the pattern is divided into a region where the pattern is not and a region where the pattern is not, for example, a cell region and a peripheral region, thereby causing a difference in the degree of planarization. That is, when the planarization process is performed using a chemical mechanical planarization method, in particular, in the process of forming the landing plug contact, the gate pattern is made of high density, and the polishing of the cell pattern having a low removal rate and the gate pattern is made of low density. In this fast peripheral area, a difference in polishing rate occurs. In other words, when the planarization process is performed until the gate hard mask layer of the cell region is exposed during the planarization process of the landing plug, the landing plug contact material of the peripheral region is higher than the rate at which the landing plug contact material layer and the hard mask layer of the cell region are removed. The speed at which the film and the hard mask film are removed is high. Accordingly, when the planarization process is performed on the cell region, the hard mask layer of the peripheral region is removed more due to the faster removal rate. In addition, overpolishing may occur in the peripheral area exceeding a conventional polishing rate, thereby causing a problem of exposing the gate metal film under the hard mask film. Due to this difference in polishing rate, a subsequent process is required to eliminate the step between the hard mask film which is not removed in the cell region and the hard mask film in the peripheral region. Therefore, if the subsequent process is not solved, many problems occur in implementing a fast refresh characteristics and high integration device.

본 발명이 이루고자 하는 기술적 과제는, 게이트 패턴의 밀도차에 의해 연마율의 차이를 나타내는 랜딩 플러그 컨택 형성시 연마율의 차이를 없애 소자의 특성을 향상시키는 반도체 소자의 랜딩 플러그 컨택 형성 방법을 제공하는 것이다.An object of the present invention is to provide a method for forming a landing plug contact of a semiconductor device, which improves device characteristics by eliminating the difference in polishing rate when forming a landing plug contact having a difference in polishing rate due to a density difference between gate patterns. will be.

상기 기술적 과제를 달성하기 위하여, 본 발명에 따른 반도체 소자의 랜딩 플러그 컨택 형성 방법은, 패턴 밀도가 상대적으로 큰 제1 영역 및 패턴 밀도가 상대적으로 작은 제2 영역을 갖는 반도체 기판 상에 층간절연막에 의해 분리된 게이트 도전막 및 하드마스크막을 구비한 게이트 스택을 형성하는 단계; 상기 제1 영역 을 노출시키는 베리어막을 이용하여 이온 주입 공정을 수행하는 단계; 상기 제1 영역 내의 층간 절연막 일부를 제거하여 상기 제1 영역의 게이트 스택 사이에서 반도체 기판을 노출시키는 랜딩 플러그 컨택홀을 형성하는 단계; 상기 제1 영역 및 제2 영역 전면에 랜딩 플러그 컨택용 물질막을 형성하는 단계; 및 상기 랜딩 플러그 컨택용 물질막을 평탄화하여 콘택 플러그를 형성하는 단계를 포함한다.In order to achieve the above technical problem, the method for forming a landing plug contact of a semiconductor device according to the present invention may include forming an interlayer insulating film on a semiconductor substrate having a first region having a relatively high pattern density and a second region having a relatively low pattern density. Forming a gate stack having a gate conductive layer and a hard mask layer separated by the first and second gate conductive layers; Performing an ion implantation process using a barrier film exposing the first region; Removing a portion of the interlayer insulating layer in the first region to form a landing plug contact hole exposing the semiconductor substrate between the gate stacks of the first region; Forming a material film for a landing plug contact on the entire surface of the first region and the second region; And planarizing the material layer for the landing plug contact to form a contact plug.

상기 하드마스크막은 질화막으로 형성하는 것이 바람직하다.The hard mask film is preferably formed of a nitride film.

상기 이온 주입은 실리콘 이온 또는 게르마늄 이온을 이용하여 수행하는 것이 바람직하다.The ion implantation is preferably performed using silicon ions or germanium ions.

상기 이온 주입은 0.1 내지 10 Kev의 주입에너지로 수행하는 것이 바람직하다.The ion implantation is preferably performed with an implantation energy of 0.1 to 10 Kev.

상기 평탄화는 화학적 기계적 평탄화 방법을 사용하여 수행하는 것이 바람직하다.The planarization is preferably carried out using a chemical mechanical planarization method.

상기 평탄화를 수행한 후에 급속 어닐링 공정을 수행하는 단계를 더 포함할 수 있다.After performing the planarization, the method may further include performing a rapid annealing process.

상기 급속 어닐링 공정은 1 내지 120초 사이에서 수행하는 것이 바람직하다.The rapid annealing process is preferably performed between 1 and 120 seconds.

이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세히 설명하고자 한다. 그러나 본 발명은 여러 가지 상이한 형태로 구현될 수 있으며, 여기에서 설명하는 실시예에 한정되지 않는다. 도면에서 여러 층 및 영역을 명확하게 표현하기 위하여 두께를 확대하여 나타내었다. 명세서 전체를 통하여 유사한 부분에 대해서는 동일한 도면 부호를 붙였다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification.

도 1 내지 도 4는 본 발명에 따른 반도체 소자의 랜딩 플러그 컨택 형성 방법을 설명하기 위하여 나타내 보인 도면들이다.1 to 4 are views illustrating a method of forming a landing plug contact of a semiconductor device according to the present invention.

도 1에 도시된 바와 같이, 소자 분리막(110) 및 활성영역을 갖는 반도체 기판(100) 상에 게이트 스택(120)을 형성한다. 상기 반도체 기판(100)은 게이트 패턴 밀도가 상대적으로 큰 셀 영영(200)과 게이트 패턴 밀도가 상대적으로 작은 주변 영역(210)으로 구분된다. 게이트 스택(120)은 게이트 도전막 패턴(121), 게이트 하드마스크막 패턴(122)으로 이루어진다. 비록 도면에는 나타내지는 않았지만, 반도체 기판(100)과 게이트 스택(120) 사이에는 게이트 절연막(미도시)이 배치된다. 게이트 도전막 패턴(121)은 폴리 실리콘막 패턴 및 금속막/금속실리사이드막 패턴으로 이루어질 수 있으며 게이트 하드마스막 패턴(122)은 질화막으로 이루어진다. 다음에 게이트 스택(120)이 형성된 반도체 기판(100) 상에 게이트 스페이서 버퍼 절연막 및 게이트 스페이서 질화막을 증착/식각 하여 상기 게이트 스택(120) 측벽을 보호하는 게이트 스페이서(130)를 형성한다. 다음에 셀 영역(200) 및 주변 영역(210)의 게이트 스택(120) 사이를 층간 절연막(140)으로 채운 후 평탄화 공정을 수행하여 게이트 전극을 분리시켜 게이트 하드마스크막을 노출시킨다.As shown in FIG. 1, the gate stack 120 is formed on the semiconductor substrate 100 having the device isolation layer 110 and the active region. The semiconductor substrate 100 is divided into a cell region 200 having a relatively large gate pattern density and a peripheral region 210 having a relatively small gate pattern density. The gate stack 120 includes a gate conductive layer pattern 121 and a gate hard mask layer pattern 122. Although not shown in the drawings, a gate insulating film (not shown) is disposed between the semiconductor substrate 100 and the gate stack 120. The gate conductive layer pattern 121 may be formed of a polysilicon layer pattern and a metal layer / metal silicide layer pattern. The gate hard mask layer pattern 122 may be formed of a nitride layer. Next, a gate spacer 130 that protects sidewalls of the gate stack 120 is formed by depositing / etching a gate spacer buffer insulating layer and a gate spacer nitride layer on the semiconductor substrate 100 on which the gate stack 120 is formed. Next, a gap between the cell region 200 and the gate stack 120 of the peripheral region 210 is filled with the interlayer insulating layer 140, and then the planarization process is performed to separate the gate electrode to expose the gate hard mask layer.

도 2에 도시된 바와 같이. 게이트의 하드마스크막이 노출된 반도체 기판(100)의 주변 영역(210) 위에 마스크 패턴(PR)을 사용하여 셀 영역(200)의 반도체 기판(100)을 오픈시킨다. 다음에, 오픈된 셀 영역(200)의 게이트 하드마스크막 패턴(122) 및 층간절연막(140) 상부에 이온을 주입한다. 이온 주입은 0.1 내지 10 kev의 주입 에너지에서 수행하여 실리콘 이온 또는 게르마늄 이온을 사용한다, 이 이온주입으로 의해, 셀 영역(200) 내의 게이트 스택(120)의 하드마스크막 패턴(122) 표면을 약화시킨다.As shown in FIG. 2. The semiconductor substrate 100 of the cell region 200 is opened by using a mask pattern PR on the peripheral region 210 of the semiconductor substrate 100 where the hard mask layer of the gate is exposed. Next, ions are implanted into the gate hard mask layer pattern 122 and the interlayer dielectric layer 140 of the open cell region 200. Ion implantation is performed at an implantation energy of 0.1 to 10 kev to use silicon ions or germanium ions. This ion implantation weakens the surface of the hardmask film pattern 122 of the gate stack 120 in the cell region 200. Let's do it.

도 3에 도시된 바와 같이, 통상의 자기 정렬 콘택(SAC; Self Align Contact) 공정을 수행하여 셀 영역(200) 내의 층간 절연막(140) 일부를 제거하여, 반도체 기판(100)의 일부가 노출되는 랜딩 프러그 콘택 홀이 형성된다. 다음에 셀 영역(200) 및 주변 영역(210) 전면에 랜딩 플러그 컨택용 물질막(150)을 증착한다. 랜딩 플러그 컨택용 물질막(150)은 폴리 실리콘막으로 이루어질 수 있다. As shown in FIG. 3, a portion of the semiconductor substrate 100 is exposed by removing a portion of the interlayer insulating layer 140 in the cell region 200 by performing a normal self alignment contact (SAC) process. Landing plug contact holes are formed. Next, a material layer 150 for the landing plug contact is deposited on the cell region 200 and the peripheral region 210. The landing plug contact material layer 150 may be formed of a polysilicon layer.

도 4에 도시된 바와 같이, 랜딩 플러그 컨택 물질막(150)이 형성된 결과물 전면에 화학적 기계적 평탄화(CMP:Chemical Mechanical Planarization)방법을 수행하여 평탄화를 진행한다. 이때 셀 영역(200)의 게이트 하드마스크막 패턴(122)을 타겟으로 하여 하드마스크막 패턴(123)이 드러나도록 화학적 기계적 평탄화 방법을 진행한다. 이 평탄화 공정 수행시 셀 영역(200)의 하드마스크막(122)표면은 이온 주입으로 약해졌기 때문에 연마율이 빨라져 주변 영역(210)과 동시에 평탄화된다. 이로 인해 셀 영역(200)을 기준으로 평탄화를 수행하더라도 셀 영역(200)의 빠른 연마율로 인해 주변 영역(210)에서의 오버 연마 현상을 방지한다. 또한 연마율 차이로 인해 발생하던 셀 영역(200)의 하드마스크막 패턴(1220과 주변영역(210)의 하드마스크막 패턴(122)의 단차가 없어진다. 이어서 평탄화 과정이 완료된 결과물 전면에 급속 어닐링 공정을 수행한다. 급속 어닐링 공정은 1 내지 120초 사이에서 진행한다. 이 어닐링에 의해 저에너지 이온을 주입함으로써 손상된 격자가 치유되며, 하드마스크막 패턴의 특성이 회복될 뿐더러 평탄화 공정 수행시 발생되는 파티 클(paticle)도 또한 제거된다.As shown in FIG. 4, the planarization is performed by performing a chemical mechanical planarization (CMP) method on the entire surface of the resultant product in which the landing plug contact material layer 150 is formed. In this case, the chemical mechanical planarization method is performed to expose the hard mask layer pattern 123 by using the gate hard mask layer pattern 122 of the cell region 200 as a target. Since the surface of the hard mask film 122 of the cell region 200 is weakened by ion implantation during the planarization process, the polishing rate is increased and is simultaneously planarized with the peripheral region 210. Accordingly, even when the planarization is performed based on the cell region 200, over-polishing in the peripheral region 210 is prevented due to the fast polishing rate of the cell region 200. In addition, the step difference between the hard mask film pattern 1220 of the cell region 200 and the hard mask film pattern 122 of the peripheral region 210 is eliminated due to the difference in polishing rate, and then a rapid annealing process is performed on the entire surface of the resultant flattening process. The rapid annealing process proceeds between 1 and 120 seconds, in which the damaged lattice is healed by implanting low-energy ions, which recovers the properties of the hard mask film pattern and generates particles during the planarization process. (paticle) is also removed.

이상 첨부된 도면을 참조하여 본 발명의 실시예를 설명하였으나, 본 발명은 상기 실시예에 한정되지 않으며, 본 발명의 기술적 사상내 에서 당분야의 통상의 지식을 가진 자에 의해 여러가지 변형이 가능함은 당연하다. While the embodiments of the present invention have been described with reference to the accompanying drawings, the present invention is not limited to the above embodiments, and various modifications are possible by those skilled in the art within the technical idea of the present invention. Of course.

지금까지 설명한 바와 같이, 본 발명에 따른 반도체 소자의 랜딩 플러그 컨택 형성 방법은, 패턴 밀도 차이에 의한 연마율 차이를 없애 셀 영역과 주변 영역의 연마율을 균일하게 맞추어 정밀한 평탄화 및 공정 마진을 확보하여 생산성의 향상을 제공한다.As described above, the method for forming a landing plug contact of a semiconductor device according to the present invention eliminates the difference in polishing rate due to the difference in pattern density to uniformly adjust the polishing rate of the cell region and the peripheral region to secure precise planarization and process margin. Provides an increase in productivity.

Claims (7)

패턴 밀도가 상대적으로 큰 제1 영역 및 패턴 밀도가 상대적으로 작은 제2 영역을 갖는 반도체 기판 상에 층간절연막에 의해 분리된 게이트 도전막 및 하드마스크막을 구비한 게이트 스택을 형성하는 단계;Forming a gate stack having a gate conductive film and a hard mask film separated by an interlayer insulating film on a semiconductor substrate having a first region having a relatively high pattern density and a second region having a relatively small pattern density; 상기 제1 영역을 노출시키는 베리어막을 이용하여 이온 주입 공정을 수행하는 단계;Performing an ion implantation process using a barrier film exposing the first region; 상기 제1 영역 내의 층간 절연막 일부를 제거하여 상기 제1 영역의 게이트 스택 사이에서 반도체 기판을 노출시키는 랜딩 플러그 컨택홀을 형성하는 단계;Removing a portion of the interlayer insulating layer in the first region to form a landing plug contact hole exposing the semiconductor substrate between the gate stacks of the first region; 상기 제1 영역 및 제2 영역 전면에 랜딩 플러그 컨택용 물질막을 형성하는 단계; 및 Forming a material film for a landing plug contact on the entire surface of the first region and the second region; And 상기 랜딩 플러그 컨택용 물질막을 평탄화하여 콘택 플러그를 형성하는 단계를 포함하는 반도체 소자의 랜딩 플러그 컨택 형성 방법.And forming a contact plug by planarizing the material layer for the landing plug contact. 제1항에 있어서,The method of claim 1, 상기 하드마스크막은 질화막으로 형성하는 것을 특징으로 하는 반도체 소자의 랜딩 플러그 컨택 형성 방법.And the hard mask layer is formed of a nitride layer. 제1항에 있어서,The method of claim 1, 상기 이온 주입은 실리콘 이온 또는 게르마늄 이온을 이용하여 수행하는 것 을 특징으로 하는 반도체 소자의 랜딩 플러그 컨택 형성 방법.The ion implantation method of the landing plug contact of the semiconductor device, characterized in that performed using silicon ions or germanium ions. 제1항에 있어서,The method of claim 1, 상기 이온 주입은 0.1 내지 10 Kev의 주입에너지로 수행하는 것을 특징으로 하는 반도체 소자의 랜딩 플러그 컨택 형성 방법.The ion implantation method of the landing plug contact of the semiconductor device, characterized in that performed by the implantation energy of 0.1 to 10 Kev. 제1항에 있어서,The method of claim 1, 상기 평탄화는 화학적 기계적 평탄화 방법을 사용하여 수행하는 것을 특징으로 하는 반도체 소자의 랜딩 플러그 컨택 형성 방법.Wherein said planarization is performed using a chemical mechanical planarization method. 제1항에 있어서,The method of claim 1, 상기 평탄화를 수행한 후에 급속 어닐링 공정을 수행하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자의 랜딩 플러그 컨택 형성 방법.And performing a rapid annealing process after performing the planarization. 제6항에 있어서,The method of claim 6, 상기 급속 어닐링 공정은 1 내지 120초 사이에서 수행하는 것을 특징으로 하는 반도체 소자의 랜딩 플러그 컨택 형성 방법.The rapid annealing process is performed for 1 to 120 seconds, characterized in that the landing plug contact forming method of the semiconductor device.
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