KR20080001418A - Thin film transistor substrate having a optical shutter and method thereof - Google Patents

Abstract

A TFT(Thin Film Transistor) substrate having an optical shutter and a manufacturing method thereof are provided to improve a response speed by forming the optical shutter, turned on/off by driving power, in a pixel area. Gate lines(111) are formed on a substrate. Data lines(131) cross the gate lines as leaving a space for a gate insulating layer, and define a pixel area(165). A TFT is formed in an intersection between the gate lines and the data lines. A pixel electrode(160) is electrically connected with the TFT through contact holes(151,153,154) formed in a passivation layer covering the TFT. In an oxide layer pattern(180), an open hole(181) for exposing the pixel electrode as covering the pixel area. An optical shutter(190) is formed on the oxide layer pattern and connected with the pixel electrode through the open hole.

Description

Thin film transistor substrate having optical shutter and its manufacturing method {Thin Film Transistor Substrate having a optical shutter and Method

1 is an exploded perspective view of a conventional liquid crystal display device.

2 is a plan view of a thin film transistor substrate having an optical shutter according to the present invention;

3 is a cross-sectional view of a thin film transistor substrate showing a state in which a driving power is not applied to an optical shutter according to the present invention.

4 is a cross-sectional view of a thin film transistor substrate showing a state in which a driving power is applied to an optical shutter according to the present invention.

5A and 5B are a plan view and a cross-sectional view of a thin film transistor substrate having a gate pattern according to the present invention.

6A through 6C are process diagrams illustrating a process of forming a gate pattern according to the present invention.

7A and 7B are a plan view and a cross-sectional view of a thin film transistor substrate on which a semiconductor pattern and a data pattern are formed.

8A to 8H are flowcharts illustrating a process of forming a semiconductor pattern and a data pattern according to the present invention.

9A and 9B are a plan view and a cross-sectional view of a thin film transistor substrate having a protective film according to the present invention.

10A and 10B are a plan view and a cross-sectional view of a thin film transistor substrate having a conductive pattern according to the present invention.

11A and 11B are a plan view and a cross-sectional view of a thin film transistor substrate having an oxide film pattern according to the present invention.

12A to 12C are process diagrams illustrating a process of forming an oxide film pattern according to the present invention.

13A and 13B are a plan view and a cross-sectional view of a thin film transistor substrate on which an optical shutter is formed according to the present invention.

14 is an enlarged plan view of a thin film transistor substrate on which an optical shutter is formed according to the present invention;

         <Explanation of symbols for the main parts of the drawings>

100: thin film transistor substrate 101: substrate

111: gate line 113: gate electrode

115: gate pad 117: gate pad lower electrode

119: gate pad upper electrode 120: gate insulating film

131: data line 133: source electrode

134: drain electrode 135: data pad

137: data pad lower electrode 139: data pad upper electrode

140: semiconductor pattern 141: active layer

143: ohmic contact layer 150: protective film

151: first contact hole 152: second contact hole

153: third contact hole 154: fourth contact hole

160: pixel electrode 165: pixel area

170: storage capacitor 171: storage electrode

180: oxide film pattern 181: open hole

190: Light shutter

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor substrate and a method of manufacturing the same, and more particularly, to a thin film transistor substrate having a light shutter for improving a response speed and a method of manufacturing the same.

Recently, with the arrival of the information society, the importance of an image display device that performs dynamics as a transmission medium for providing various information to users has been emphasized more than ever.

The cathode ray tube or the cathode ray tube, which has been the mainstream of such an image display device, has a problem of weight and volume, and various kinds of flat panel displays have been developed to solve such problems. have.

The flat panel display device includes a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP) and an electroluminescence (EL). Most of these are commercially available and commercially available.

Among these, liquid crystal display devices can satisfy the trend of light and short and short of electronic products and have improved mass productivity, and are rapidly replacing cathode ray tubes or CRTs in many applications.

In particular, an active matrix type liquid crystal display device that drives a liquid crystal cell using a thin film transistor (hereinafter referred to as "TFT") has the advantages of excellent image quality and low power consumption, and secures the latest mass production technology. As a result of research and development, it is rapidly developing into larger size and higher resolution.

A configuration and an operation of the liquid crystal display as described above with reference to FIG. 1 will be described below.

The liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field. As shown in FIG. 1, a thin film transistor substrate and a color filter substrate, spacers positioned to maintain a constant cell gap between two substrates, and And liquid crystal filled in the cell gap.

Here, the thin film transistor substrate 70 is connected to the gate line 71 and the data line 72 formed to cross each other, the thin film transistor 73 and the thin film transistor 73 formed at the intersections of the 71 and 72. A pixel electrode 74 and a lower alignment film (not shown) applied for liquid crystal alignment.

In this case, the thin film transistor 73 includes a source electrode connected to the data line 72, a drain electrode facing the source electrode with a channel therebetween, and a semiconductor layer forming a channel. In this case, the semiconductor layer includes an active layer forming a channel between the source electrode and the drain electrode, and an ohmic contact layer disposed on the active layer to perform ohmic contact with the source electrode and the drain electrode.

The color filter substrate 80 includes a black matrix 81 for preventing light leakage, a color filter 82 for color implementation, a common electrode 83 forming a vertical electric field with the pixel electrode 74, and an upper portion coated for liquid crystal alignment. The alignment film 84 is comprised.

In this case, the alignment layer serves to orient the liquid crystal 90 interposed between the thin film transistor substrate 70 and the color filter substrate 80 in a predetermined direction. An organic layer such as polyimide may be used on the alignment layer using a rubbing device. As the rubbing process is performed, alignment grooves (not shown) in which the liquid crystals are aligned are formed.

Here, the liquid crystal display device is completed by separately manufacturing a thin film transistor substrate and a color filter substrate, and then injecting and encapsulating a liquid crystal.

Conventionally, in the liquid crystal display device configured as described above, liquid crystal molecules 90 filled between substrates are rotated by dielectric anisotropy by an electric field formed between the pixel electrode 74 and the common electrode 73. The gray scale is realized by varying the light transmittance of the pixel region according to the degree of rotation of the pixels.

In this case, the response speed of the liquid crystal molecules corresponding to the electric field formed between the two electrodes is generally several tens of ms (milliseconds), and thus there is a limit in manufacturing a liquid crystal display device having a faster response characteristic.

SUMMARY OF THE INVENTION In order to solve the conventional problems as described above, an object of the present invention is to provide a thin film transistor substrate and a method of manufacturing the optical shutter is formed that can improve the response speed.

In order to achieve the above object, a thin film transistor substrate according to the present invention, the gate line formed on the substrate; A data line intersecting with the gate line with the gate insulating layer interposed therebetween to define the pixel region; A thin film transistor formed at an intersection of the gate line and the data line; A pixel electrode connected to the thin film transistor through a contact hole formed in the passivation layer covering the thin film transistor; An oxide film pattern covering an area of the pixel area and having an open hole for exposing the pixel electrode; And an optical shutter formed on the oxide film pattern and connected to the pixel electrode through the open hole.

The oxide film pattern according to the present invention is characterized by consisting of silicon oxide having a thickness that can transmit light.

The optical shutter according to the present invention is formed in the same pattern as the oxide film pattern.

The optical shutter according to the present invention is a thin film transistor substrate, characterized in that composed of an ink having a nanostructure.

The optical shutter according to the present invention is characterized in that when the driving power is not applied through the pixel electrode, the optical shutter is rolled up into a cylindrical shape to open the pixel region.

The optical shutter according to the present invention is characterized in that when the driving power is applied through the pixel electrode, the pixel area is flatly closed.

In addition, the method of manufacturing a thin film transistor substrate according to the present invention includes the steps of forming a gate line on the substrate; Forming a data line crossing the gate line with the gate insulating layer interposed therebetween to define a pixel region; Forming a thin film transistor at an intersection of the gate line and the data line; Forming a pixel electrode connected to the thin film transistor through a contact hole formed in the passivation layer covering the thin film transistor; Forming an oxide film pattern covering the pixel area and having open holes for exposing the pixel electrode; And forming an optical shutter formed on the oxide film pattern and connected to the pixel electrode through the open hole.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, the configuration and operation of the thin film transistor substrate according to the present invention will be described with reference to FIGS. 2 to 4. 2 is a plan view of a thin film transistor substrate on which an optical shutter is formed, FIG. 3 is a cross-sectional view of a thin film transistor substrate on which a driving power is applied to the optical shutter, and FIG. 4 is a driving power not applied to the optical shutter. A cross-sectional view of a thin film transistor substrate.

2 to 4, the thin film transistor substrate according to the present invention includes a gate line 111 formed on the substrate 101, a gate insulating film 120 covering the gate line 111, and a gate insulating film 120. And the data line 131 crossing the gate line 111 to define the pixel region 165, and the thin film transistor T formed at each intersection of the gator line 111 and the data line 131. In addition, the passivation layer 150 covering the thin film transistor T, the pixel electrode 160 electrically connected to the thin film transistor T through a contact hole penetrating the passivation layer 150, the gate line 111 and the pixel electrode. A storage capacitor 170 formed at an overlapping portion of the 160, an oxide pattern 180 formed in the pixel region 165, and an open hole 181 formed to expose the pixel electrode 160, and an oxide pattern 180. Optical shutter 19 electrically connected to the pixel electrode 160 through the open hole 181 formed in the 0).

The thin film transistor substrate according to the present invention further includes a gate pad 115 connected to the gate line 111 and a data pad 135 connected to the data line 131.

The gate line 111 transfers a gate signal supplied from a gate driver (not shown) connected to the gate pad 115 to the gate electrode 113 constituting the thin film transistor T.

The data line 131 includes a source electrode 132 and a drain constituting the thin film transistor T by interlocking a data signal supplied from a data driver (not shown) connected to the data pad 135 with ON / OFF of the gate electrode. It serves to transfer to the electrode 134.

The thin film transistor T serves to charge the pixel signal of the data line 131 to the pixel electrode 160 in response to the gate signal of the gate line 111. The thin film transistor T is connected to the gate line 111. 113, the source electrode 133 connected to the data line 131, and the pixel electrode through the first contact hole 151 facing the source electrode 133 with the channel therebetween and penetrating the passivation layer 150. A drain electrode 134 connected to 160 is provided.

In addition, the thin film transistor T overlaps the gate electrode 113 with the gate insulating layer 120 interposed therebetween, and the active layer 141 and the ohmic contact forming a channel between the source electrode 133 and the drain electrode 134. The semiconductor pattern further includes a layer 143.

The active layer 141 is also formed to overlap the lower data pad electrode 127. In this case, an ohmic contact layer 143 for ohmic contact with the source electrode 133, the drain electrode 134, and the data pad lower electrode 127 is formed on the active layer 141.

The passivation layer 150 covers the thin film transistor T formed on the gate insulating layer 120, and at the same time, the active layer 141 and the pixel region 165 forming the channel may be exposed to moisture or scratches. protects against scratches.

Here, the passivation layer 150 may be formed of a gate insulating layer 130 by sputtering or PECVD using an inorganic insulating material such as silicon nitride, an organic organic compound such as acryl-based organic compound, benzocyclobutene (BCB), or perfluorocyclobutane (PFCB). Is deposited on the substrate.

In this case, the first to fourth contact holes 151, 152, 153 and 154 are formed in the passivation layer 150 through a photolithography process and an etching process using a mask. Here, the first contact hole 151 penetrates the passivation layer 150 to expose the drain electrode 134, and the second contact hole 152 penetrates the passivation layer 150 to expose the storage electrode 171. The third contact hole 153 penetrates the passivation layer 150 and the gate insulating layer 120 to expose the gate pad lower electrode 117, and the fourth contact hole 154 penetrates the passivation layer 150 to lower the data pad. The electrode 127 is exposed.

The pixel electrode 160 is connected to the drain electrode 134 of the thin film transistor T through the first contact hole 151 penetrating the passivation layer 150 and is formed in the pixel region 165. In this case, the pixel electrode 160 is electrically connected to the optical shutter 190 through an open hole 181 formed in the oxide layer pattern 180 covering the pixel region 165.

In this case, a potential difference is formed between the pixel electrode 160 to which the pixel signal is supplied through the thin film transistor T and the common electrode (not shown) to which the common voltage is supplied, thereby electrically connecting the pixel electrode 160. The optical shutter 190 is driven on / off.

The storage capacitor 170 has a shape in which the storage electrode 171 and the previous gate line 111 overlap each other with the gate insulating layer 120 and the passivation layer 150 interposed therebetween. The storage electrode 171 is electrically connected to the pixel electrode 160 through the second contact hole 152 formed in the passivation layer 150.

The storage capacitor 170 configured as described above serves to stably maintain the pixel signal charged in the pixel electrode 160 until the next pixel signal is charged.

The oxide layer pattern 180 is patterned to cover the pixel region 165 of the thin film transistor T, and serves to improve interface characteristics so that the light shutter 190 can be easily turned on or off.

In this case, an open hole 181 is formed at one side of the oxide layer pattern 180 to electrically connect the optical shutter 190 and the pixel electrode 160.

The optical shutter 190 is formed by spraying a nanostructured ink on the oxide layer pattern 180 patterned in the pixel region 165 through an inkjet method, and the voltage difference between the pixel electrode 160 and the common electrode. It is driven on / off by to adjust the amount of light incident from the outside.

That is, when a predetermined potential difference is formed between the pixel electrode 160 and the common electrode, as shown in FIG. 3, the optical shutter 190 formed on the oxide pattern 180 of the pixel region 165 has a cylindrical shape. The rolled up portion covers the pixel region 165 by unfolding, thereby blocking light.

Subsequently, when the potential difference between the pixel electrode 160 and the common electrode is removed, as shown in FIG. 4, the optical shutter 190 covering the pixel region 165 is rolled up to transmit light. do.

At this time, the optical shutter 190 is turned on / off at a response speed having a predetermined response speed, more specifically, a rising time of 0.1 s and a falling time of 0.4 s due to a potential difference generated between the pixel electrode 160 and the common electrode. Driven off.

The gate pad 115 is connected to a gate driver (not shown) to supply a gate signal to the gate line 121.

The gate pad 115 may have a third contact hole 153 and a third contact hole 153 penetrating through the gate pad lower electrode 117, the gate insulating layer 120, and the passivation layer 150 extending from the gate line 111. The gate pad upper electrode 119 is connected to the gate pad lower electrode 117 through the?

The data pad 135 is connected to a data driver (not shown) to supply a data signal to the data line 131.

The data pad 135 may have a data pad lower electrode 137 extending from the data line 131, a lower portion of the data pad through the fourth contact hole 154 and the fourth contact hole 154 passing through the passivation layer 150. The data pad upper electrode 139 is connected to the electrode 137.

Hereinafter, a method of manufacturing a thin film transistor substrate according to the present invention will be described in detail with reference to the accompanying drawings.

First, a process of forming a gate pattern through the first mask process according to the present invention will be described with reference to FIGS. 5A and 5B.

More specifically, as shown in FIG. 6A, the gate metal layer 110a is formed on the substrate through a deposition method such as sputtering.

Subsequently, by performing a photolithography process using the first mask, a predetermined photoresist pattern PR is formed on the gate metal layer 110a as shown in FIG. 6B.

After the photoresist pattern PR is formed as described above, as illustrated in FIG. 6C, an etching process for the gate metal layer 110a exposed by the photoresist pattern PR and an ashing process for the photoresist pattern are performed. By forming the gate pattern 111, a gate pattern including the gate line 111, the gate electrode 113 connected to the gate line 111, and the gate pad lower electrode 117 is formed.

After the gate pattern is formed on the substrate 101 as described above, as shown in FIGS. 7A and 7B, the semiconductor pattern 140 and the data pattern forming the channel through the second mask process according to the present invention. 130 is formed.

More specifically, as illustrated in FIG. 8A, the gate insulating layer 120 is entirely deposited on the substrate 101 on which the gate pattern is formed. Here, the gate insulating layer 120 is made of an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx).

Subsequently, as illustrated in FIG. 8B, the active layer 141, the ohmic contact layer 143, and the data metal layer 130a are sequentially deposited on the gate insulating layer 120 through a deposition method such as PECVD or sputtering.

Here, the active layer 141 is composed of an amorphous silicon layer, and the ohmic contact layer 143 is composed of an n + amorphous silicon layer.

Subsequently, as shown in FIG. 8C, a photoresist pattern having a predetermined shape is formed on the data metal layer 130a through a photolithography process using a second mask. At this time. By using a diffraction exposure mask having a diffraction exposure portion in the channel region of the thin film transistor T as the second mask, the photoresist pattern formed in the channel region is formed to have a lower height than other regions.

After forming the photoresist pattern PR on the data metal layer 130a as described above, as shown in FIG. 8D, the wet etching of the data metal layer 130a exposed by the photoresist pattern PR is performed. etching).

Subsequently, by removing the photoresist pattern PR covering the channel region through an ashing process using an oxygen (O ₂ ) plasma, as illustrated in FIG. 8E, the data metal layer 130a formed in the channel region is removed. Expose

Then, as shown in FIG. 8F, the exposed data metal layer 130a is removed by dry etching, thereby allowing the data line 131, the source electrode 133 connected to the data line 131, and A data pattern including a drain electrode 134, a data pad lower electrode 137, and a storage electrode 171 facing the source electrode 133 is formed through the channel region.

At this time, as the source electrode 133 and the drain electrode 134 constituting the data pattern are separated, the ohmic contact layer 143 formed on the channel region is exposed to the outside.

Thereafter, the exposed ohmic contact layer 143 is removed by dry etching, as shown in FIG. 8G, between the source electrode 133 and the drain electrode 134 of the thin film transistor T. The active layer 141 forming the channel is opened.

Next, as shown in FIG. 8H, the semiconductor pattern and data pattern for channel formation are finally formed by removing the photoresist pattern PR remaining on the data pattern.

After the semiconductor pattern and the data pattern are formed as described above, as illustrated in FIGS. 9A and 9B, the first to fourth contact holes (not shown) may be formed on the substrate 101 using the third mask process according to the present invention. The passivation layer 150 having the 151, 152, 153, and 154 formed thereon is formed.

In more detail, the passivation layer 150 is entirely formed on the gate insulating layer 130 on which the data pattern 160 is formed by a deposition method such as PECVD.

Thereafter, the first to fourth contact holes 151, 152, 153, and 154 are formed on the passivation layer 150 by performing a photolithography process and an etching process on the passivation layer 170 using the third mask.

Here, the first contact hole 151 penetrates the passivation layer 150 to expose the drain electrode 164, and the second contact hole 172 penetrates the passivation layer 170 to expose the storage electrode 191. The third contact hole 173 penetrates the passivation layer 150 and the gate insulating layer 130 to expose the gate pad lower electrode 127, and the fourth contact hole 174 penetrates the passivation layer 150 to lower the data pad. The electrode 167 is exposed.

After the protective film 170 having the plurality of contact holes is formed as described above, as illustrated in FIGS. 10A and 10B, the pixel electrode (not shown) is formed on the protective film 150 through the fourth mask process according to the present invention. 160, a transparent electrode pattern including the gate pad upper electrode 119 and the data pad upper electrode 139 is formed.

In more detail, the transparent electrode material (ITO) is deposited on the entire surface of the protective layer 170 on which the plurality of contact holes are formed through a deposition method such as sputtering.

In this case, indium tin oxide (ITO), tin oxide (TO), or indium zinc oxide (IZO) may be used as the transparent electrode material.

Subsequently, the pixel electrode 160, the gate pad upper electrode 119, and the data pad are formed on the passivation layer 170 by patterning the transparent electrode material ITO through a photolithography process and an etching process using a fourth mask. A transparent electrode pattern including the upper electrode 139 is formed.

Here, the pixel electrode 160 is connected to the drain electrode 134 of the thin film transistor T through the first contact hole 151 formed in the passivation layer 150, and the storage electrode (eg, through the second contact hole 152). 171 is connected to the optical shutter 190 through an open hole 181 formed in the oxide layer pattern 180.

In addition, the gate pad upper electrode 119 is electrically connected to the gate pad lower electrode 117 through the third contact hole 153 formed in the passivation layer 150, and the data pad upper electrode 139 is the fourth contact hole. It is electrically connected to the data pad lower electrode 137 through 154.

After the transparent electrode pattern is formed as described above, as illustrated in FIGS. 11A and 11B, the pixel region 165 includes the oxide layer pattern 180 on which the open hole 181 is formed to expose the pixel electrode according to the present invention. To form).

More specifically, as illustrated in FIG. 12A, an oxide film SiO ₂ is entirely formed on the substrate 101 on which the transparent electrode pattern is formed.

Then, by performing a photolithography process using a fifth mask, as shown in FIG. 12B, the photoresist pattern PR is formed on the oxide film formed in the pixel region 165.

Subsequently, by performing an etching process on the oxide film exposed by the photoresist pattern, as shown in FIG. 12C, an oxide film having an open hole 181 covering the pixel region 165 and exposing the pixel electrode 160 is formed. The pattern 180 is formed.

After forming the oxide film pattern as described above, as shown in FIGS. 13A and 13B, the optical shutter 190 driven on / off by a potential difference formed between the pixel electrode 160 and the common electrode according to the present invention. To form.

That is, an optical shutter having a shape corresponding to that of the oxide film pattern 180 formed in the pixel region 165 is sprayed by spraying ink having a nanostructure by using an inkjet nozzle on the pixel region 165 on which the oxide film pattern 180 is formed. 190).

Here, one end of the optical shutter 190 is electrically connected to the pixel electrode 160 through an open hole 181 formed in the oxide film pattern 180.

In this case, when the potential difference is not formed between the pixel electrode 160 and the common electrode, as shown in FIG. 14, the optical shutter 190 has an end portion at which the other end of the optical shutter 190 is not electrically connected to the pixel electrode 160. It has a shape rolled up into a cylindrical shape.

Therefore, when the potential difference is not formed, the optical shutter 190 serves to pass the light incident from the light source to the outside.

However, when a potential difference is formed between the pixel electrode 160 and the common electrode, the optical shutter 190 has a shape in which the other end portion of the optical shutter 190 is not electrically connected to the pixel electrode 160.

Therefore, the optical shutter 190 serves to block light incident from the light source when the potential difference is formed.

As described above, the present invention has an effect that the response speed can be improved by forming an optical shutter driven on / off by a driving power source in the pixel region.

In addition, the present invention has the effect that the process time and process can be simplified by forming the optical shutter using an ink jet instead of a complicated process such as injecting liquid crystal between the substrate.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (14)

A gate line formed on the substrate; A data line crossing the gate line with a gate insulating layer interposed therebetween to define a pixel area; A thin film transistor formed at an intersection portion of the gate line and the data line; A pixel electrode electrically connected to the thin film transistor through a contact hole formed in the passivation layer covering the thin film transistor; An oxide layer pattern covering the pixel area and having an open hole for exposing the pixel electrode; And And a photo shutter formed on the oxide layer pattern and connected to the pixel electrode through the open hole. The method of claim 1, The oxide film pattern is a thin film transistor substrate, characterized in that composed of silicon oxide having a thickness that can transmit light. The method of claim 1, The optical shutter is thin film transistor substrate, characterized in that formed in the same pattern as the oxide film pattern. The method of claim 1, The optical shutter is a thin film transistor substrate, characterized in that consisting of ink having a nano structure. The method of claim 1, When no driving power is applied through the pixel electrode, the optical shutter is rolled up into a cylindrical shape to open the pixel area. And when the driving power is applied through the pixel electrode, the optical shutter flatly closes the pixel region. The method according to any one of claims 1 to 5, The response speed of the optical shutter is a thin film transistor substrate, characterized in that the rising time is about 0.1㎳ and the falling time is about 0.4㎳. Forming a gate line on the substrate; Forming a data line crossing the gate line with a gate insulating layer interposed therebetween to define a pixel area; Forming a thin film transistor at an intersection portion of the gate line and the data line; Forming a pixel electrode connected to the thin film transistor through a contact hole formed in the passivation layer covering the thin film transistor; Forming an oxide layer pattern covering the pixel area and forming an open hole for exposing the pixel electrode; And And forming an optical shutter formed on the oxide layer pattern and connected to the pixel electrode through the open hole. The method of claim 7, wherein forming the oxide film pattern, Forming an oxide film on the substrate on which the pixel electrode is formed; Forming a photoresist pattern on the oxide film through a mask process; Etching the oxide film exposed by the photoresist pattern; And Ashing the photoresist pattern remaining on the etched oxide film Method of manufacturing a thin film transistor substrate comprising a. The method of claim 8, And forming an open hole for exposing the pixel electrode formed in the pixel region to the outside. The method of claim 8, The oxide film pattern is a method of manufacturing a thin film transistor substrate, characterized in that consisting of silicon oxide having a thickness that can transmit light. The method of claim 7, wherein The optical shutter is formed in the same pattern as the oxide film pattern by an inkjet method. The method of claim 7, wherein The optical shutter is a method of manufacturing a thin film transistor substrate, characterized in that consisting of ink having a nano structure. The method of claim 7, wherein When no driving power is applied through the pixel electrode, the optical shutter is rolled up into a cylindrical shape to open the pixel area. And when the driving power is applied through the pixel electrode, the optical shutter flatly closes the pixel region. The method of claim 7, wherein The response speed of the optical shutter has a rising time of about 0.1 ms and a polling time of about 0.4 ms.

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