KR20070122035A - Method for manufacturing semiconductor device - Google Patents

Abstract

A method of fabricating a semiconductor device is provided to simultaneously perform a repair etching process and a pad etching process by using one etching mask. A substrate with a fuse(12) is prepared, and then interlayer dielectrics(11,13) of oxide layer series are formed to cover the fuse. A pad(14) is formed on the interlayer dielectric not to correspond to the fuse. An etching barrier layer(15) of nitride layer series is formed on the pad, and then a protective layer(16) of oxide layer series is formed on the entire surface to cover the etching barrier layer. An etching mask is formed to have openings corresponding to the pad and the fuse. The protective layer is subjected to a first etching process until the etching barrier is exposed. A second etching process of the substrate is performed until the pad is exposed and the interlayer dielectric remains on the fuse.

Description

Manufacturing method of semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

1 and 2 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

11: lower interlayer insulating film

12: fuse

13: upper interlayer insulating film

14: Pad

15: etching barrier layer

16: protective layer

17 photosensitive film pattern

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to an etching method for opening a pad and a fuse for repair of a semiconductor memory device.

In general, a DRAM (Dynamic Random Access Memory) device has a separate redundancy cell to replace a defective memory cell. These spare cells are manufactured at the same time in the normal memory cell manufacturing process and are used in place of the defective memory cells. Such a process of replacing a defective memory cell with a spare cell is called a repair process.

In the repair process, a program is performed in an internal circuit to select a bad memory cell and replace the corresponding address with the address of the spare cell. Therefore, when an address corresponding to a bad line is input in actual use, the selection is switched to the line of the spare cell instead. One of the programming methods is a method of burning a wire by a laser beam and breaking the wire. The wire broken by the laser is called a fuse.

In general, fuses are simultaneously formed through an etching process performed during a word line or bit line forming process in a DRAM device manufacturing process to simplify the process. It is formed of a polysilicon layer (poly silicon layer) of the same material as. However, in recent years, in consideration of the integration degree and the operating speed of the semiconductor memory device, it is formed of a metal material instead of the polysilicon film.

Prior to the repair process, an etching process (hereinafter referred to as a repair etching process) is performed to leave an insulating film, such as an oxide film, deposited on the fuse to a predetermined thickness. Recently, in order to simplify the process, one etching mask is used in the repair etching process to leave a certain thickness of the oxide film deposited on the fuse and at the same time open a pad for wire bonding. . In this case, in order to open the pad, not only the oxide film but also the TiN film formed as an etch barrier layer on the pad must be etched.

As described above, when the repair etching process and the etching process for releasing the pad (hereinafter referred to as the pad etching process) are simultaneously performed using one etching mask, the thickness of the oxide film remaining on the pad opening and the fuse is controlled simultaneously. There are many difficulties.

For example, target thickness control of the oxide film remaining on the fuse in a state where the interlayer insulating film between the fuse and the pad is sufficiently thick, which is formed relatively thicker than the thickness of the passivation layer formed on the interlayer insulating film. When the etching process is performed, overetch occurs in the pad area, and the TiN film on the upper part of the pad is removed. However, in a state where the interlayer insulating film between the fuse and the pad is not formed sufficiently thick, which is formed relatively thinner than the thickness of the protective layer, sufficient transient etching is not performed, thereby causing a problem in that the TiN film is not removed.

Accordingly, the thickness of the interlayer insulating film may be formed relatively thicker than that of the protective layer, and then the etching process may be performed. In this case, the metal wiring or the metal layer formed on the same layer at the same time as the metal wiring of the other part is opened. Many difficulties arise in the via etching process. As described above, since there is a limit in forming a thick interlayer insulating film in the process, Cl ₂ gas is supplied to the TiN film remaining on the pad after securing a certain thickness of the interlayer insulating film in consideration of the process. The plasma etch process is performed to remove. However, in this case, since the etch rate of the pad made of Al is higher than that of the TiN film, more pads are removed than the amount of the TiN film is removed, thereby causing a problem that the uniformity of the pad surface is lowered.

Accordingly, the present invention has been made to solve the above-mentioned problems of the prior art, and provides a method of manufacturing a semiconductor device which can simultaneously perform a repair etching process and a pad etching process using a single etching mask without damaging the pad. Its purpose is to.

According to an aspect of the present invention, there is provided a method including providing a substrate on which a fuse is formed, forming an interlayer insulating layer of an oxide-based material to cover the fuse, and not corresponding to the fuse. Forming a pad on the interlayer insulating film, forming an etch barrier layer of a nitride based material on the pad, and forming a protective layer of an oxide based material on the entire structure to cover the etch barrier layer Forming an etching mask having an opening at a portion corresponding to the pad and the fuse, and performing a first etching process using the etching mask to etch the protective layer until the etching barrier layer is exposed. And performing a second etching process using the etching mask to expose the pad and to a predetermined thickness on the fuse. Retaining the interlayer insulating film, wherein the second etching process is at least one of the wafer chuck temperature, pressure, bias power and the amount of fluorocarbon gas to control the etch rate of the oxide-based material and the nitride-based material A method of manufacturing a semiconductor device is performed by adjusting any one parameter.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, the same reference numerals throughout the specification represent the same components.

Example

1 to 3 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

First, as shown in FIG. 1, the pad is defined as a region PAD (hereinafter referred to as a pad region) and a region in which a fuse is to be formed (FUSE) (hereinafter referred to as a fuse region). Accordingly, a semiconductor substrate (not shown) on which a predetermined semiconductor structure layer is formed is prepared.

Subsequently, a lower interlayer insulating film 10 is formed on the semiconductor substrate. In this case, the lower interlayer insulating film 10 is formed of an oxide film-based material. For example, it is formed of Boron Phosphorus Silicate Glass (BPSG), Phosphorus Silicate Glass (PSG), Tetra Ethyle Ortho Silicate (TEOS), or the like.

Subsequently, a fuse 12 is formed in the fuse region FUSE on the lower interlayer insulating layer 10. In this case, the fuse 12 is formed of a polysilicon film or a metal-based material.

Subsequently, an upper interlayer insulating layer 13 is formed on the entire structure to cover the fuse 12. In this case, the upper interlayer insulating layer 13 is formed of an oxide-based material similarly to the lower interlayer insulating layer 11.

Subsequently, the pad 14 and the etch barrier layer 15 are formed in the pad region PAD on the upper interlayer insulating layer 13. In this case, the pad 14 is formed of an Al film, and the etch barrier layer 15 is formed of a TiN film.

A protective layer 16 is then formed over the entire structure to cover the pad 14 and the etch barrier layer 15. In this case, the protective layer 16 is formed of an oxide-based material having an etch selectivity with respect to the etch barrier layer 15.

Subsequently, after the photosensitive film is coated on the protective layer 16, the photosensitive film pattern 17 is formed by performing exposure and development processes using a photo mask.

Subsequently, the repair etching process and the pad etching process are performed using a single mask of the photoresist pattern 17. At this time, the repair etching process and the pad etching process is carried out in two steps.

First, as shown in FIG. 1, the first etching process 18 uses an etching selectivity between the protective layer 16 and the etching barrier layer 15, that is, an etching selectivity between the TiN film and the oxide film. 15) until it is exposed. As a result, a first contact hole 19A through which the etch barrier layer 15 is exposed is formed in the pad region PAD, and a second contact is formed inside the protective layer 16 in the fuse region FUSE. A second contact hole 19B is formed.

Subsequently, as shown in FIG. 2, a second etching process 20 is performed. The etching process 20 uses a plasma etching apparatus to adjust the etching selectivity between the TiN film and the oxide film to expose the pad 14 and to leave the oxide film with a predetermined thickness on the upper portion of the fuse 12. At this time, the technical principle for controlling the etching selectivity between the TiN film and the oxide film is shown in Table 1.

Parameter TiN Etch Rate Oxide etching rate Wafer chuck temperature Increase when temperature rises Decrease in temperature rise pressure Highest at 15-30 mTorr Highest at medium pressure RF bias power Low dependency High dependency Fluorocarbon gas quantity Relatively small decrease due to gas volume reduction Larger amount of gas decreases

As shown in Table 1, the etching selectivity between the TiN film and the oxide film can be adjusted by controlling the process conditions in the plasma etching equipment. Parameters affecting the etch rate between the TiN film and the oxide film under the process conditions include wafer chuck temperature, pressure, RF bias power, and fluoro-carbon gas amount.

The etching rate of the TiN film increases as the wafer temperature increases, whereas the etching rate of the oxide film decreases. In addition, the etching rate of the TiN film is the highest at a relatively low pressure of 15 ~ 30mTorr, the oxide film etching rate is highest at a medium pressure higher than the low pressure. In addition, the etching rate of the TiN film has a lower dependence on RF bias power than the oxide film. That is, the etch rate of the oxide film has a threshold value rapidly decreasing below a certain bias power, and the threshold value is very high. On the other hand, although the etching rate of the TiN film tends to increase until the predetermined bias power, the etching rate tends to be lower than that of the oxide film. In addition, the etching rate of the oxide film is significantly reduced than the TiN film as the fluorine carbon gas amount decreases.

Accordingly, by appropriately adjusting the parameters in Table 1 during the second etching process 20, the protective layer 16 and the interlayer insulating layer 13 are etched while the TiN film is etched to expose the pad 14 without using Cl ₂ gas. Thus, an oxide film is left on the fuse 12 at a predetermined thickness.

Meanwhile, in FIG. 2, '21A' and '21B' are a third and fourth contact holes simultaneously formed by the etching process 20, and '16A' is an etching process 20. Shows a protective layer patterned by &quot; 13A &quot; and indicates an interlayer insulating film patterned by the etching process 20. FIG.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the etching process is performed by appropriately controlling the parameters affecting the etching rate between the TiN film and the oxide film, so that the repair etching process and the pad etching process are performed using one etching mask without damaging the pad. Can be performed simultaneously.

Claims (2)

Providing a substrate having a fuse formed thereon; Forming an interlayer insulating layer of an oxide-based material to cover the fuse; Forming a pad on the interlayer insulating layer so as not to correspond to the fuse; Forming an etch barrier layer on the pad using a nitride film-based material; Forming a protective layer of an oxide-based material on the entire structure to cover the etch barrier layer; Forming an etching mask having an opening in a portion corresponding to the pad and the fuse; Performing a first etching process using the etching mask to etch the protective layer until the etching barrier layer is exposed; And Performing a second etching process using the etching mask to expose the pad and to leave the interlayer insulating layer at a predetermined thickness on the fuse; The second etching process may be performed by adjusting at least one parameter of wafer chuck temperature, pressure, bias power, and fluorine carbon gas amount to control an etch rate of the oxide based material and the nitride based material. Manufacturing method. The method of claim 1, The nitride film-based material is a TiN film manufacturing method of a semiconductor device.

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