KR20070111165A - Removing method of copper diffusion barrier layer - Google Patents

Removing method of copper diffusion barrier layer Download PDF

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KR20070111165A
KR20070111165A KR1020060044190A KR20060044190A KR20070111165A KR 20070111165 A KR20070111165 A KR 20070111165A KR 1020060044190 A KR1020060044190 A KR 1020060044190A KR 20060044190 A KR20060044190 A KR 20060044190A KR 20070111165 A KR20070111165 A KR 20070111165A
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diffusion barrier
copper diffusion
copper
barrier layer
chamber
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KR1020060044190A
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Korean (ko)
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최부경
박래춘
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동부일렉트로닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching

Abstract

A method for removing a copper diffusion barrier layer is provided to prevent deterioration of a physical characteristic of copper by minimizing the time difference between etching of a copper diffusion barrier layer and deposition of a barrier metal. A copper diffusion barrier layer is removed from an etch chamber(30) for the copper diffusion barrier layer in a fabricating process for forming a copper interconnection on a semiconductor substrate. The etch chamber for the copper diffusion barrier layer and a deposition chamber(40) for the barrier metal are incorporated in a system to etch the copper diffusion barrier layer. CF4 and Ar mixture gas is used as an etch gas in the etch chamber for the copper diffusion barrier layer. Pressure of 100-180 milliTorr, a source power of 300-5000 watts, bias power of 100-300 watts and CF4 of 10-20 sccm and Ar of 200-500 sccm are used in the etch chamber.

Description

구리 확산 방지막 제거 방법 {Removing Method of Copper Diffusion Barrier Layer}Removing Method of Copper Diffusion Barrier Layer

도 1은 기존 방법에 의한 구리확산방지막 식각챔버와 베리어 메탈 증착챔버의 운전 개략도,1 is a schematic view of an operation of a copper diffusion barrier etching chamber and a barrier metal deposition chamber according to a conventional method;

도 2는 본 발명에 의한 구리확산방지막 식각챔버와 베리어 메탈 증착챔버의 운전 개략도,2 is a schematic view of the operation of the copper diffusion barrier etching chamber and the barrier metal deposition chamber according to the present invention;

도 3은 구리확산방지막 식각에서 베리어 메탈 증착까지의 시간에 따른 수율 및 비아홀 저항을 나타낸다.3 shows the yield and via hole resistance over time from copper diffusion barrier etching to barrier metal deposition.

본 발명은 구리확산방지막 제거 방법에 관한 것으로서, 상세하게는 구리배선을 형성하기 위한 공정에서 트렌치 식각 공정 이후에 구리확산방지막이 식각된 후 베리어메탈증착까지의 시간차이를 최소화하여 구리의 물성저하를 방지하도록 한 구리확산방지막 제거방법에 관한 것이다.The present invention relates to a method for removing a copper diffusion barrier, and in detail, to minimize the time difference between the copper diffusion barrier after the trench etching process and the deposition of the barrier metal in the process for forming copper wiring, thereby minimizing copper physical property degradation. The present invention relates to a method for removing a copper diffusion barrier that is prevented.

반도체 회로가 고집적화되면서 금속 배선의 물질로 알루미늄(Al)보다 비저항이 낮으면서 동시에 신뢰성(Reliability)이 우수한 구리(Cu)를 사용하게 되었다.As semiconductor circuits have been highly integrated, copper (Cu), which has lower resistivity than aluminum (Al) and has excellent reliability, has been used as a material for metal wiring.

그러나 구리는 이를 금속 배선으로 사용하기에는 많은 문제점을 가지고 있다. 구리는 휘발성이 강한 화합물의 형성이 어려워 미세 패턴을 형성하기 위한 건식 식각 공정에 어려움이 있다. 또한 산화물과 실리콘에서 빠르게 확산되는데, 만약 구리가 실리콘의 활성 영역(예를 들면 트랜지스터의 소스, 드레인, 게이트 영역)에 확산된다면 접합이나 산화물 누설을 발생시켜서 소자에 손상을 입히게 되는 문제가 있다. 또한 구리는 저온(200℃ 이하)의 대기에서 쉽게 산화되며, 산화시 또 다른 산화를 정지할 수 있는 보호층을 형성하지 않는다.However, copper has many problems to use it as metal wiring. Since copper is difficult to form a highly volatile compound, there is a difficulty in a dry etching process for forming a fine pattern. In addition, it diffuses rapidly in oxides and silicon. If copper diffuses into active regions of silicon (eg, transistor source, drain, and gate regions), there is a problem of damaging the device by generating a junction or oxide leakage. In addition, copper is easily oxidized at low temperatures (200 ° C. or lower) and does not form a protective layer that can stop another oxidation upon oxidation.

이러한 문제를 해결하기 위하여 생각해 낸 것이 특별한 베리어 메탈들로 최적화된 다마신 공법이다. 그 중 현재 많이 사용되고 있는 듀얼다마싱 공정에 대하여 좀 더 자세히 살펴보면, 먼저 하부 기판에 형성된 구리 배선상에 구리 확산방지막과 층간절연막등을 형성한다. 여기서 구리 확산방지막은 식각저지막의 역할도 수행할 수 있는데, 이는 주로 실리콘 질화물(SiN), 실리콘 카바이드(SiC), 실리콘 시아나이드(SiCN)등으로 만들어진다. 그 후 상부 배선과의 접속을 형성하기 위하여 패터닝 노광 식각등의 공정을 통하여 비아와 트랜치를 형성한다. 계속해서 상기 구리확산방지막(SiN등)을 식각한 후, 비아와 트랜치에 베리어 메탈을 물리적기상증착 법(PVD) 또는 화학기상증착법(CVD)를 이용하여 증착시킨다. 그 후 상기 베리어메탈 내부를 구리로 채운 다음에 화학적 기계 평탄화(CMP)공정으로 여분의 구리를 갈아내어 구리배선을 형성한다.To solve this problem, one came up with a damascene method optimized with special barrier metals. The dual damascene process, which is widely used among them, will be described in more detail. First, a copper diffusion barrier layer and an interlayer dielectric layer are formed on a copper wiring formed on a lower substrate. The copper diffusion barrier may also serve as an etch stop layer, which is mainly made of silicon nitride (SiN), silicon carbide (SiC), silicon cyanide (SiCN), or the like. Thereafter, vias and trenches are formed through a process such as patterned exposure etching to form a connection with the upper wiring. Subsequently, the copper diffusion barrier layer (SiN, etc.) is etched, and the barrier metal is deposited on vias and trenches using physical vapor deposition (PVD) or chemical vapor deposition (CVD). Thereafter, the barrier metal is filled with copper, and the copper is removed by grinding excess copper by a chemical mechanical planarization (CMP) process.

상기 공정 중 본 발명과 관련된 구리확산방지막이 식각된 후 베리어 메탈 증착까지 공정의 현재 운전형태를 살펴보면, 도 1에서 보는 바와 같이, 웨이퍼가 수납된 카세트(11)가 로드락 챔버(LoadLock Chamber)(21)로 로딩된다. 로딩된 카세트 내의 웨이퍼는 로드락챔버(21)에서 구리확산방지막식각챔버(30)로 트랜스퍼되어서 트랜치나 비아의 하부의 구리확산방지막을 식각하고 로드락챔버(21)로 다시 트랜스퍼된다. 그 후 웨이퍼는 카세트에 모여져서 베리어메탈증착챔버의 로드락챔버(22)로 트랜스퍼된다. 다시 웨이퍼가 수납된 카세트(11)는 베리어메탈증착챔버의 로드락챔버(22)로 로딩이 되고, 로딩된 카세트내의 웨이퍼는 베리어 메탈 증착챔버(40)로 트랜스퍼된다. 베리어 메탈증착챔버(40)에서 베리어 메탈이 증착된 후 다시 로드락챔버(22)로 트랜스퍼되는 과정을 거치게 된다. 그러나 웨이퍼가 구리확산 방지막 식각챔버(30)에서 로드락 챔버(21)로 트랜스퍼된 후에 베리어 메탈 증착 챔버(40)에 트랜스퍼되기까지는 최소 한시간이상이 걸리는데, 이 과정에서 구리가 공기 중에 노출이 되어 산화막을 형성하게 되고, 이 산화막의 두께에 따라서 수율 및 비아홀 저항이 변하게 되는 문제점이 있다(도 3). Looking at the current operation of the process from the copper diffusion barrier to the barrier metal deposition after the etching of the copper diffusion film related to the present invention, as shown in Figure 1, the cassette 11 containing the wafer is a load lock chamber (LoadLock Chamber) ( 21). The wafer in the loaded cassette is transferred from the load lock chamber 21 to the copper diffusion barrier etch chamber 30 to etch the copper diffusion barrier below the trench or via and back to the load lock chamber 21. The wafer is then collected in a cassette and transferred to the load lock chamber 22 of the barrier metal deposition chamber. The cassette 11 containing the wafer is loaded into the load lock chamber 22 of the barrier metal deposition chamber, and the wafer in the loaded cassette is transferred to the barrier metal deposition chamber 40. After the barrier metal is deposited in the barrier metal deposition chamber 40, the barrier metal is deposited and then transferred to the load lock chamber 22. However, it takes at least an hour before the wafer is transferred from the copper diffusion barrier etching chamber 30 to the load lock chamber 21 and then transferred to the barrier metal deposition chamber 40. In this process, the copper is exposed to air and the oxide film is exposed. There is a problem in that the yield and the via hole resistance change depending on the thickness of the oxide film (Fig. 3).

본 발명은 이러한 비아홀 저항 페일(Fail) 등을 해결하기 위해 구리확산 방 지막 식각과 베리어 메탈 증착 사이의 시간차이를 최소화시켜서 구리의 물성저하를 방지하여 반도체 수율을 향상시킬 수 있도록 한 구리확산방지막 제거 방법을 제공하고자 함에 그 목적이 있다.The present invention eliminates the copper diffusion barrier to improve the semiconductor yield by preventing the degradation of copper properties by minimizing the time difference between the copper diffusion barrier etching and the barrier metal deposition in order to solve such a via hole resistance fail (Fail), etc. The purpose is to provide a method.

본 발명에 의한 구리확산방지막 제거 방법은 구리확산방지막 식각챔버와 베리어 메탈 증착챔버를 하나의 시스템화하여 구리확산방지막을 식각하는 것을 특징으로 한다. 이로서 구리확산 방지막의 식각과 베리어메탈의 증착 사이의 시간차이를 최소화하여 구리의 산화에 따른 물성저하를 방지하여 반도체의 수율을 향상시킬 수 있다.The method for removing a copper diffusion barrier according to the present invention is characterized by etching the copper diffusion barrier by forming a single system of the copper diffusion barrier etching chamber and the barrier metal deposition chamber. This minimizes the time difference between the etching of the copper diffusion barrier and the deposition of the barrier metal to prevent degradation of properties due to the oxidation of copper, thereby improving the yield of the semiconductor.

도 2는 본 발명에 의한 구리확산방지막 식각챔버와 베리어 메탈 증착챔버의 운전 개략도인데, 이에 근거하여 구리확산방지막 제거방법에 대하여 상세히 설명하면 다음과 같다.FIG. 2 is a schematic view illustrating the operation of the copper diffusion barrier etching chamber and the barrier metal deposition chamber according to the present invention.

본 발명에 따른 구리확산방지막을 제거하는 공정은 먼저 웨이퍼가 수납된 카세트(13)가 로드락 챔버(23)로 로딩되어 진다. 이후 로딩된 카세트내의 웨이퍼는 한장씩 구리 확산방지막 식각챔버(30)로 트랜스퍼되어져서, 구리확산방지막 식각챔버(30)에서 구리확산방지막이 식각된다. In the process of removing the copper diffusion preventing film according to the present invention, the cassette 13 containing the wafer is first loaded into the load lock chamber 23. Thereafter, the wafers in the loaded cassette are transferred to the copper diffusion barrier etching chamber 30 one by one, so that the copper diffusion barrier is etched in the copper diffusion barrier etching chamber 30.

이 때 구리확산방지막 식각챔버의 운전조건은 압력 : 0~180mT, 소스파 워(Source Power) : 300~500W, 바이어스 파워(Bias Power) : 100~300W이다. 식각가스로서 CF4와 Ar 혼합가스 또는 CF4/CHF3와 Ar 혼합가스를 사용하는데, 가스공급량은 CF4와 Ar 혼합가스인 경우에는 CF4 : 10~20sccm, Ar : 200~500sccm이고, CF4/CHF3와 Ar 혼합가스인 경우에는 CF4 : 5~15sccm, CHF3 : 5~15sccm, Ar : 200~500sccm이다. At this time, the operating conditions of the copper diffusion barrier etching chamber are pressure: 0 ~ 180mT, source power: 300 ~ 500W, bias power: 100 ~ 300W. As the etching gas, CF 4 and Ar mixed gas or CF 4 / CHF 3 and Ar mixed gas are used.In case of CF 4 and Ar mixed gas, CF 4 : 10 ~ 20sccm, Ar: 200 ~ 500sccm, CF 4 / CHF 3 and Ar mixed gas is CF 4 : 5 ~ 15sccm, CHF 3 : 5 ~ 15sccm, Ar: 200 ~ 500sccm.

계속해서 구리확산방지막 식각챔버(30)에서 구리확산방지막이 식각된 웨이퍼가 한 시스템 내에 있는 베리어메탈 증착챔버(40)로 트랜스퍼되어진다. 따라서 기존 방법에 비하여 웨이퍼의 구리확산방지막의 식각과 베리어 메탈 증착사이의 시간을 최소화시킬 수 있어 구리의 물성저하를 방지할 수 있다. 한편, 베리어메탈 증착챔버(40)로 트랜스퍼된 웨이퍼는 베리어메탈증착 챔버(40)에서 비아와 트랜치에 베리어 메탈을 물리적기상증착법(PVD) 또는 화학기상증착법(CVD)를 이용하여 증착하게 된다. 베리어 메탈이 증착된 웨이퍼가 다시 로드락챔버(23)로 트랜스퍼되어 지고, 여기서 카세트에 모여서 다음 공정으로 트랜스퍼된다.Subsequently, the wafer in which the copper diffusion barrier is etched from the copper diffusion barrier etching chamber 30 is transferred to the barrier metal deposition chamber 40 in the system. Therefore, compared with the conventional method, the time between etching the copper diffusion barrier of the wafer and the barrier metal deposition can be minimized, thereby preventing the deterioration of copper properties. On the other hand, the wafer transferred to the barrier metal deposition chamber 40 is to deposit the barrier metal on the via and trench in the barrier metal deposition chamber 40 using physical vapor deposition (PVD) or chemical vapor deposition (CVD). The wafer on which the barrier metal is deposited is transferred back to the load lock chamber 23 where it is collected in a cassette and transferred to the next process.

구리확산방지막 식각 챔버와 베리어메탈 증착챔버를 하나의 시스템화 함으로써 구리 확산방지막의 식각과 베리어 메탈의 증착 사이의 시간 지연으로 인한 구리의 물성 저하를 최소화시켜 반도체의 수율을 향상시킬 수 있다.By systemizing the copper diffusion barrier etching chamber and the barrier metal deposition chamber into a single system, the semiconductor yield can be improved by minimizing the deterioration of copper properties due to the time delay between the etching of the copper diffusion barrier and the deposition of the barrier metal.

Claims (3)

반도체 기판상에 구리배선을 형성하기 위한 공정 중 구리확산방지막 식각챔버에서 구리확산방지막을 제거하는 방법에 있어서, 상기 구리확산방지막 식각챔버와 베리어 메탈 증착챔버를 하나의 시스템화하여 상기 구리확산방지막을 식각하는 것을 특징으로 하는 구리 확산방지막 제거방법.A method of removing a copper diffusion barrier from a copper diffusion barrier etching chamber during a process of forming a copper wiring on a semiconductor substrate, wherein the copper diffusion barrier etching chamber and the barrier metal deposition chamber are systemized to etch the copper diffusion barrier. Copper diffusion barrier film removal method characterized in that. 제1항에 있어서, 상기 구리 확산방지막 식각챔버는 식각가스로 CF4와 Ar 혼합가스를 사용하며, 상기 구리확산방지막 식각챔버는 압력 : 100~180mT, 소스파워(Source Power) : 300~500W, 바이어스 파워(Bias Power) : 100~300W, CF4 : 10~20sccm, Ar : 200~500sccm으로 운전되는 것을 특징으로 하는 구리 확산방지막 제거방법.The method of claim 1, wherein the copper diffusion barrier etching chamber is a CF 4 and Ar mixed gas as an etching gas, the copper diffusion barrier etching chamber is pressure: 100 ~ 180mT, Source Power: 300 ~ 500W, Bias power: 100 ~ 300W, CF 4 : 10 ~ 20sccm, Ar: 200 ~ 500sccm It is characterized in that the copper diffusion barrier removal method. 제1항에 있어서, 상기 구리 확산방지막 식각챔버는 식각가스로 CF4/CHF3와 Ar 혼합가스를 사용하며, 상기 구리확산방지막 식각챔버는 압력 : 100~180mT, 소스파워(Source Power) : 300~500W, 바이어스 파워(Bias Power) : 100~300W, CF4 : 5~15sccm, CHF3 : 5~15sccm, Ar : 200~500sccm으로 운전되는 것을 특징으로 하는 구리 확산방지막 제거방법.The method of claim 1, wherein the copper diffusion barrier etching chamber is a mixture of CF 4 / CHF 3 and Ar as an etching gas, the copper diffusion barrier etching chamber is pressure: 100 ~ 180mT, Source Power: 300 ~ 500W, bias power (Bias Power): 100 ~ 300W, CF 4 : 5 ~ 15sccm, CHF 3 : 5 ~ 15sccm, Ar: 200 ~ 500sccm It characterized in that the copper diffusion barrier removal method.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01149957A (en) * 1987-12-07 1989-06-13 Hitachi Ltd Method and device for forming thin film
KR20020094599A (en) * 2001-06-12 2002-12-18 주식회사 하이닉스반도체 Cu film deposition equipment of semiconductor device
JP2003273212A (en) * 2002-03-14 2003-09-26 Fujitsu Ltd Laminate structure and its manufacturing method
JP2004071774A (en) * 2002-08-05 2004-03-04 Tokyo Electron Ltd Plasma processing method using multi-chamber system

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01149957A (en) * 1987-12-07 1989-06-13 Hitachi Ltd Method and device for forming thin film
KR20020094599A (en) * 2001-06-12 2002-12-18 주식회사 하이닉스반도체 Cu film deposition equipment of semiconductor device
JP2003273212A (en) * 2002-03-14 2003-09-26 Fujitsu Ltd Laminate structure and its manufacturing method
JP2004071774A (en) * 2002-08-05 2004-03-04 Tokyo Electron Ltd Plasma processing method using multi-chamber system

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