KR20070107886A - Repair circuit of semiconductor memory device - Google Patents

Abstract

A repair circuit of a semiconductor memory device is provided to reduce the area of a semiconductor chip by reducing an address line, by sharing a decoded address outputted from an address decoder in a fuse box. An address input circuit(110) outputs an address. A row address decoder(120) decodes an address. A sub word line driver(150) repairs a defective main word line among a number of main word lines connected to a main word line driver(140) according to the output of the row address decoder. A fuse box(130) generates a repair control signal to prevent the output of the row address decoder provided to the defective main word line according to the output of the row address decoder.

Description

Repair circuit of semiconductor memory device

1 is a schematic block diagram of a semiconductor memory device using a conventional address method.

2 is a schematic block diagram of a semiconductor memory device using the address sharing scheme of the present invention.

3 is a block diagram schematically illustrating the fuse box of FIG. 2.

4 is a detailed block diagram of the address comparison circuit of FIG. 3.

FIG. 5 is a detailed circuit diagram of the enable fuse circuit of FIG. 3.

FIG. 6 is a detailed circuit diagram of the address comparison circuit of FIG. 4.

FIG. 7 is a detailed circuit diagram of the fuse output circuit of FIG. 3.

<Explanation of symbols for the main parts of the drawings>

310: enable fuse circuit 320: fuse output circuit

CPAD: Address comparison circuit CP1 to CP8: Address comparison circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly, to a repair circuit of a semiconductor memory device.

As the DRAM process is increasingly integrated to sub-nano, the size of cell blocks has also decreased. However, when a dynamic fuse is used, when a repair circuit having the same repair efficiency is manufactured, the number of fuses is not reduced but only a cell block. Therefore, the chip size may increase due to the fuse. To solve this problem, a static fuse method has been used. Static fuses can use an undecoded address to reduce the number of fuses in approximately half. However, the static fuse method requires the use of an undecoded address, so a separate driver must be driven. When a separate driver is driven, an additional address line is needed as many as the number of addresses, thereby increasing the chip size due to unnecessary address lines.

1 is a schematic block diagram of a semiconductor memory device using a conventional address method. An address input circuit 11, a row address decoder 12, a fuse box 13, a main word line driver 14, and a sub word line driver 15 are included. The address input circuit 11 applies the undecoded addresses ADD <0: 7> to the row address decoder 12 and the fuse box 13. At this time, the area of the chip becomes large due to the area occupied by the undecoded address lines.

Accordingly, an object of the present invention is to provide a repair circuit of a semiconductor memory device which can reduce the area of a semiconductor chip by reducing the address line by sharing the decoded address output from the address decoder in the fuse box. .

In the repair circuit of the semiconductor device according to the present invention for achieving the above technical problem, a defect among a plurality of main word lines connected to an address input circuit for outputting an address, a row address decoder for decoding an address, and a main word line driver A sub word line driver for repairing the generated main word line according to the output of the row address decoder, and blocking an output of the row address decoder provided to the main word line where the defect occurs in accordance with the output of the row address decoder It includes a repair circuit of a semiconductor memory device including a fuse box for generating a repair control signal for.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

2 is a schematic block diagram of a semiconductor memory device using the address sharing scheme of the present invention. The semiconductor memory device includes an address input circuit 110, a row address decoder 120, a fuse box 130, a main word line driver 140, and a sub word line driver 150. The address input circuit 110 (address buffer and address latch) receives the input signal IPSG and outputs a plurality of addresses ADD <0: 7> which are not decoded. The row address decoder 120 receives and decodes the undecoded addresses ADD <0: 7> and outputs the decoded addresses ADD0 <0: 1> to ADD7 <0: 1>. In this case, the decoded addresses ADD0 <0: 1> to ADD7 <0: 1> are applied to the fuse box 130, the main word line driver 140, and the sub word line driver 150. The fuse box 130 generates a repair control signal HITB to block the output of the row address decoder provided to the defective main word line according to the output of the row address decoder 120. The decoded address provided to the defective main word line among the plurality of main word lines connected to the main word line driver 140 is blocked in response to the repair control signal HITB. The sub word line driver 150 repairs a main word line in which a defect occurs among a plurality of main word lines connected to the main word line driver 140 according to the output of the row address decoder 120.

3 is a block diagram schematically illustrating the fuse box of FIG. 2. The fuse box 130 includes an enable fuse circuit 310, an address comparison circuit unit CPAD, and a fuse output circuit 320. The enable fuse circuit 310 receives a fuse set signal FUSET and outputs a fuse enable signal FUEN and a fuse power signal FUPW. The address comparison circuit unit CPAD may include a plurality of comparison repair signals in response to the fuse power signal FUPW, the fuse set signal FUSET, and the decoded addresses ADD0 <0: 1> to ADD7 <0: 1>. Outputs HIT1 to HIT8). In addition, the address comparison circuit unit CPAD includes a plurality of address comparison circuits CP1 to CP8. The fuse output circuit 320 outputs the repair control signal HITB in response to the fuse enable signal FUEN and the plurality of comparison repair signals HIT1 to HIT8.

4 is a detailed block diagram of the address comparison circuit of FIG. 3. The address comparison circuit unit CPAD includes a plurality of address comparison circuits CP1 to CP8. In the present invention, eight address comparison circuits CP1 to CP8 are presented as an example. The number of address comparison circuits CP is required as many as the number of decoded addresses ADD0 <0: 1> to ADD7 <0: 1> applied. Each of the address comparison circuits CP1 to CP8 receives a fuse power supply FUPW and a fuse set signal FUSET, and receives a plurality of addresses ADD0 <0: 1> to ADD8 <0: 1>, respectively. The comparison repair signals HIT1 to HIT8 are output.

FIG. 5 is a detailed circuit diagram of the enable fuse circuit of FIG. 3. The enable fuse circuit 310 includes an input buffer 510, a latch circuit 520, and an output buffer 530. The input buffer 510 includes a PMOS transistor PT01, a fuse 512, and an NMOS transistor NT01. The PMOS transistor PT01 transfers the power supply voltage Vdd to the first node N1 in response to the fuseset signal FUSET. The NMOS transistor NT01 transfers a potential applied to the second node N2 through the fuse 512 to the ground voltage Vss. The latch circuit 520 latches the signal FI applied to the second node N2 and outputs a fuse enable signal FUEN through the output buffer 530.

FIG. 6 is a detailed circuit diagram of the address comparison circuit of FIG. 4. Since the configuration and operation of the plurality of address comparison circuits CP1 to CP8 are similar to each other, a description will be given with reference to FIG. The first address comparison circuit CP1 includes a power supply circuit 610, an input driver 620, an output selection circuit 630, a latch unit 640, and an output driver 650. The power supply circuit 610 includes a fuse 611 and an NMOS transistor NT03. The fuse 611 transfers or cuts off the fuse power FUPW to the node N4. The NMOS transistor NT03 resets the node N4 in response to the fuse set signal FUSET to output the internal signal VI in a logic low state. The input driver 620 includes a first transfer gate P1, a second transfer gate P2, and a NAND gate NG1 that operate according to the level of the internal signal VI. The first transfer gate P1 is turned on by the first logic level of the internal signal VI so that the address ADD0 is applied to the internal input address IAD. On the contrary, when the internal signal VI is in the second logic level state, the second transfer gate P2 is turned on and the address bar ADD0b is applied to the internal input address IAD. The NAND gate NG1 outputs the output transfer signal ADOUT in response to the internal signal VI and the internal input address IAD. The output selection circuit 630 includes an OR gate, a second selector 632, and a first selector 631. The OR gate OG outputs the internal switch signal NSG in response to the address ADD0 and the internal signal VI. The second selector 632 includes a plurality of PMOS transistors PT02 to PT04 and a plurality of NMOS transistors NT04 to NT06. The first PMOS transistor PT02 applies the power supply voltage Vdd to the first node G1 in response to the address bar ADD0b. The second PMOS transistor PT03 connects the first node G1 and the second node G2 in response to the internal switch signal bar NSGb. The third PMOS transistor PT04 connects the second node G2 and the third node G3 in response to the internal signal VI. The first NMOS transistor NT04 connects the third node G3 and the fourth node G4 in response to the internal signal bar VIb. The second NMOS transistor NT05 connects the fourth node G4 and the fifth node G5 in response to the internal switch signal NSG. The third NMOS transistor NT06 connects the fifth node G5 and the ground voltage Vss in response to the address ADD0. The first selector 631 includes a third transfer gate P3 and inverters IV6 and IV7. The third transfer gate P3 is turned on or off in response to the internal switch signal NSG to transfer the internal signal bar VIb to the latch unit 640. The latch unit 640 latches the output signal of the first selector 631 or the output signal of the second selector 632 and outputs an output control signal OCS. The output driver 650 includes a fourth transfer gate P4, a fifth transfer gate P5, and an inverter IV12. The fourth transfer gate P4 and the fifth transfer gate P5 operate in response to the output control signal OCS or the signal latched by the latch unit 640 to transfer the output transfer signal ADOUT to the node N11. To output the first repair signal HIT1.

The operation of the address comparison circuit CP1 will be described in detail according to the fuse 611 state and the address ADD0 level as follows.

(a) when fuse 611 is blown and address ADD0 is logic high;

Since the fuse 611 of the power supply circuit 610 is cut off, when the fuse set signal FUSET is enabled to the NMOS transistor NT03, the potential of the fourth node N4 is in a logic low state. The internal signal VI, which is in a logic low state, is then applied to the input driver 620 and the output selection circuit 630, respectively. The first transfer gate P1 of the input driver 620 is turned on by the internal signal VI to transfer the address ADD0 to the fifth node N5. The first NAND gate NG1 outputs an output transfer signal ADOUT in a logic high state in response to an internal input address IAD in a logic high state and an internal signal VI in a logic low state. The output selection circuit 630 outputs the first selection signal SEL1 or the second selection signal SEL2 for controlling the output level of the output transmission signal ADOUT. The OR gate OG of the output selection circuit 630 outputs the internal switch signal NSG in a logic low state in response to the internal signal VI and the address ADD0. The first selector 631 outputs the first select signal SEL1 in the logic high state in response to the internal signal VI in the logic low state and the internal switch signal NSG in the logic low state. In this case, the second selector 632 does not generate the second select signal SEL2 since the transistors PT03 and NT05 are turned off in response to the internal switch signal NSG. The latch unit 640 latches the first selection signal SEL1 in a logic high state, and the fifth transfer gate P5 of the output driver 650 is turned on in response to the output control signal OCS. Therefore, the output driver 650 outputs the first repair signal HIT1 in a logic low state.

(b) when fuse 611 is blown and address ADD0 is logic low;

Since the fuse 611 of the power supply circuit 610 is cut off, when the fuse set signal FUSET is enabled to the NMOS transistor NT03, the potential of the fourth node N4 is in a logic low state. The internal signal VI, which is in a logic low state, is then applied to the input driver 620 and the output selection circuit 630, respectively. The first transfer gate P1 of the input driver 620 is turned on by the internal signal VI to transfer the address ADD0 to the fifth node N5. The first NAND gate NG1 outputs an output transfer signal ADOUT in a logic high state in response to an internal input address IAD in a logic low state and an internal signal VI in a logic low state. The OR gate OG of the output selection circuit 630 outputs the internal switch signal NSG in a logic high state in response to the internal signal VI and the address ADD0. The third transfer gate P3 of the first selector 631 is turned off in response to the internal switch signal NSG in the logic high state so as not to generate the first select signal SEL1. The second PMOS transistor PT02 of the second selector 632 is turned off in response to the address bar ADD0b. The fourth to sixth NMOS transistors NT04 to NT06 are all turned on in response to the internal switch signal NSG, the internal signal VI, and the address ADD0 to receive the second selection signal SEL2 in a logic low state. Output The latch unit 640 latches the second selection signal SEL2 in a logic low state, and the fourth transfer gate P4 of the output driver 50 is turned on in response to the output control signal OCS. Therefore, the output driver 650 outputs the first repair signal HIT1 in a logic high state.

(c) when fuse 611 is connected and address ADD0 is logic high;

Since the fuse 611 of the power supply circuit 610 is connected, the potential of the fourth node N4 becomes a logic high state. The internal signal VI, which is in a logic high state, is then applied to the input driver 620 and the output selection circuit 630, respectively. The second transfer gate P2 of the input driver 620 is turned on by the internal signal VI to transfer the address bar ADD0 to the fifth node N5. The first NAND gate NG1 outputs an output transfer signal ADOUT in a logic high state in response to an internal input address IAD in a logic low state and an internal signal VI in a logic high state. The OR gate OG of the output selection circuit 630 outputs the internal switch signal NSG in a logic low state in response to the internal signal VI and the address ADD0. The third transfer gate P3 of the first selector 631 is turned on in response to the internal switch signal NSG in the logic low state to output the first select signal SEL1 in the logic low state. Since the second PMOS transistor PT02 of the second selector 632 is turned off in response to the internal switch signal NSG, the internal signal VI, and the address ADD0, the second select signal SEL2 is not generated. Do not. The latch unit 640 latches the first selection signal SEL1 in a logic low state, and the fourth transfer gate P4 of the output driver 650 is turned on in response to the output control signal OCS. Therefore, the output driver 650 outputs the first repair signal HIT1 in a logic high state.

(d) when fuse 611 is connected and address ADD0 is logic low;

Since the fuse 611 of the power supply circuit 610 is connected, the potential of the fourth node N4 becomes a logic high state. The internal signal VI, which is in a logic high state, is then applied to the input driver 620 and the output selection circuit 630, respectively. The second transfer gate P2 of the input driver 620 is turned on by the internal signal VI to transfer the address bar ADD0 to the fifth node N5. The first NAND gate NG1 outputs an output transfer signal ADOUT in a logic low state in response to an internal input address IAD in a logic high state and an internal signal VI in a logic high state. The OR gate OG of the output selection circuit 630 outputs the internal switch signal NSG in a logic low state in response to the internal signal VI and the address ADD0. The third transfer gate P3 of the first selector 631 is turned on in response to the internal switch signal NSG in the logic low state to output the first select signal SEL1 in the logic low state. The second to fourth PMOS transistors PT02 to PT04 and the fourth to fourth NMOS transistors NT04 to NT05 of the second selector 632 have an internal switch signal NSG, an internal signal VI, and an address. Since it is turned off in response to the bar ADD0b, the second selection signal SEL2 is not generated. The latch unit 640 latches the first selection signal SEL1 in a logic low state, and the fourth transfer gate P4 of the output driver 650 is turned on in response to the output control signal OCS. Therefore, the output driver 650 outputs the first repair signal HIT1 in a logic low state.

FIG. 7 is a detailed circuit diagram of the fuse output circuit of FIG. 3. Referring to FIG. 7, a logic controller 710 and a logic output unit 720 are included. The logic controller 710 includes a plurality of NAND gates NA1 to NA3. The first NAND gate NA1 outputs the first logic signal LS1 in response to the first to third repair signals HIT1 to HIT3. The second NAND gate NA2 outputs the second logic signal LS2 in response to the fourth to sixth repair signals HIT4 to HIT6. The third NAND gate NA3 outputs the third logic signal LS3 in response to the seventh to eighth repair signals HIT7 to HIT8 and the fuse enable signal FUEN. The logic output unit 720 outputs the repair control signal HITB in response to the first to third logic signals LS1 to LS3. Accordingly, when the fuse output circuit 320 receives the logic high state repair signals HIT1 to HIT8 from the address comparison circuit CP, the fuse output circuit 320 outputs the repair control signal HITB in the logic low state, and thus the main word line. The redundancy word line is selected by the driver 140 and the sub word line driver 150.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the repair circuit of the semiconductor memory device according to the present invention reduces the area of the semiconductor chip by reducing the address line by sharing the decoded address output from the address decoder in the fuse box. Can be reduced.

Claims (9)

An address input circuit for outputting an address; A row address decoder for decoding an address; A sub word line driver for repairing a main word line having a defect among a plurality of main word lines connected to a main word line driver according to an output of the row address decoder; And And a fuse box configured to generate a repair control signal for blocking an output of the row address decoder provided to the defective main word line according to the output of the row address decoder. According to claim 1, wherein the fuse box. An enable fuse circuit configured to generate a fuse enable signal and a fuse power signal in response to the fuse set signal; An address comparison circuit unit generating repair signals in response to the fuse set signal, the fuse power signal, and the decoded address; And And a fuse output circuit configured to output a repair control signal in response to the fuse enable signal and the repair signals. The method of claim 2, wherein the address comparison circuit unit, Including as many address comparison circuits as the number of addresses, Each of the address comparison circuits receives the fuse power source and the fuse set signal in common, and outputs a first repair signal in response to the respective addresses. The method of claim 3, wherein each of the address comparison circuits, A power supply circuit receiving the fuse power signal and outputting an internal signal in response to the fuse set signal and the fuse connection state; An input driver receiving an address and an address bar in response to the internal signal and outputting an output transmission signal; An output selection circuit outputting a first selection signal or a second selection signal in response to the address and the internal signal; A latch unit for latching an output first selection signal or second selection signal; And an output driver configured to receive an output transmission signal in response to the first selection signal or the second selection signal and to determine an output level to output a repair signal. The method of claim 4, wherein the power supply circuit, A fuse for transmitting or disconnecting the power supply voltage to a node; And an NMOS transistor operating in response to the fuseset signal and resetting the node to generate an internal signal. The method of claim 4, wherein the input driver, A first switching element turned on when the internal signal is in a logic low state to transfer the address to a node; A second switching element which is turned on when the internal signal is in a logic high state and transfers the address bar to the node; And And a NAND gate configured to generate an output transfer signal in response to the address or address bar applied to the node and the internal signal. The method of claim 4, wherein the output selection circuit, A NAND gate outputting an internal switch signal in response to the address and the internal signal; A first selector configured to output a first select signal in response to the internal switch signal and the internal signal; And And a second selector configured to operate the PMOS transistors and the NMOS transistors in response to the address, the internal switch signal, the internal signal, and the address bar to output a second select signal. The method of claim 4, wherein the latch unit, Receiving the first selection signal or the second selection signal, A repair circuit of a semiconductor memory device that outputs an applied signal and a latched signal. The method of claim 4, wherein the output driver, A first switching element turned on when the signal output from the latch unit is logic high to output the output transfer signal as the repair signal; And a second switching element which is turned on when the signal output from the latch unit is logic low and outputs the output transfer signal inverted by the inverter as the repair signal.

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