KR100273219B1 - Repair circuit of semiconductor memory cell - Google Patents

Repair circuit of semiconductor memory cell Download PDF

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KR100273219B1
KR100273219B1 KR1019970034401A KR19970034401A KR100273219B1 KR 100273219 B1 KR100273219 B1 KR 100273219B1 KR 1019970034401 A KR1019970034401 A KR 1019970034401A KR 19970034401 A KR19970034401 A KR 19970034401A KR 100273219 B1 KR100273219 B1 KR 100273219B1
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South Korea
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defect
fuse
signal
fuses
defect repair
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KR1019970034401A
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Korean (ko)
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KR19990011334A (en
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김재운
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김영환
현대반도체주식회사
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/812—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a reduced amount of fuses
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G11C29/787—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using a fuse hierarchy

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Abstract

PURPOSE: A defect repair circuit is provided to be capable of reducing the number of used fuses, so reducing manufacturing costs. CONSTITUTION: A plurality of defect repair circuits(101-10n) are connected to fuses(FU31-FU3n) for applying or cutting off a ground potential, and output different signals according to whether the fuses(FU31-FU3n) are connected to the ground potential. Each of the defect repair circuits(101-10n) comprises a capacitor, a PMOS transistor and an inverter. A plurality of NOR gates(NOR1-NORn) have one input terminals connected to receive a defect repair signal(REP) and the other input terminals connected to output signals of corresponding defect repair circuits(101-10n).

Description

반도체메모리 셀의 결함구제회로{REPAIR CIRCUIT OF SEMICONDUCTOR MEMORY CELL}REPAIR CIRCUIT OF SEMICONDUCTOR MEMORY CELL

본 발명은 반도체메모리 셀의 결함구제회로에 관한 것으로, 특히 결함이 발생된 셀에 저장되는 데이터를 리던던시(redundancy) 셀로 인가할 때, 이를 제어하는 퓨즈(fuse)의 사용을 줄이기에 적당하도록 한 반도체메모리 셀의 결함구제회로에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a defect repair circuit of a semiconductor memory cell, and more particularly to a semiconductor suitable for reducing the use of a fuse controlling the data stored in the cell where the defect occurs as a redundancy cell. The present invention relates to a defect repair circuit of a memory cell.

일반적으로, 반도체메모리는 다수의 셀을 제작하여 그 셀에 데이터를 저장하며, 이러한 다수의 셀 중에 한 개 혹은 몇 개의 셀에 결함이 발생될 경우에 메모리전체를 사용하지 못하게 되는 것을 방지하기 위하여 리던던시 셀을 제작하여 결함이 발생된 셀과 대체한다. 결함구제(repair)란 상기한 바와같이 결함이 발생된 셀을 리던던시 셀로 대체하는 것을 의미하며, 종래 반도체메모리 셀의 결함구제회로를 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.In general, a semiconductor memory fabricates a plurality of cells and stores data therein, and redundancy to prevent the entire memory from being used when a defect occurs in one or a few of these cells. Fabricate the cell and replace it with the defective cell. The defect repair means to replace a cell in which a defect is generated as a redundancy cell as described above. The defect repair circuit of the conventional semiconductor memory cell will be described in detail with reference to the accompanying drawings.

도1은 종래 반도체메모리 셀의 결함구제회로도로서, 이에 도시한 바와같이 각기 병렬로 접속되어 입력단(IN)으로부터 입력되는 결함구제신호(REP)를 도통제어하여 각각의 출력단(OUT1∼OUTn)에 전달하는 퓨즈(FU11∼FU1n)와; 접지(VSS)의 전위를 도통제어하여 상기 각 출력단(OUT1∼OUTn)에 전달하는 퓨즈(FU21∼FU2n)로 구성된다. 이하, 상기와 같이 구성된 종래 기술의 동작을 도2를 참조하여 설명한다.FIG. 1 is a defect repair circuit diagram of a conventional semiconductor memory cell. As shown in FIG. 1, a defect repair signal REP inputted from an input terminal IN is connected to each other in parallel to conduct a control to transfer them to each output terminal OUT1 to OUTn. Fuses FU11 to FU1n; And a fuse FU21 to FU2n that conducts control of the potential of the ground VSS to the output terminals OUT1 to OUTn. Hereinafter, the operation of the prior art configured as described above will be described with reference to FIG.

도2는 종래 반도체메모리 셀의 결함구제회로에 있어서, 제2출력단(OUT2)을 선택하였을 때의 일 실시예시도로서, 이에 도시한 바와같이 사용자가 출력단(OUT2)을 선택하기 위해서는 퓨즈(FU11,FU13∼FU1n)을 차단함과 아울러 퓨즈(FU22)를 차단하여야 한다. 따라서, 입력단(IN)으로부터 입력되는 결함구제신호(REP)는 퓨즈(FU12)를 통해 출력단(OUT2)에 인가되며, 출력단(OUT1,OUT3∼OUTn)은 퓨즈(FU21,FU23∼FU2n)에 따른 접지전위(VSS)가 나타난다.FIG. 2 illustrates an exemplary embodiment when a second output terminal OUT2 is selected in a defect repair circuit of a conventional semiconductor memory cell. As shown in FIG. 2, in order to select an output terminal OUT2, a fuse FU11, In addition to blocking FU13 to FU1n, the fuse FU22 should be cut off. Therefore, the defect relief signal REP input from the input terminal IN is applied to the output terminal OUT2 through the fuse FU12, and the output terminals OUT1, OUT3 to OUTn are grounded according to the fuses FU21, FU23 to FU2n. The potential VSS appears.

그러나, 상기한 바와같이 동작되는 종래 반도체메모리 셀의 결함구제회로는 많은 수의 퓨즈를 사용함으로써, 제조비용이 상승하는 문제점과; 출력단의 갯수에 해당하는 많은 수의 퓨즈를 절단해야함으로써, 퓨즈절단을 위한 프로그램이 복잡해짐과 아울러 퓨즈절단에 따른 시간이 지체되는 문제점이 있었다.However, the defect repair circuit of the conventional semiconductor memory cell operated as described above has a problem that the manufacturing cost increases by using a large number of fuses; By cutting a large number of fuses corresponding to the number of output stages, the program for the fuse cutting is complicated and there is a problem that the time due to the fuse cutting is delayed.

본 발명은 상기한 바와같은 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 사용되는 퓨즈의 갯수를 줄일 수 있는 반도체메모리 셀의 결함구제회로를 제공하는데 있다.The present invention has been made to solve the above problems, and an object of the present invention is to provide a defect repair circuit of a semiconductor memory cell that can reduce the number of fuses used.

도1은 종래 반도체메모리셀의 결함구제회로도.1 is a defect relief circuit diagram of a conventional semiconductor memory cell.

도2는 도1에 있어서, 제2출력단을 선택하였을 때의 일 실시예시도.FIG. 2 is a diagram illustrating one embodiment when a second output terminal is selected in FIG. 1; FIG.

도3은 본 발명의 일 실시예시도.Figure 3 is an embodiment of the present invention.

도4는 도3에 있어서, 제2출력단을 선택하였을 때의 일 실시예시도.4 is a diagram illustrating one embodiment when a second output terminal is selected in FIG.

***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***

101∼10n:결함구제선택부 FU31∼FU3n:퓨즈101 to 10n: defect remedy selection unit FU31 to FU3n: fuse

NOR1∼NORn:노아게이트 INV1∼INVn:인버터NOR1-NORn: Noah gate INV1-INVn: Inverter

C1∼Cn:커패시터 N1∼Nn:노드C1-Cn: Capacitors N1-Nn: Nodes

PM1∼PMn:피모스트랜지스터 OUT1∼OUTn:출력단PM1 to PMn: PMOS transistor OUT1 to OUTn: Output terminal

IN:입력단IN: input terminal

상기한 바와같은 본 발명의 목적은 접지의 전위를 인가 혹은 차단하는 다수개 퓨즈에 각각 접속되어 그 퓨즈의 접지접속 여부에 따라 상이한 신호를 출력하는 다수의 결함구제선택부와; 상기 각 퓨즈의 접지 접속여부에 따른 각 결함구제선택부로부터 출력되는 상이한 신호에 의해 입력단으로부터 입력되는 결함구제신호의 입력상태에 상관없이 일정한 신호를 각 출력단으로 출력하거나 또는 결함구제신호의 입력상태에 따른 신호를 각 출력단으로 출력하는 다수의 논리게이트로 구성함으로써 달성되는 것으로, 이와같은 본 발명에 의한 반도체메모리 셀의 결함구제회로를 첨부한 도면을 참조하여 설명하면 다음과 같다.As described above, an object of the present invention includes: a plurality of defect relief selection units connected to a plurality of fuses for applying or blocking a potential of ground to output a different signal depending on whether the fuse is connected to a ground; Regardless of the input state of the defect relief signal input from the input terminal by a different signal outputted from each defect relief selection unit according to whether or not the ground connection of each fuse is performed, a constant signal is output to each output terminal or the input state of the defect relief signal is This is achieved by configuring a plurality of logic gates for outputting a signal according to the respective output stages. A defect relief circuit of a semiconductor memory cell according to the present invention will be described with reference to the accompanying drawings.

도3은 본 발명에 의한 반도체메모리 셀의 결함구제회로도로서, 이에 도시한 바와같이 접지(VSS)의 전위를 인가 혹은 차단하는 퓨즈(FU31∼FU3n)에 접속되어 그 퓨즈(FU31∼FU3n)의 접지(VSS)접속 여부에 따라 상이한 신호를 출력하는 결함구제선택부(101∼10n)와; 입력단(IN)으로부터 입력되는 결함구제신호(REP)를 일측에 입력받고, 상기 결함구제선택부(101∼10n)의 출력을 타측에 입력받아 노아조합하여 출력단(OUT1∼OUTn)으로 각각 출력하는 노아게이트(NOR1∼NORn)로 구성되며, 상기 결함구제선택부(101∼10n)는 퓨즈(FU31∼FU3n)를 통한 접지(VSS)의 전위와, 커패시터(C1∼Cn)를 통한 전원전압(VCC)과, 피모스트랜지스터(PM1∼PMn)의 소스로부터 드레인을 통한 전원전압(VCC)을 각 노드(N1∼Nn)에 접속하고, 이 노드(N1∼Nn)의 전압을 반전하여 상기 피모스트랜지스터(PM1∼PMn)의 게이트에 인가함과 아울러 상기 노아게이트(NOR1∼NORn)의 타측에 인가하는 인버터(INV1∼INVn)로 구성된다. 이하, 상기한 바와같이 구성된 본 발명의 동작을 도4를 참조하여 설명한다.Fig. 3 is a circuit diagram of a defect repair circuit of a semiconductor memory cell according to the present invention, which is connected to the fuses FU31 to FU3n for applying or blocking the potential of the ground VSS as shown in FIG. (VSS) defect recovery selecting sections 101 to 10n for outputting a different signal depending on whether or not a connection is made; Noah which receives the defect relief signal REP input from the input terminal IN on one side, receives the output of the defect relief selection units 101 to 10n on the other side, and combines the outputs to output terminals OUT1 to OUTn. The defect relief selectors 101 to 10n each have a potential of the ground VSS through the fuses FU31 to FU3n and a power supply voltage VCC through the capacitors C1 to Cn. And the power supply voltage VCC from the source of the PMOS transistors PM1 to PMn to the drains of the nodes N1 to Nn by inverting the voltages of the nodes N1 to Nn. The inverters INV1 to INVn are applied to the gates of PM1 to PMn and to the other side of the NOA gates NOR1 to NORn. Hereinafter, the operation of the present invention configured as described above will be described with reference to FIG.

도4는 본 발명에 의한 반도체메모리 셀의 결함구제회로에 있어서, 제2출력단(OUT2)을 선택하였을 때의 일 실시예시도로서, 이에 도시한 바와같이 사용자가 출력단(OUT2)을 선택하기 위해서는 퓨즈(FU32)을 차단해야 한다. 따라서, 결함구제선택부(101,103∼10n)의 노드(N1,N3∼Nn)에는 퓨즈(FU31,FU33∼FU3n)를 통한 접지(VSS)의 전위가 나타나고, 이는 인버터(INV1,INV3∼INVn)을 통해 반전되어 고전위로 피모스트랜지스터(PM1,PM3∼PMn)의 게이트에 인가됨과 아울러 노아게이트(NOR1,NOR3∼NORn)의 타측에 입력되므로, 피모스트랜지스터(PM1,PM3∼PMn)는 턴오프되고, 노아게이트(NOR1,NOR3∼NORn)는 일측의 입력에 상관없이 출력단(OUT1,OUT3∼OUTn)으로 저전위를 출력한다. 이때, 결함구제선택부(102)의 노드(N2)에는 커패시터(C2)를 통한 전원전압(VCC)이 나타나고, 이는 인버터(INV2)를 통해 반전되어 저전위로 피모스트랜지스터(PM2)의 게이트에 인가됨과 아울러 노아게이트(NOR2)의 타측에 입력되므로, 피모스트랜지스터(PM2)는 턴온되어 노드(N2)에는 그 피모스트랜지스터(PM2)의 소스에 입력되는 전원전압(VCC)에 따른 고전위가 나타나고, 노아게이트(NOR2)는 입력단(IN)을 통해 입력되는 결함구제신호(REP)를 반전하여 출력단(OUT2)으로 출력한다. 이때, 상기 노드(N2)에 나타나는 피모스트랜지스터(PM2)의 소스에 입력되는 전원전압(VCC)에 따른 고전위는 상기 커패시터(C2)를 통해 인버터(INV2)로 입력되는 전원전압(VCC)을 안정시킨다.FIG. 4 is a diagram illustrating an exemplary embodiment when the second output terminal OUT2 is selected in the defect repair circuit of the semiconductor memory cell according to the present invention. As shown in FIG. (FU32) must be blocked. Therefore, the potentials of the ground VSS through the fuses FU31, FU33 to FU3n appear at the nodes N1, N3 to Nn of the defect relief selection units 101, 103 to 10n, which are used to drive the inverters INV1, INV3 to INVn. It is inverted through and applied to the gates of the PMOS transistors PM1 and PM3 to PMn at high potential and is input to the other side of the NOA gates NOR1 and NOR3 to NORn, so the PMOS transistors PM1 and PM3 to PMn are turned off. The NOA gates NOR1 and NOR3 to NORn output low potentials to the output terminals OUT1 and OUT3 to OUTn regardless of the input on one side. At this time, the power supply voltage VCC through the capacitor C2 appears at the node N2 of the defect relief selector 102, which is inverted through the inverter INV2 and applied to the gate of the PMOS transistor PM2 at a low potential. In addition, since it is input to the other side of the NOA gate NOR2, the PMOS transistor PM2 is turned on so that the high potential according to the power supply voltage VCC input to the source of the PMOS transistor PM2 appears at the node N2. The NOR gate NOR2 inverts the defect relief signal REP input through the input terminal IN and outputs the inverted defect output signal to the output terminal OUT2. In this case, the high potential according to the power supply voltage VCC input to the source of the PMOS transistor PM2 appearing at the node N2 is a power supply voltage VCC input to the inverter INV2 through the capacitor C2. Stabilize.

상기한 바와같이 동작되는 본 발명에 의한 반도체메모리 셀의 결함구제회로는 사용되는 퓨즈의 수가 반으로 감소함으로써, 제조비용이 절감하는 효과와; 하나의 퓨즈를 절단하여 원하는 출력을 얻음으로써, 퓨즈절단을 위한 프로그램을 단순화할 수 있는 효과와 아울러 퓨즈절단에 따른 소요시간을 줄일 수 있는 효과가 있다.The defect relief circuit of the semiconductor memory cell of the present invention operated as described above has the effect of reducing the manufacturing cost by reducing the number of fuses used by half; By cutting the fuse to obtain the desired output, the program for the fuse cutting can be simplified and the time required for the fuse cutting can be reduced.

Claims (2)

접지의 전위를 인가 혹은 차단하는 다수개 퓨즈에 각각 접속되어 그 퓨즈의 접지접속 여부에 따라 상이한 신호를 출력하는 다수의 결함구제선택부와; 상기 각 퓨즈의 접지 접속여부에 따른 각 결함구제선택부로부터 출력되는 상이한 신호에 의해 입력단으로부터 입력되는 결함구제신호의 입력상태에 상관없이 일정한 신호를 각 출력단으로 출력하거나 또는 결함구제신호의 입력상태에 따른 신호를 각 출력단으로 출력하는 다수의 논리게이트로 구성되는 것을 특징으로 하는 반도체메모리 셀의 결함구제회로.A plurality of defect repair selection units each connected to a plurality of fuses for applying or blocking a potential of the ground and outputting a different signal depending on whether the fuse is connected to a ground; Regardless of the input state of the defect relief signal input from the input terminal by a different signal outputted from each defect relief selection unit according to whether or not the ground connection of each fuse is performed, a constant signal is output to each output terminal or the input state of the defect relief signal is And a plurality of logic gates for outputting a corresponding signal to each output terminal. 제 1항에 있어서, 상기 결함구제선택부는 퓨즈의 접속여부에 따른 접지전위, 커패시터를 통한 전원전압, 피모스트랜지스터의 소스로부터 드레인을 통한 전원전압을 하나의 노드에 공통접속하여, 그 노드의 전압을 반전하여 상기 피모스트랜지스터의 게이트에 인가함과 아울러 상기 논리게이트의 타측에 인가하는 인버터로 구성되는 것을 특징으로 하는 반도체메모리 셀의 결함구제회로.The node of claim 1, wherein the defect remedy selection unit commonly connects a ground potential according to whether a fuse is connected, a power supply voltage through a capacitor, and a power supply voltage through a drain from a source of a PMOS transistor to a node, thereby providing a voltage of the node. And an inverter applied to the gate of the PMOS transistor and applied to the other side of the logic gate.
KR1019970034401A 1997-07-23 1997-07-23 Repair circuit of semiconductor memory cell KR100273219B1 (en)

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