KR100271716B1 - Row redundant circuit - Google Patents

Abstract

PURPOSE: A row redundant circuit is provided to adopt an address comparator to reduce the number of transistors all the way to reduce the layout size as well as the number of decode lines. CONSTITUTION: The row redundant circuit includes the address comparator(10), a blocker(20) and a deliverer(30). The row redundant circuit includes a pre-charger, a power loss compensator and a driver. The pre-charger charges a row redundant fuse box during a stand-by mode priorly. The power loss compensator compensates for the loss power of a terminal of the pre-charger. The driver receives the output signal of the compensator and enables a normal row line and a repair row line with response to the voltage level of the received signal. The address comparator compares pre-decoded first and second address signals. The blocker detects failure occurrence with response to the output signal of the address comparator and blocks the voltage transfer to a row line corresponding to the failure address. The deliverer is turned on and off by the first address signal and delivers the output voltage level of the pre-charger which is delivered by way of the blocker to a ground node.

Description

Rho redundant circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low-redundant circuit of a semiconductor memory device, and more particularly, to a low-redundant circuit in which an address comparator is used to simplify an address decoding method and its output is used on the low-redundant side.

As shown in FIG. 1, a general fuse decoding circuit includes a PMOS transistor P1 for precharging a pre-node Pre by an initial precharge signal XDP #, and a potential of the prenode Pre. Latch device (PMOS transistor (P2), inverter (IV1)) that compensates for the lost power of the latch and the output signal of the inverter (IV1) is inverted to select the row or repair row line. A plurality of NMOSs connected in parallel between the driver device IV2 for outputting a signal and the pre-node Pre and the ground terminal, and to which an address decoding signal AXIJ <0: 3 is applied to each gate terminal, respectively. A redundant fuse box is formed of transistors N1 to N4, and a plurality of fuses f1 to f4 respectively connected between the free node Pre and the plurality of NMOS transistors N1 to N4.

Referring to the fuse blowing method using the conventional fuse decoding circuit configured as described above, first, the pre-node Pre is precharged to the high level H by the precharge signal XDP #, and the word line If no defect occurs, the pre-node Pre is discharged to the low level L by the address decoding signal AXIJ <0: 3. Therefore, the NRD signal is maintained at a low level so as to be normal. The word line is enabled.

By the way, when a defect occurs in the word line of the address (any one of AXij <0: 3> same as in the above example), the fuse corresponding to the address (the fuse in f1 to f4) is blown, and thus the free line is free. The node Pre maintains the high level, and thus the NRD signal maintains the high level, so that the spare word line is operated, so that the repair is performed for the corresponding word line where the defect has occurred.

In order to generate the address decoding signal AXij <0: 3>, the address decoder shown in FIG. 2 is mainly employed.

The address decoder shown in FIG. 2 has a predecoded signal AXi < 0: 1 > AXj = 0: 1 &gt; and a plurality of NAND gates L7 to L4 and the output terminals of the NAND gates L1 to L4. Inverters IV3 to IV6 connected to each other generate an address decoding signal AXij <0: 3>.

As such, when the address decoding signal AXij <0: 3> from the conventional address decoder is applied to the low redundant fuse array side of the fuse decoding circuit, in the case of the 64M C-Rambus DRAM, there is a low redundant fuse box for every 256K cell array. Since 32 units are repeated, four routing lines of the address decoding signals AXij <0: 3> drive the gates of these 32 fuse arrays.

In the case of the 64M C-Rambus DRAM, a 256-row subcell array is used, so the four fuses in FIG. 1 will increase to 76, and the number of decoding lines entering the fuse gate input will also increase to 16.

Accordingly, a problem arises in that a large amount of losses are caused in the parasitic RC, gate capacitance, and area occupied by each routing line.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a low-redundant circuit that can simplify the decoding and significantly reduce the layout area by employing an address comparator.

In order to achieve the above object, the low-redundant circuit according to the present invention comprises a precharge means for precharging the low redundant fuse box in the standby mode, and a loss power compensation means for compensating the loss power of the primary end of the precharge means; In the low-redundancy circuit of the semiconductor memory device having a driver means for receiving the output signal of the loss power compensation means to drive the normal low line and the repair low line selectively enabled according to the potential level,

Address comparison means for comparing the two address signals to determine whether the predecoded first and second address signals are identical;

Blocking means for determining whether or not a defect occurs by the output signal of the address comparison means to block the potential transfer to the low line corresponding to the defective address and switching control by the first address signal through the blocking means It characterized in that it comprises a transmission means for transmitting the output potential of the precharge means to be transmitted to the ground terminal.

1 is a circuit diagram illustrating an example of a general fuse decoding circuit.

FIG. 2 is a circuit diagram showing an example of an address decoder for generating the address decoded signal shown in FIG.

3 is a low-redundant circuit diagram according to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

10: address comparison means 20: blocking means

30: delivery means

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 7 is a low-redundant circuit diagram according to an exemplary embodiment of the present invention. The same reference numerals are used to refer to the same elements as those described in FIG. 1, and description thereof will be omitted.

The difference between FIG. 1 and FIG. 1 is that the address comparison means 10 which compares the pre-decoded first address signal AX0 <0: 1> and the second address signal A (AX1 <0: 1>) with each other. ), A blocking means (20) which is controlled by a signal from the address comparing means (10) to block the potential transfer of the defective address if a defective address is found, and a free signal transmitted through the blocking means (20). It is configured to further include a transmission means 30 for transmitting a signal from the pull end of the charging means (P1) to the ground terminal.

The address comparing means 10 is controlled by the pre-decoded second address signal AX1 <0: 1> and inverted by the inverter IV7. The pre-decoded first address signal AX1 <0: 1 NMOS transistor N5 serving as a first transfer element for transferring the potential of >) to the blocking means 20, and the pre-decoded second address signal AX0 <0: 1> inverted by inverter IV8. And an NMOS transistor N6 as a second transfer element which is controlled by the potential of and transfers the potential of the pre-decoded first address signal AX0 <0: 1> to the blocking means 20.

Then, the address comparison means 10 determines whether two address bits are the same, and if they are the same (for example, the values of AXi and AXj are 00 and 11), the values of AXi and AXj are 01 and 10. The determination is determined by the value of AXi, which is the least significant bit.

The blocking means 20 is controlled by a signal Addcom outputted from the address comparing means 10, and a PMOS transistor P3 and an NMOS connected to a fuse in a low redundant fuse box (i.e., fl to f4), respectively. A transistor N7 and another PMOS transistor P4 and an NMOS transistor N8, one ends of the PMOS transistor P3 and the NMOS transistor N7 are interconnected, and the other PMOS transistor P4 and the NMOS transistor N8 are interconnected. One end of N8 is interconnected.

The transfer means 30 is provided between the connection node and the ground terminal of the PMOS transistor P3 and the NMOS transistor N7, and the NMOS transistor whose switching is controlled by the address signal AX0 <0> ( N7 and another address signal AX0 <provided between a connection node and a ground terminal of the NMOS transistor P4 and NMOS transistor N8 and having a potential level opposite to that of the address signal AX0 <0>. 1>) is configured as NMOS transistor N10 whose switching is controlled.

Next, the operation of the low redundant circuit according to the embodiment of the present invention configured as described above is as follows.

First, when the first and second address signals AX0 <0: 1> and AX1 <0: 1> input to the address comparing means 10 are different from each other, for example, AX0 <1> becomes a high level and AX1 < When 1> is at the low level, the first transfer element N6 is turned off and the second transfer element N6 is turned on so that the source potential (high level) of the second transfer element N6 is turned on. Is applied to the blocking means 20 through the output node Addcom.

Accordingly, the PMOS transistors P3 and P4 are turned off, the NMOS transistors N7 and N8 are turned on, and the NMOS transistor N9 in the transmission means 30 connected in series with the NMOS transistor N7. Is turned off, and since the NMOS transistor N10 in the transmission means 30 connected with the NMOS transistor N8 is turned on, decoding is possible.

When the first and first address signals AX0 <0: 1> and AX1 <0: 1> input to the address comparing means 10 are the same, for example, AX0 <1> is high level and AX1. When <1> becomes a high level, since the first transfer element N5 is turned on and the second transfer element N6 is turned off, the source potential of the first transfer element N5 is reduced. (Low level) is applied to the blocking means 20 through the output node Addcom.

Accordingly, the PMOS transistors P3 and P4 are turned on, the NMOS transistors N7 and N8 are turned off, and the NMOS transistor N9 in the transmission means 30 connected in series with the PMOS transistor P3. ) Is turned off, and since the NMOS transistor N10 in the transmission means 30 connected in series with the PMOS transistor P4 is turned on, decoding becomes possible.

In this state, when a defect occurs in the word line of the corresponding decoded address, the fuse corresponding to the address (fuse among fl to f4) is blown, and thus the potential of the free node Pre is set to a high level state. As a result, the NRD signal remains at a high level to enable the spare word line.

Therefore, a repair operation is performed on the word line where the failure has occurred.

When this embodiment of the present invention is applied to the 64M C-Rambus DRAM, the total number of decoding lines will be greatly reduced to 12 since three lines are required, the Addcom line, the AXi <0>, and the AXi <1> lines. .

As described above, according to the low-redundant circuit according to the present invention, by employing an address comparison means to greatly reduce the number of transistors required for the design of the decoding stage, a large advantage in the layout area can be obtained. In addition, the number of decoding lines can be reduced by reducing the number of decoding lines.

In addition, the preferred embodiments of the present invention are disclosed for the purpose of illustration, and those skilled in the art will be able to make various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications, modifications, and the like in the scope of the claims It should be seen as belonging.

Claims (5)

Precharge means for precharging the low redundant fuse box in the standby mode, loss power compensation means for compensating the loss power of the output stage of the precharge means, and receiving the output signal of the loss power compensation means according to the potential level thereof. In a redundant circuit of a semiconductor memory device having a driver means for driving a normal low-order repair line and a repair low-line selectively enabled, the two address signals are determined to determine whether the pre-decoded first and second address signals are the same. A blocking means for judging whether or not a defect has occurred by an output signal of the address comparing means and the address comparison means for comparing, and for blocking potential transfer to a rouline corresponding to the defective address; and by the first address signal. The precar is controlled by switching, and is transmitted through the blocking means. In that it comprises a delivery means for delivering the output potential of the ground terminal means Lawrence redundant circuit according to claim. 2. The apparatus of claim 1, wherein the address comparing means comprises: a first transfer element controlled by the pre-decoded second address to transfer an inverted potential of the pre-decoded first address to the blocking means; And a second transfer element controlled by an inversion potential of two addresses to transfer the predecoded first address to the blocking means. 3. The low-redundant circuit of claim 2, wherein the first and second transfer elements comprise a MOS transistor. The low-redundancy circuit of claim 1, wherein the blocking means comprises a plurality of MOS transistors. 2. The low redundant circuit of claim 1, wherein the transfer means comprises a plurality of MOS transistors.

Images