KR20070102178A - Flash memory device and method of operating the same - Google Patents

Abstract

A flash memory device and a driving method thereof are provided to decrease over-program fail by grouping cell blocks of a NAND type flash memory device as blocks with high usage frequency and blocks with low usage frequency and then applying an ISPP(Incremental Step Pulse Program) start bias differently to the blocks. A number of memory cell blocks are grouped into a group(210) with high usage frequency and a group(220) with low usage frequency according to a block address. A high voltage generator(230) generates a program voltage during a program operation. An address comparator(250) compares the block address with a specific address and then outputs a control signal according to the comparison result. A high voltage controller(240) controls the program voltage generated from the high voltage generator according to the control signal. A row decoder(260) applies a voltage regulated through the high voltage controller to a selected cell of the selected block group.

Description

Flash memory device and method of driving the same {Flash memory device and method of operating the same}

1 is a schematic diagram illustrating a program method of a general NAND type flash memory device.

2 is a schematic diagram for explaining a method of erasing a general NAND type flash memory device.

3 is a graph illustrating program and erase threshold voltage changes due to cycling of a NAND type flash memory device.

4 is a graph showing a program threshold voltage distribution of a cell block in which an over program occurs due to cycling of a NAND type flash memory device.

5 is a block diagram of a NAND-type flash memory device according to an embodiment of the present invention.

<Explanation of symbols for main parts of the drawings>

210: first group block 220: second group block

230: high voltage generator 240: high voltage controller

250: address comparator 260: row decoder

The present invention relates to a flash memory device, and in particular, by applying different incremental step pulse program (ISPP) start biases of a high frequency block and a low frequency block, it is possible to reduce an over program fail of a block that is likely to cause cycling deterioration. A flash memory device and a driving method thereof.

NAND-type flash memory devices are used in portable electronic systems such as notebooks, PDAs, and cellular phones, as well as in computer BIOS, printers, and USB drivers. The range of use is expanding.

The NAND-type flash memory device includes a plurality of cell blocks. One cell block includes a cell string 101 and 102 and a cell string connected in series with a plurality of cells for storing data, as shown in FIG. And a drain select transistor 110 and a source select transistor 120 between the drain and cell strings 101 and 102 and the source, respectively. Here, the cell strings 101 and 102 are configured by the number of bit lines BL, and accordingly, the drain select transistor 110 and the source select transistor 120 are configured as much. In addition, a predetermined bias is applied to the cell gate through the word line WL, a predetermined bias is applied to the drain through the bit line BL, and a source through the common source line CSL for a predetermined operation of the cell. A predetermined bias is applied to. On the other hand, the cell of the NAND type flash memory device is formed with a gate in which a tunnel oxide film, a floating gate, a dielectric film, and a control gate are stacked in a predetermined region on a semiconductor substrate, and junctions are formed on both sides of the gate.

In order to program the selected cell M11 of the NAND-type flash memory device configured as described above, a program voltage of about 16 to 19 V is applied to the selected word line (ISP) by an incremental step pulse program (ISPP) method. A pass voltage of about 10V is applied to an unselected word line Pass WL, a ground voltage Vss is applied to a selected bit line, and a power supply voltage Vcc is applied to an unselected bit line. Is applied. At this time, the power supply voltage Vcc is applied to the drain select line DSL, the ground voltage Vss is applied to the source select line SSL, and the power supply voltage Vcc is applied to the common source line CSL. The ground voltage Vss is applied to the bulk. In this case, since the threshold voltages of the cells are distributed between about 1 to 2.5V, the cells of the entire string are turned on and the power supply voltage Vcc is applied to the drain select line DSL, so the drain select transistor is turned on. Thus, the voltage at the channel maintains the bit line voltage of 0V. Therefore, the cell to be programmed receives all the program voltages, thereby causing the program operation. In the erase operation, as shown in FIG. 2, an erase voltage of about 20 V is applied to the triple P well and 0 V is applied to all of the word lines of the selected block to remove electrons injected into the floating gate.

As described above, both the electrical programming and the erasing of the NAND type flash memory device are enabled by FN tunneling. That is, since the electrons are moved by the strong electric field through the thin tunnel oxide film and the threshold voltage is changed to perform the program and erase functions, deterioration of the tunnel oxide film due to this is inevitable. Therefore, if the program and erase are repeated under a constant voltage condition, the program and erase threshold voltages change according to the number of repetitions. That is, as the number of programs and erases increases, the threshold voltage increases.

The flow of electrons through the tunnel oxide film during the program or erase operation creates an electron trap in the tunnel oxide bulk, and traps any electrons or holes at the interface between the tunnel oxide film and the semiconductor substrate. Before the hole is trapped, it creates a neutral trap center that is in a neutral state. The reason why the threshold voltage changes due to the electrons trapped in the tunnel oxide bulk is because the FN current decreases and the flat band voltage rises. The reason why the flat band voltage rises is almost the same as if the electrons are trapped in the tunnel oxide film, and the electrons are occupied in the floating gate, so it can be thought of as a programmed cell. If there is a thickening energy wall that electrons have to cross.

On the other hand, the neutral trap center at the interface between the semiconductor substrate and the tunnel oxide film lowers the speed of electrons when current flows through the channel of the cell, thereby lowering the GM of the cell. However, when actually reading the state of the cell, the state of the cell is determined by how much current flows in the cell. Therefore, when the GM of the cell is lowered, the threshold voltage of the cell is increased. As a result, the program and erase threshold voltages of the cell after cycling gradually increase as shown in FIG. 3.

When the threshold voltage of a cell programmed by cycling gradually increases and approaches a voltage applied to an unselected word line (usually 4.5-5V) during a read operation as shown in FIG. 4, the cell current does not flow sufficiently. Even if a cell in an erased state is incorrectly recognized as a program state. This failure is called over program failing.

In order to fundamentally improve the over program fail due to the cycling threshold voltage transition, the quality of the tunnel oxide layer needs to be improved. However, this deterioration process is inevitable and thus there is a limit to the improvement.

An object of the present invention is to provide a flash memory device capable of reducing over program fail and a driving method thereof.

Another object of the present invention is to classify a cell block of a NAND type flash memory device into high-use blocks and low-use blocks, and to reduce over-program failing by applying an ISPP start bias differently. A memory device and a driving method thereof are provided.

A flash memory device according to an embodiment of the present invention may include a plurality of memory cell blocks grouped into a high frequency group and a low frequency group according to a block address; A high voltage generator for generating a program voltage during programming; An address comparator for comparing the block address with a specific address and outputting first and second control signals according to the result; A high voltage controller for adjusting a program voltage generated from the high voltage generator in accordance with the first and second control signals; And a row decoder for applying a voltage adjusted through the high voltage controller to a selected cell of the selected block group.

 The address comparator determines whether the block address is lower than the specific address.

In addition, the method of driving a flash memory device according to an embodiment of the present invention comprises the steps of: grouping a plurality of memory cell blocks into a high frequency group and a low frequency group according to the block address; Comparing the block address with a specific address and adjusting a program voltage according to the result; And applying the adjusted program voltage to a selected cell of the selected block group, wherein the program start voltage of the high frequency block is lower than that of the low frequency block.

The program voltage is applied in an ISPP manner.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

5 is a configuration diagram of a NAND-type flash memory device according to an embodiment of the present invention, in which NAND-type blocks are used so that different program biases are applied by grouping blocks with high use frequency and blocks with low use frequency according to a block address. It is a block diagram of a flash memory element.

Referring to FIG. 5, a plurality of blocks BLK0 to BLKn constituting a memory cell array are grouped into a plurality of groups, for example, first and second block groups 210 and 220 according to the order of block addresses. The high voltage generator 230 generates a high voltage Vpp to be applied to the cell during programming. The high voltage Vpp generated by the high voltage generator 230 is adjusted according to the block address by the high voltage controller 240 and applied to the row decoder 250, and applied to the selected memory cell through the row decoder 250. On the other hand, the address comparator 260 determines whether the block address is lower than a specific address, generates the first and second control signals EN1 and EN2, and applies the voltage to the high voltage controller 240. 250 may be applied to the selected cell of the selected block.

In general, since NAND type flash memory devices program sequentially according to the order of block addresses, a block having a low block address has a high possibility of threshold voltage transition and over program fail due to cycling. Therefore, if the program is executed by making the ISPP start bias of the high frequency block lower than the low frequency block, the possibility of over program failing can be reduced. That is, as shown in FIG. 6 (a), some blocks having a low block address perform an ISPP program with increasing voltage from 16V, and some blocks having a high block address are 16.5V as shown in FIG. 6 (b). You can start the ISPP program. At this time, the boundary k of the block address is set in consideration of the use environment of the actual user. For example, in the case of 1G memory used for MP3, 256 blocks corresponding to 1/4 blocks can be set as boundaries.

As described above, according to the present invention, ISPP is used to group high-frequency blocks and low-frequency blocks into a plurality of block groups according to a block address. By applying different starting biases, over-program fail due to cycling of frequently used blocks can be reduced, and blocks with relatively low use frequency and hard to deteriorate cycling can increase program speed. As a result, the ISPP start bias can be high for the remaining blocks except for some blocks having a low block address, thereby improving the program speed and improving the reliability of the device because the cycling failure of the cell is improved without the inherent quality of the tunnel oxide. Probe test yield is improved because over program failure is improved.

Claims (4)

A plurality of memory cell blocks grouped into high usage groups and low usage groups according to block addresses; A high voltage generator for generating a program voltage during programming; An address comparator for comparing the block address with a specific address and outputting a control signal according to the result; A high voltage controller for adjusting a program voltage generated from the high voltage generator according to the control signal; And And a row decoder for applying a regulated voltage through the high voltage controller to a selected cell of the selected block group. The flash memory device of claim 1, wherein the address comparator determines whether the block address is lower than the specific address. Grouping the plurality of memory cell blocks into groups of high use and groups of low use according to the block address; Comparing the block address with a specific address and adjusting a program voltage according to the result; And Applying the adjusted program voltage to selected cells of the selected block group, And executing a program by lowering a program start voltage of the block of high use frequency than that of the block of low use frequency. The method of claim 3, wherein the program voltage is applied in an ISPP scheme.

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