KR20090080588A - Non-volatile semiconductor memory device with dummy cells and method for adjusting threshold voltage of dummy cells - Google Patents

Abstract

A nonvolatile semiconductor memory device and a method for controlling a threshold voltage of dummy cells are provided to minimize a read error due to read disturbance by programming the dummy cells quickly. A memory cell array(1) has dummy cells inside a cell string. The dummy cells have different threshold voltage. A sense amplifier and latch(2) senses and stores the input output data of the memory cell transistors inside the memory cell array. A column decoder(3) selects the bit lines. A low decoder(5) selects the word lines. A high voltage generating circuit(8) generates the voltage higher than the operation power voltage. A control circuit(7) controls the operation of the nonvolatile semiconductor memory device. A dummy cell controller(101) is connected to the control circuit. The dummy cell controller controls the threshold voltage of the dummy cells inside the memory cell array.

Description

Non-volatile semiconductor memory device with dummy cells and method for adjusting threshold voltage of dummy cells}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to nonvolatile semiconductor memories, and more particularly to nonvolatile semiconductor memories that store data by injecting or releasing charges into floating gates.

In recent years, with the rapid development of information processing devices such as multimedia terminals, notebook computers, and the like, semiconductor memory devices employed as important components of the information processing devices have also become high-speed operation and large capacity.

In general, semiconductor memory devices are largely divided into volatile semiconductor memory devices and nonvolatile semiconductor memory devices. Volatile semiconductor memory devices may be further classified into dynamic random access memory and static random access memory. Such a volatile semiconductor memory device is fast in terms of read and write speed, but has a disadvantage in that contents stored in a memory cell are lost when the external power supply is cut off.

The nonvolatile semiconductor memory device may include a mask read only memory (MROM), a programmable read only memory (PROM), an erasable and programmable read only memory (EPROM), and an electrical device. And erasable programmable read only memory (EEPROM).

The nonvolatile semiconductor memory device of this kind is mainly used to store contents to be preserved regardless of the power supply since the contents can be permanently stored in the memory cell even when the external power supply is interrupted. However, in the case of the MROM, PROM, and EPROM, general users are not free to erase and write (or program) themselves through an electronic system. In other words, it is not easy to erase or reprogram the programmed contents on-board. On the other hand, in the case of the EEPROM, since the operation of electrically erasing and writing is possible by the system itself, the application to the system program storage device or the auxiliary memory device requiring continuous contents update is continuously expanding.

Many electronic devices controlled by modern computers or microprocessors further require the development of high density, electrically erasable and programmable EEPROMs. Moreover, data storage devices such as digital cameras are required to be compact in size, and in the case of a portable computer or notebook-sized battery-powered computer system, the use of a hard disk device having a rotating magnetic disk as a secondary memory device is relatively large. Designers of such systems are very interested in the development of high density, high performance EEPROMs that occupy smaller areas.

NAND-type flash EEPROMs with flash erase function, which have emerged with the advancement of EEPROM design and manufacturing technology, have a high degree of integration compared to conventional EEPROMs, which is very advantageous for application to large capacity auxiliary storage devices. The flash EEPROM is classified into a NAND type, a NOR type, or an AND type according to the type of a unit memory cell array configuration. It is understood that the NAND type has a higher degree of integration than the NOR or AND type. It is well known in the art.

1 is a block diagram of a conventional nonvolatile semiconductor memory device. The device blocks shown in FIG. 1 have been disclosed in Japanese Patent Laid-Open No. 2004-127346 published in Japan on April 22, 2004.

1, a memory cell array 1, a sense amplifier and latch 2 for sensing and storing input and output data of memory cell transistors, a column decoder 3 for selecting bit lines, an input and output buffer 4, a word line NAND type with a row decoder 5 for selecting them, an address register 6, a high voltage generating circuit 8 for generating a high voltage higher than the operating power supply voltage, and a control circuit 7 for controlling the operation of the memory device. The block connection configuration of the EEPROM is shown.

FIG. 2A is an equivalent circuit diagram illustrating a connection structure of the memory cells in the memory cell array 1 of FIG. 1. The memory cell array 1 has a plurality of cell strings (or NAND cell units), but for convenience, the memory cell array 1 may include a first cell string 1a connected to an even bit line BLe and an odd bit line BLo. Only the two cell string 1b is shown.

The first cell string 1a includes a string select transistor SST1 having a drain connected to a bit line BLe, a ground select transistor GST1 having a source connected to a common source line CSL, and the string selection. A plurality of memory cell transistors MC31a, MC30a, ..., MC0a having drain-source channels connected in series between the source of the transistor SST1 and the drain of the ground select transistor GST1. Similarly, the second cell string 1b includes a string select transistor SST2 having a drain connected to the bit line BLo, a ground select transistor GST2 having a source connected to the common source line CSL, And a plurality of memory cell transistors MC31b, MC30b, ..., MC0b having drain-source channels connected in series between the source of the string select transistor SST2 and the drain of the ground select transistor GST2. .

The signal applied to the string select line SSL is commonly applied to the gates of the string select transistors SST1 and SST2, and the signal applied to the ground select line GSL is applied to the ground select transistors GST1 and GST2. Commonly applied to the gate. The word lines WL0-WL31 are equally connected to the control gates of the memory cell transistors belonging to the same row. The bit lines BLe and BLo operatively connected to the sense amplifier and latch 2 of FIG. 1 are arranged to cross each other in a different layer from the word lines WL0-WL31, and the bit lines are the same layer. In parallel to each other.

Erase, write, and read operations during the operation of the NAND type EEPROM are generally performed as follows. Erase and program (or write) operations are accomplished by using known F-N tunneling currents. For example, during erasing, a very high potential is applied to the substrate 10 shown in FIG. 3 and a low potential is applied to the CG (control gate 20) of the memory cell transistor. In this case, a potential determined by the capacitance between CG and FG (floating gate) 18 and the coupling ratio between the FG and the capacitance between the substrate is applied to the FG 18. If the potential difference between the floating gate voltage Vfg applied to the FG and the substrate voltage Vsub applied to the substrate is greater than the potential difference that may cause F-N tunneling, electrons collected in the FG move from the FG to the substrate. When such an operation occurs, the threshold voltage Vt of the memory cell transistor including the CG, FG, the source 12, and the drain 14 is lowered. Even when the Vt is sufficiently low and 0 V is applied to the CG and the source, when the current flows when a moderately high voltage is applied to the drain, we say that it is "ERASE" and logically denoted as "1". .

On the other hand, during writing, 0 V is applied to the source 12 and the drain 14 and a very high voltage is applied to the CG 20. At this time, an inversion layer is formed in the channel region so that both the source and the drain have a potential of 0V. If the potential difference applied between Vfg and Vchannel (0 V), determined by the ratio of capacitances between CG and FG and between the FG and channel regions, is large enough to cause F-N tunneling, electrons move from the channel region to FG. In this case, Vt increases, and if the current is not flowing when a preset positive voltage is applied to CG, 0 V is applied to the source, and a proper voltage is applied to the drain, we call it "PROGRAM." "Is often indicated.

In a configuration of a memory cell array having a plurality of cell strings such as the first and second cell strings 1a and 1b, page units refer to memory cell transistors in which a control gate is commonly connected to the same word line. A plurality of pages including a plurality of memory cell transistors is called a cell block, and a unit of one cell block typically includes one or a plurality of cell strings per bit line. NAND flash memory has a page program mode for high speed programming. The page program operation consists of a data loading operation and a program operation. The data loading operation sequentially latches and stores byte sized data from the input / output terminals in the data registers. Data registers are provided to correspond to each bit line. A program operation is an operation of temporarily writing data stored in the data registers into memory transistors on a selected word line through bit lines.

The NAND type EEPROM as described above generally performs read (read), program (write) operations in units of pages, and erase operations in units of blocks. In practice, the electron movement between the FG and the channel of the memory cell transistor occurs only in the program and erase operations, and in the read operation, the data stored in the memory cell transistor is read as it is without harmless after the erase and program operations are completed. The action takes place.

In a read operation, a voltage (typically a read voltage) higher than the selection read voltage Vr applied to the CG of the selected memory cell transistor is applied to the unselected CG of the memory cell transistor. Then, current may or may not flow on the corresponding bit line according to the program state of the selected memory cell transistor. If a threshold voltage of a programmed memory cell is higher than a reference value under a predetermined voltage condition, the memory cell is read off-cell and a high level voltage is charged on a corresponding bit line. On the contrary, if the threshold voltage of the programmed memory cell is lower than the reference value, the memory cell is read on-cell and the corresponding bit line is discharged to a low level. This bit line state is finally read as "0" or "1" through the sense amplifier called the page buffer.

Memory cell transistors in the cell string are initially erased to have a threshold voltage of, for example, about −3V or less. Subsequently, if a high voltage is applied to the word line of the selected memory cell for a predetermined time to program the memory cell transistor, the selected memory cell is changed to a higher threshold voltage, while the threshold of memory cells not selected during programming. The voltages do not change.

FIG. 2B illustrates a bias voltage relationship applied to the equivalent circuit of FIG. 2A in the read operation mode. FIG. In the read operation mode, when the even bit line BLe is selected, for example, 0.7 V is applied as the precharge voltage to the selected even bit line BLe, and for example, to the unselected odd bit line BLO. 0V is applied as the voltage for noise shielding. In this case, when the memory cell transistor MC0a in the first cell string 1a is selected, the selection read voltage Vr is applied to the selected word line WL0 and the unselected word lines WL1-WL31 are selected. ), A read voltage Vread is applied to the string select line SSL and the ground select line GSL, and OV is applied to the common source line CSL.

By the voltage biasing of the above example, the data stored in the memory cell transistor MC0a in the selected first cell string 1a is sensed to achieve a read operation. More specifically, when the string select transistor SST1, the ground select transistor GST1, and the memory cell transistors MC01-MC31a are turned on according to a threshold voltage value of the memory cell transistor MC0a. The voltage of the selection bit line BLe is discharged to a level of 0V or substantially maintains the set voltage. If the threshold voltage of the selected memory cell transistor is lower than the reference value, a current path is formed from the selection bit line BLe to the common source line CSL to discharge the selection bit line BLe to a low level. Therefore, the sense amplifier connected to the selection bit line BLe senses the selected memory cell transistor as an on-cell (data 0 or 1). If electrons are injected into the floating gate of the selected memory cell and the threshold voltage is higher than the reference value, a current path from the selection bit line BLe to the common source line CSL is not formed and is free in the selection bit line BLe. The charged voltage remains almost at that level. In this case, the sense amplifier connected to the selection bit line BLe detects the selected memory cell as an off-cell (data 1 or 0).

In the above read operation mode, the read voltage Vread is also applied to the control gates of the memory cell transistors MC31b, MC30b, ..., MC1b in the second cell string 1b connected to the unselected bit line Blo. Since it is applied, the unselected memory cell transistors MC31b, MC30b, ..., MC1b: A are subjected to electrical stress. Lead disturb problems caused by electrical stress will be more apparent with reference to FIG. 3.

FIG. 3 is a diagram for describing voltage stresses respectively occurring in memory cells connected to selected bit lines and unselected bit lines in FIG. 2B. In FIG. 3, the memory cell transistor MCib shown on the left side of the drawing may be any of the unselected memory cell transistors MC31b, MC30b,..., MC1b: A in the second cell string 1b of FIG. 2B. Indicates one. Also, the memory cell transistor MCia shown on the right side of the drawing may represent any one of the unselected memory cell transistors MC31a, MC30a,..., MC1a connected to the selected bit line BLe of FIG. 2B. .

The threshold voltage of the memory cell transistor is about -3V, and a gate insulating film such as an interlayer dielectric film 19 such as ONO formed under the control gate 20 and a gate oxide film formed under the floating gate 18 ( Let the coupling ratio indicate the ratio of capacitors by 16) to about 0.5. When the thickness of the gate insulating layer 16 is about 80 kV and a read voltage Vread of about 6.5 V is applied to the control gate 20, the memory cell transistor MCib is applied to the memory cell transistor MCia. In comparison, since the drain-source channel voltage is as low as 0.7V, a relatively strong electric field is applied to the gate insulating layer, for example, the gate oxide layer 16. For example, as shown in the drawing, an electrical stress, or an electric field, applied to the gate oxide layer 16 of the memory cell transistor MCib is about 6 MV / cm, and the gate oxide layer 16 of the memory cell transistor MCia is The receiving electric field is about 5.1 MV / cm. As shown in FIG. 3, the memory cells that are most subjected to electrical stress in the conventional read operation mode are unselected memory cell transistors MCib connected to a bit line to which 0 V is applied in order to act as a noise shielding for adjacent bit lines. . On the other hand, the non-selected memory cells MCia connected to the selected bit line receive less read disturb since the channel voltage is maintained at 0.5V to 0.7V.

As described above, it can be seen that the unselected memory cell transistors connected to the unselected bit lines in the read operation mode are subject to relatively high electrical stress due to the low channel voltage. Such electrical stresses increase the probability of causing lead disturb in recent densified memory fabrication processes. When the gate oxide film is made thinner and the distance between the lower portion of the control gate and the active region becomes shorter, the above electrical stress may shift the threshold voltage value of the memory cell transistor little by little. Therefore, when the memory cell transistor whose threshold voltage value is changed in the read operation mode is selected, a read error may be caused by the read disturb.

Furthermore, the area where the read operation is mainly performed among the memory cell areas of the flash EEPROM may be an area containing a small number of code data such as ROM table information requiring high-speed access or indexing information about stored data of the main memory cell array. have. For memory cells belonging to such an area, a very serious situation is caused when a read disturbance occurs due to a read operation. When a read error occurs due to a read disturb that causes a change in the threshold voltage of the memory cells, data having a read error is difficult to be normally recovered even by logic such as an error correction code, thereby causing a total defect of the semiconductor memory device. can do.

Accordingly, one of the solutions for minimizing or reducing the read disturb problem in the nonvolatile semiconductor memory has been disclosed in Korean Patent Application No. 10-2006-127849 filed by the applicant of the present application. According to the prior art, a floating formation switching unit is provided in the memory cell array to maintain the channel voltage of the memory cells connected to the unselected bit line at a level higher than the operating power supply voltage.

The floating formation switching unit is provided for each cell string in the memory cell array, and includes a switching transistor as a dummy cell connected between a ground select transistor and a memory cell located farthest from a bit line among the memory cells. In order for the dummy cell provided in the cell string to serve as a floating formation switching unit, an operation of adjusting the threshold voltage of the dummy cell to a desired setting level is required.

As described above, in addition to employing a dummy cell to prevent read disturb, a small number of code data such as a dummy cell for storing information about a memory chip or indexing information about stored data of a memory cell array, etc. In the case of employing the dummy cell to store the data, the threshold voltage adjustment for the dummy cells may be performed differently from that of the normal memory cell.

In order to ensure the reliability and mass production of semiconductor memory devices, it is necessary to adjust the threshold voltages on such dummy cells efficiently in a shorter time.

Accordingly, an object of the present invention is to provide a nonvolatile semiconductor memory device capable of more efficiently controlling the threshold voltage of a dummy cell which performs a function different from that of a normal memory cell.

Another object of the present invention is to provide a nonvolatile semiconductor memory device capable of performing a program operation on dummy cells more quickly and efficiently.

Another object of the present invention is to provide a method for more efficiently and quickly programming dummy cells in a nonvolatile semiconductor memory device including dummy cells in a cell string to prevent or minimize read errors due to read disturb. .

It is still another object of the present invention to provide a method of manufacturing a plurality of semiconductor memory chips having at least one dummy cell in a cell string on a wafer, and then more efficiently die-sorting and repairing the semiconductor memory chips at the wafer level. have.

Another object of the present invention is to provide a method for more efficiently handling at least one or more dummy cells included in a cell string of a nonvolatile semiconductor memory device, and a nonvolatile semiconductor memory device accordingly.

It is still another object of the present invention to provide a floating forming switch in a NAND type nonvolatile semiconductor memory device in which an unselected memory cell transistors in an unselected cell string may maintain a boosted channel voltage and thus be more free from a read disturb problem during a read operation. The present invention provides a method for programming functional dummy cells in a shorter time.

According to an aspect of the present invention for achieving the above object of the present invention, after manufacturing a plurality of semiconductor memory chips having at least one dummy cell in a cell string on a wafer, and then at the wafer level A method of diessing and repairing comprises: a first step of adjusting a threshold voltage for the dummy cell in the cell string; And performing a second sorting and repair operation on the normal memory cells in the cell string.

Preferably, prior to performing the first step, the step of performing diesting and repair on the dummy cell may be optionally provided, and the first step may be performed by applying a special command different from the normal command. Can be.

According to another aspect of the present invention, a nonvolatile semiconductor memory device includes a memory cell array including two or more dummy cells having different threshold voltages in a cell string together with normal memory cells; After a plurality of semiconductor memory chips including the memory cell array are fabricated on a wafer, before diesting and redundancy is performed on the normal memory cells when the semiconductor memory chip is diced and repaired at the wafer level. And a dummy cell controller configured to adjust threshold voltages of the dummy cells in response to an external input command.

In an embodiment of the present disclosure, the dummy cell controller may further have a function of performing diesting and redundancy on the dummy cells after the threshold voltages of the dummy cells are adjusted.

According to another aspect of the present invention, a post program for a normal memory cell in a semiconductor memory device having a memory cell array having two or more dummy cells having different threshold voltages together with normal memory cells in a cell string Previously, the method of programming the dummy cells is:

When erasing the normal memory cells, erase is performed in a cell block unit including adjacent dummy cells located closer to the normal memory cells among the dummy memory cells, and then erase erase is performed on the normal memory cells. Performing a step;

Performing a program and executing program verification on all adjacent dummy cells in the memory cell array;

For the remaining dummy cells that do not belong to the adjacent dummy cells, a program verifier is first performed, and then a program is executed for the dummy cells requiring the program.

In the exemplary embodiment of the present invention, the remaining dummy cells are located closer to the ground select line in the cell string than the adjacent dummy cells, and upon erasing in the cell block unit, the normal dummy gates are disposed in the gates of the adjacent dummy cells. A voltage equal to the erase gate voltage applied to the gates of the memory cells is applied, and a floating voltage or a voltage higher than the erase gate voltage is applied to the gates of the remaining dummy cells.

In the embodiment of the present invention, during the erase verification, the ground voltage or the read voltage is applied to the gates of the adjacent dummy cells, and the read voltage is applied to the gates of the remaining dummy cells. Preferably, the step increase width of the incremental step pulse program used in the programming of the dummy cells is set higher than that of the normal memory cell, and the program for the dummy cells is performed by an external input command.

In an embodiment of the present invention, when there are two dummy cells in the cell string, the adjacent dummy cell is connected to the normal memory cell located farthest from the bit line, and the other dummy cell is connected to the ground select transistor. In addition, when there are three dummy cells in the cell string, the adjacent dummy cell is connected to the normal memory cell located farthest from the bit line, and the remaining dummy cells are connected to the ground select transistor and the string select transistor, respectively.

A nonvolatile semiconductor memory device according to another aspect of the present invention is:

A memory cell array including two or more dummy cells each having a different threshold voltage in a cell string;

When erasing the normal memory cells in the cell string, erase is performed in a cell block unit including adjacent dummy cells located closer to the normal memory cells among the dummy cells, and then erased for the normal memory cells. An erase control circuit for performing an erase verification;

Program and perform program verification on all adjacent dummy cells in the memory cell array, and perform dummy program execution on the remaining dummy cells that do not belong to the adjacent dummy cells, and then target dummy cells that require a program. A dummy cell control circuit for performing a program is provided.

In an embodiment of the present disclosure, the erasing control circuit may be applied to the normal memory cells to the gates of the adjacent dummy cells when the normal memory cells are erased to prevent the threshold voltages of the dummy cells from being changed. A voltage equal to the gate voltage is applied, and a voltage higher than the floating or erase gate voltage is applied to the gates of the remaining dummy cells. The erase control circuit applies a ground voltage or a read voltage to the gates of the adjacent dummy cells and applies the read voltages to the gates of the remaining dummy cells during the erase verification.

In an embodiment of the present invention, the dummy cell control circuit sets the step increase width of the increment step pulse program used in programming the dummy cells higher than that of the normal memory cell. In addition, the dummy cell control circuit performs a program on the dummy cells in response to a mode register set signal.

Preferably, the dummy cells requiring the program are cells having a threshold value lower than a set threshold voltage. After the program for the dummy cells is terminated, the post program for the normal memory cells is performed.

A nonvolatile semiconductor memory device according to an embodiment of the present invention is:

A plurality of memories each having a floating gate connected in series with each other in series with a first selection transistor having a drain connected to a bit line, a second selection transistor having a source connected to a common source line, and a source of the first selection transistor A third and fourth selection transistor having a channel connected in series with each other in series between a cell transistor and a source of a last memory cell transistor of the plurality of memory cell transistors and a drain of the second selection transistor; A memory cell array having a plurality of cell strings;

An erase control circuit for performing the erase block operation on the plurality of memory cell transistors after the erase of the plurality of memory cell transistors is performed together with the third select transistor when the erase is performed on the plurality of memory cell transistors. Wow;

Program and perform program verification on all third selection transistors in the memory cell array, and perform program verification on all fourth selection transistors in the memory cell array first, and then select a fourth selection transistor requiring programming. Dummy cell control circuit for performing a program for them.

According to the device method configuration of the present invention as described above, since the program operation for the dummy cells is performed more quickly and efficiently, the manufacturing cost of the nonvolatile semiconductor memory device is reduced and the program convenience is increased. In addition, the function of the dummy cells is guaranteed to improve the reliability of the operation of the nonvolatile semiconductor memory device.

Hereinafter, according to the present invention, a preferred embodiment of a nonvolatile semiconductor memory device having dummy cells and a threshold voltage adjusting method of dummy cells will be described with reference to the accompanying drawings.

Although many specific details are set forth in the following examples by way of example and in the accompanying drawings, it is noted that this has been described without the intent to assist those of ordinary skill in the art to provide a more thorough understanding of the present invention. shall. However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details. The functional circuits and operations of conventional nonvolatile semiconductor memory devices are not described in detail in order not to obscure the present invention.

Hereinafter, a description of the function and operation of the dummy cell as the floating forming switching unit for preventing read disturbance will be made with reference to FIGS. 4 to 9 in order to provide a more thorough understanding of the present invention. Subsequently, a threshold voltage adjusting technique according to the present invention will be described in detail with reference to FIGS. 10 to 17 to more efficiently perform threshold voltage regulation on dummy cells in a short time.

First, FIG. 4 shows a connection structure of a memory cell string having a floating forming switch for preventing read disturb. 5 is an equivalent circuit diagram illustrating an implementation example of FIG. 4, and FIG. 6 is a diagram illustrating a read operation bias voltage relationship applied to the equivalent circuit of FIG. 5. FIG. 7 is an equivalent circuit diagram illustrating still another exemplary embodiment of FIG. 4, and FIG. 8 is a diagram for describing voltage stresses occurring in an unselected memory cell according to FIG. 4. 9 is a simulation graph illustrating a channel voltage boosting effect for preventing read disturb according to FIG. 4.

Referring to FIG. 4, in order to increase the drain-source channel voltage of the non-selected memory cells in the unselected cell string to the operation principle of self-boosting, the floating forming switching units 110 and 120 are formed inside the cell strings 10a and 10b. Each is shown installed. In the read operation mode, a higher voltage Vcc is applied as the precharge voltage for self-boosting to the unselected bit line BLO. In addition, the switch SW2 of the floating formation switching unit 120 is turned off, so that the common source line CSL is electrically separated from the cell string 10b.

As a result, in FIG. 4, it can be seen that the internal connection configuration of the cell strings constituting the memory cell array is unique compared to FIG. 2A. That is, the floating forming switching units 110 and 120 are installed in the cell strings, and the floating forming switching units 120 belonging to the cell string 10b unselected in the read operation mode among the floating forming switching units 110 and 120. Serves to maintain the channel voltage of the memory cells connected to the unselected bit line BLo at a level higher than or equal to the operating power supply voltage.

As a result, the floating formation switching unit is present for each cell string in the memory cell array. The floating formation switching unit is switched on when belonging to the selected cell string, and switched off when belonging to the non-selected cell string. Therefore, when the odd bit line BLo is unselected, the operating power supply voltage Vcc is applied to the bit line BLo, and the floating formation switching unit 120 is switched off by the control voltage S1. Accordingly, the common source line CSL and the second cell string 10b are electrically isolated from each other. At this time, in the channels of the non-selected memory cell transistors MC31b, MC30b, ..., MC1b, as much as VCC-Vth (threshold voltage of SST2) as the channel voltage, as shown in the graph shown on the right side of FIG. It is precharged. When the read voltage Vread is applied to the control gates of the unselected memory cell transistors MC31b, MC30b,..., MC1b after the floating formation switching unit 120 is switched off, the memory cell The channel voltage is raised as shown in the graph by the self boosting operation of the transistors. Here, the voltage Vboosting increased by self-boosting depends on the coupling ratio of each of the memory cell transistors, and the voltage level is about 4V or more. Therefore, the electrical stress or electric field applied to the gate oxide film 16 of the non-selected memory cell transistors MC31b, MC30b, ..., MC1b becomes about 1.0 MV / cm or less as shown in FIG. As a result, the electrical stresses of the unselected memory cell transistors MC31b, MC30b, ..., MC1b are much weaker than the electrical stresses of the unselected memory cell transistors connected to the selected bit line. Minimized or prevented.

In FIG. 4, for convenience of description, it is assumed that the odd bit line BLO is unselected. However, when the even bit line BLe is not selected, the operating power supply voltage Vcc is applied to the even bit line BLe in the read operation mode. A voltage of 0.7 V is applied to the odd bit line BLe. In this case, the on / off operation of the switches SW1 and SW2 is reversed from the state shown in FIG. That is, the switch SW1 is turned off and the switch SW2 is turned on.

FIG. 5 is an equivalent circuit diagram of an example of implementation of FIG. 4. Referring to FIG. 5, the first cell string 20a constituting part of the memory cell array 1 of FIG. 1 has a common source and a first selection transistor SST1 having a drain connected to the bit line BLe. A plurality of memory cell transistors MC31a and MC30a each having a floating gate and a channel connected in series to a second select transistor GST1 connected to a source line CSL and a source of the first select transistor SST1. Between the source of the last memory cell transistor MC0a of the plurality of memory cell transistors MC31a, MC30a, ..., MC0a and the drain of the second selection transistor GST1 The channels are connected to each other in series and are composed of third and fourth select transistors DMC12 and DMC21 having different threshold voltage values.

Similarly, the second cell string 20b includes a first select transistor SST2 having a drain connected to the bit line BLo, and a second select transistor GST2 having a source connected to the common source line CSL. And a plurality of memory cell transistors MC31b, MC30b, ..., MC0b connected to the source of the first selection transistor SST2 in series with each other and each having a floating gate, and the plurality of memory cell transistors. Channels connected in series between the source of the last memory cell transistor MC0b and the drain of the second selection transistor GST2 among the fields MC31b, MC30b, ..., MC0b, each having a different threshold voltage value. And third and fourth select transistors DMC22 and DMC11.

The dummy cell transistors DMC11 and DMC12 are set to have a threshold voltage of about 0.6 V in the dummy cell part 100 constituting the floating formation switching unit, and the dummy cell transistors DMC21 and DMC22 are about It is set to have a threshold voltage of -2V. Accordingly, when the second cell string 20b is unselected, the control voltage Dummy2 is applied as the read voltage Vread, and the control voltage Dummy1 is applied as about 1V, the dummy cell transistor DMC22 Since the dummy cell transistor DMC11 is turned off, the common source line CSL is not electrically connected to the bit line BLo through the second cell string 20b. On the other hand, the dummy cell transistors DMC12 and DMC21 in the selected cell string 20a are all turned on to provide a condition for the read operation to the selected memory cell transistor to be normally performed.

Referring to FIG. 6 showing the read operation bias voltage relationship applied to the equivalent circuit of FIG. 5, it is seen that the channel voltages for the unselected memory cells connected to the unselected bit lines are increased by the self boosting effect.

In the dummy cell portion 100 of FIG. 5, the dummy cell transistors DMC11 and DMC12 are adjusted to have a threshold voltage of about 0.6V, and the dummy cell transistors DMC21 and DMC22 are about −2V. When adjusted to have a threshold voltage, the bias voltage relationship applied to each part of the circuit in the read operation mode can be as follows.

After the read command is applied, as shown in the graph to the right of FIG. 6, 0.7 V is applied to the selected bit line BLe at time point t1, and an operating power supply voltage of about 2.6 V is applied to the unselected bit line BLO. (Vcc) is applied. The operating power supply voltage Vcc is applied to the string select line SSL at time point t2. In the conventional case, a read voltage Vread was applied to the SSL. At the time point t2, the selection read voltage Vread is applied to the selected word line, for example, WL0, the control voltage Dummy2 is applied as the read voltage Vread, and the control voltage Dummy1 is applied as about 1V. Accordingly, the dummy cell transistor DMC22 is turned on, the dummy cell transistor DMC11 is turned off, and the second cell string 20b is electrically isolated from the bit line BLo. Meanwhile, all of the dummy cell transistors DMC12 and DMC21 in the selected cell string 20a are turned on so that the channel of the selected memory cell transistor MC0a is electrically connected between the bit line BLe and the common source line CSL. To be connected. As a result, the first cell string 20a has a discharge path and the second cell string 20b is in a floating state because the discharge path is blocked.

According to the bias condition as described above, after the time point t2, a voltage corresponding to Vcc-Vth (threshold voltage of SST2) is applied to each channel of the unselected memory cells of the unselected bit line BLO. It is precharged. In this state, when the read voltage Vread is applied to the unselected word lines WL1-WL31 and the ground select line GSL at the time point t3, the channel voltage rise due to the self-boosting operation appears.

As a result, since the channel voltages of the non-selected memory cells connected to the unselected bit lines are self-boost by the read voltage Vread, they appear as boosting voltages Vboost that increase by a boosting ratio at Vcc-Vth. The boosting ratio eventually depends mostly on the coupling ratio of the memory cell transistors, where the coupling ratio is the capacitance between CG and FG (called C2) and the capacitance between FG and bulk / substrate (called C1). Ratio, the coupling ratio (Cr) is represented as C2 / C1 + C2. In the embodiment of the present invention, the coupling ratio Cr is 0.5, and the memory cell transistors have a threshold voltage of about -3V in an erased state.

In the biasing voltage waveform of FIG. 6, the time points t1 and t2 are distinguished for convenience of explanation, and even when biasing is performed, the result of the operation is not affected.

As such, the unselected memory cell transistors connected to the unselected bit lines due to the channel voltages raised by self-boosting are significantly less electrically stressed than in the conventional case. Therefore, the read disturb is prevented or minimized so that the probability of causing a read error is low.

FIG. 7 is an equivalent circuit diagram illustrating still another embodiment of FIG. 4. Unlike FIG. 5, the dummy transistors DMC11, DMC12, DMC21, and DMC22 in the dummy transistor unit 102 may be selected from a string select transistor SST or a ground select transistor. The case shown by the transistor (GST) is shown. In other words, the dummy transistor section 102 is formed of a normal MOS transistor instead of a memory cell transistor having a floating gate. Similarly, the dummy cell transistors DMC11 and DMC12 are adjusted to have a threshold voltage of about 0.6V, and the dummy cell transistors DMC21 and DMC22 are adjusted to have a threshold voltage of about −2V.

Also in the case of FIG. 7, the bias voltage relationship applied to each circuit portion in the read operation mode is the same as that of FIG. As a result, instead of constructing the floating formation switching unit with the memory cell transistor, only the transistors such as string select transistors are different, and the channel voltages for the unselected memory cells connected to the unselected bit lines are increased by self-boosting. Is substantially the same.

FIG. 8 is a diagram for describing voltage stresses occurring in unselected memory cells connected to unselected bit lines according to FIG. 4. In comparison with the memory cell transistor MCib of FIG. 3, it can be seen that the channel voltage Vch between the source 12 and the drain 14 becomes about 4V or more due to the self-boosting effect. Compared with the conventional case, an electric field of about 6 MV / cm is applied to the gate oxide film 16 in the related art, whereas an electric field of about 1 MV / cm is applied to the embodiment of the present invention. In FIG. 8, when the arrow sign AR1 is compared at the boundary, such a difference in electric field strength is shown.

9 is a simulation graph illustrating a channel voltage boosting effect for preventing read disturb according to FIG. 4. In FIG. 9, the horizontal axis represents one cell string having 32 memory cell transistors in micron units, and the vertical axis represents a channel voltage of an unselected memory cell transistor connected to an unselected bit line. In order to provide a quicker understanding, comparing the graphs assigned with the graph code G10 and the graph code G6 solves the lead disturb problem by self-boosting and the conventional case where the lead disturb problem may be caused. The cases are distinct. As a result, the drain-source channel voltage shown in the graph symbol G10 is about 5V or more in the simulation due to the self-boosting effect, which is about 4V or more higher than in the related art. The graph symbol G8 represents the channel voltage precharged before the self-boosting operation, and the graph symbol G4 synthesizes the channel voltage according to the conventional initial operation, the operation after applying the power supply voltage, and the initial operation of the present embodiment. Is showing.

As such, since the unselected memory cell transistors in the unselected cell string in the read operation mode have a self-boosting operation, the channel voltage is raised as shown in the graph. Accordingly, the electrical stress or electric field applied to the gate oxide layer 16 of the non-selected memory cell transistors MC31b, MC30b, ..., MC1b becomes about 1.0 MV / cm or less as shown in FIG. Is minimized or prevented.

A nonvolatile memory device having a memory cell array configuration as shown in FIG. 5 or 7 as described above may include an erase circuit that performs an erase operation to return data retention characteristics of the memory cells to an initial state. It is provided in 7). The apparatus also has a program circuit in the control circuit 7 of FIG. 1 for storing data in the normal memory cells on which the erase operation has been performed.

As described above, by employing the dummy cell unit 100, read disturb for unselected memory cell transistors connected to the unselected bit line in the read operation mode is minimized or prevented. Therefore, the probability of causing a read error in the read operation of the memory cell is reduced.

Hereinafter, the threshold voltage adjusting method according to the present invention will be described with reference to FIGS. 10 to 17 to more efficiently perform the threshold voltage adjustment for the dummy cells in a short time.

10 is a schematic block diagram of a nonvolatile semiconductor memory device according to the present invention. Referring to FIG. 10, a memory cell array 1 having dummy cells in a cell string, a sense amplifier and latch 2 for detecting and storing input / output data of memory cell transistors in the memory cell array 1, and bit lines may be provided. A column decoder 3 for selection, an input / output buffer 4, a row decoder 5 for selecting word lines, an address register 6, a high voltage generating circuit 8 for generating a high voltage higher than the operating power supply voltage, A control circuit 7 for controlling the operation of the volatile semiconductor memory device and a dummy cell controller 101 connected to the control circuit 7 to adjust threshold voltages of the dummy cells in the memory cell array 1. The block connection configuration of the NAND type flash memory is shown.

In any cell string 20a of the memory cell array 1, as shown in FIG. 11, dummy cells having different threshold voltage values to prevent read disturb for normal memory cells MC0a to MC31a. (DMC12, DMC21) are provided. However, in other cases, the dummy cells DMC12 and DMC21 may be used for specific data storage or other purposes in addition to preventing read disturb.

After fabricating a plurality of semiconductor memory chips including the memory cell array on a wafer, when the semiconductor memory chip is diced and repaired at the wafer level, the dummy cell controller 101 is configured to provide the normal memory cells. Before the diesorting and redundancy are performed, threshold voltage adjustments are made to the dummy cells in response to an external input command.

In addition, the dummy cell controller 101 may additionally have a function of performing diesting and redundancy on the dummy cells before the threshold voltages of the dummy cells are adjusted.

FIG. 11 shows cell string structures having two or more dummy cells per cell string in the memory cell array of FIG. 10. First, an example of the connection structure of the cell strings shown on the left side of FIG. 11 is referred to as Case 1, and an example of the connection structure of the cell strings shown on the right side is referred to as Case 2. In case 1, two dummy cells are connected to one cell string, and in case 2, three dummy cells are connected to one cell string.

 In Case 1, the first cell string 20a and the second cell string 20b constituting part of the memory cell array 1 of FIG. 10 are identical to the cell string structure of FIG. 5.

Meanwhile, in case 2, the first cell string 21a and the second cell string 21b constituting a part of the memory cell array 1 of FIG. 10 may function as dummy cells in the case 1 connection configuration. The selection transistors DMC31 and DMC32 are further added.

That is, in case 2, the first cell string 21a includes a first select transistor SST1 having a drain connected to the bit line BLe, and a fifth connected to the source of the first select transistor SST1. Channels are connected in series to the select transistor DMC31, the second select transistor GST1 having a source connected to the common source line CSL, and the source of the fifth select transistor DMC31, and each of which has a floating gate. Among the plurality of memory cell transistors MC31a, MC30a,..., MC0a and the memory cell transistors furthest from the bit line BLe among the plurality of memory cell transistors MC31a, MC30a,..., MC0a. A channel is connected to each other in series between the source of MC0a and the drain of the second select transistor GST1 and includes third and fourth select transistors DMC12 and DMC21 having different threshold voltage values.

For example, in the dummy cell unit 100 constituting the floating formation switching unit, the dummy cell transistors DMC11 and DMC12 may be set to have a threshold voltage of about 0.6 V to 2 volts, and the dummy cell transistors ( DMC21 and DMC22 are set to have a threshold voltage of about -2V. Accordingly, when the second cell string 21b is unselected, the control voltage Dummy2 is applied as the read voltage Vread, and the control voltage Dummy1 is applied as about 1 V, the dummy cell transistor DMC22 Since the dummy cell transistor DMC11 is turned off, the common source line CSL is not electrically connected to the bit line BLo through the second cell string 21b. On the other hand, the dummy cell transistors DMC12 and DMC21 in the selected cell string 21a are all turned on to provide a condition for the read operation to the selected memory cell transistor to be normally performed.

On the other hand, the dummy cell unit 110 configured as the fifth select transistors DMC31 and DMC32 is employed for edge effects with respect to the word line WL [31].

FIG. 12 is a flowchart illustrating a sequence relationship between diesorting and redundancy for dummy cells and normal memory cells when the apparatus of FIG. 10 is wafer fab-out in accordance with an embodiment of the present invention.

Referring to FIG. 12, steps S120 to S123 are sequentially shown. In step S120 it is checked whether the wafer fab (fabrication) is out. The nonvolatile memory device of FIG. 10 having dummy cells in a cell string as in FIG. 11 is fabricated as one of a plurality of chips on a wafer. In one embodiment of the present invention, when the wafer fabs out, the dummy cells are processed before normal memory cells in an EDS process. As a result, after fabricating a plurality of semiconductor memory chips on the wafer, step S121 may be selectively performed when diesting and repairing the semiconductor memory chip at the wafer level. In step S121, diesting and repairing of the dummy cells in the cell string are primarily performed.

When step S121 is selectively completed, step S122 of adjusting the threshold voltage for the dummy cell is performed. When the execution of step S122 is completed, step S123 is performed to secondaryly perform die-sorting and repair on the normal memory cells in the cell string.

According to FIG. 12, when diesting and repairing the semiconductor memory chip at the wafer level, the threshold voltages for the dummy cells in response to an external input command before diesorting and redundancy for the normal memory cells are performed. Adjustment is made. Therefore, the threshold voltage adjustment for the dummy cells is made separately from the normal memory cells. The operation of FIG. 12 is controlled by the dummy cell controller 101 in response to the input command ICMD of FIG. 10. The input command ICMD is a signal generated by the control circuit 7 when a tester external to the device applies an external input command.

From now on, after the nonvolatile semiconductor memory device is shipped as a product, a technique of adjusting the threshold voltages of the dummy cells at the user level will be described as another embodiment of the present invention.

First, FIG. 13 illustrates an erase operation bias voltage relationship in the case of block erasing the memory cell of FIG. 11.

As shown in FIG. 13, in the block erase operation, a coupling issue EF due to the parasitic capacitance C3 may appear. The coupling issue is a problem of erase failure that may occur in the memory cell MC0a in the cell string of FIG. 11. In the case of the memory cell MC0a located farthest from the bit line BLe, since an insufficient erase operation occurs due to the coupling issue, it is difficult to fully adjust the threshold voltage at the time of erasing. It has a higher threshold voltage value than (MC1a). In order to solve such a problem of erase failure, the control voltage Dummy2 of the adjacent dummy cell DMC12 is applied as 0 volts in the embodiment of the present invention. The control voltage Dummy1 of the dummy cell DMC21 connected between the adjacent dummy cell DMC12 and the ground select transistor GST1 is applied in two cases in the embodiment of the present invention, that is, the control of the dummy cell DMC21. The voltage Dummy1 may be applied as 0 volts, or the dummy cell DMC21 may be maintained in a floating state .. The table shown in Fig. 13 shows the erase operation bias voltage relationship according to the above two cases. You can see that.

FIG. 14 is a flowchart illustrating a sequence of a block erase operation and a dummy cell program operation for dummy cells according to another embodiment of the present invention. FIG. 15 is a diagram illustrating variation of distribution of threshold voltages of cell transistors in the operation sequence of FIG. 14, and FIG. 16 is a diagram illustrating an operation bias voltage relationship applied to each other in accordance with the operation sequence of FIG. 14. In addition, FIG. 17 is a diagram illustrating a step increase width of an incremental step pulse program for a dummy cell and a normal cell in a program operation according to FIG. 14.

First, referring to FIG. 14, steps S140 to S149 are sequentially shown. The step S140 is a step of receiving an erase command, and the step S141 is a step of starting block erasing. Step S142 is a step of performing block erase including adjacent dummy cells. In step S142, erase bias voltages positioned at the right side of the table of FIG. 13 are applied to the cell string of FIG. 11. For example, the string select line SSL, the unselected word lines, the control voltage Dummy1 of the dummy cell DMC21, the ground select line GSL, and the bit line / common select line BL / CSL are floating. Biased in the state. The selected word line and the control voltage Dummy2 of the adjacent dummy cell DMC12 are biased as a ground voltage, for example, 0 volts. When the step S142 is completed, an erase verification operation (step S143) is performed. In the erase verification operation, it is checked whether the threshold voltages of the normal memory cells are set to the set threshold voltage value after erasing. Therefore, the erase verification operation of step S143 is performed on the normal memory cells in the cell string, and the control voltage Dummy2 of the adjacent dummy cell DMC12 is the same as the bias voltage shown in the erase verification section of FIG. 16. , From 0 volt to the read voltage Vread, and the control voltage Dummy1 of the remaining dummy cell DMC21 is applied as the read voltage Vread. In this case, an erase verification voltage is applied to the selected bit line, and zero volts is applied to the unselected bit line and the selected and unselected word lines. As shown in the erase verification section, the string select line and the ground select line are biased as read voltages, and the common select line is biased as 0 volts.

When the step S143 is completed, the normal memory cells and the dummy memory cells in the memory cell array have the state transition ST1 as shown in FIG. 15, and thus have a cell spread in the upper left to the upper right in FIG. 15. That is, when the normal memory cell is a multi-level cell (MLC), the normal memory cells have four distributions 16a, 16b, 16C, and 16d before erasing, and the dummy cells have two distributions 15a and 15b. Has In each part of FIG. 15, the horizontal axis indicates threshold voltages of cells, and the vertical axis indicates the number of cells. As described above, when block erasing and verification are performed in the state having the upper left side of FIG. 15, the state transition ST1 occurs as indicated by the arrow in FIG. 15, and the cell distribution changes as shown in the upper right side. In other words, the four distributions 16a, 16b, 16C, and 16d for the normal cells move along the arrow signs S10, S11, S12, and S13 and are integrated into one distribution 16e. That is, according to the erase operation, all normal memory cells have a threshold voltage value near -3 volts, for example. In this case, the adjacent dummy cells of the dummy cells move along the arrow S14 to belong to the distribution 15a, and all the dummy cells including the remaining dummy cells DMC21 and located at the same position as the remaining dummy cells DMC21. The cells remain in the distribution 15c.

Referring back to FIG. 14, when the step S143 is completed, steps (steps S144 and S145) of executing a program and executing a program verification for all adjacent dummy cells in the memory cell array are sequentially performed. In step S144 for programming all the adjacent dummy cells, biasing voltages as shown in the PGM Vth adjustment section in the threshold voltage adjustment section for dummy 2 are applied in FIG. 16. For example, the control voltage Dummy2 of the adjacent dummy cell DMC12 is applied as the program voltage Vpgm-1, and the control voltage Dummy1 of the remaining dummy cell DMC21 is applied as the pass voltage Vpass. In this case, 0 volts is applied to the selected bit line, a power supply voltage Vdd is applied to the unselected bit line and the string selection line, and a pass voltage Vpass is applied to the selected and unselected word lines, respectively. In addition, 0 volts is applied to the ground select line and about 1.5 volts is applied to the common select line.

Incremental step pulse program may be used in the program operation of the dummy cells, in which case the step increment width of the increment step pulse program for the dummy cells is the step increment of the increment step pulse program for the normal memory cell as shown in FIG. Greater than width That is, the level of the voltage that increases during programming of the dummy cells is relatively rough, as shown in FIG. 17, about 0.5 volts. On the other hand, the step increment of the normal memory cell is about 0.2 volts. In FIG. 17, arrow ST20 indicates the step increment of the incremental step pulse program for the dummy cell, and arrow ST10 indicates the step increment of the incremental step pulse program for the normal memory cell.

Returning to FIG. 14 again, in step S145 for performing program verification for all adjacent dummy cells, biasing voltages as shown in the verification section in the threshold voltage adjustment section for dummy 2 in FIG. 16 are applied.

When the execution up to step S145 is completed, the normal memory cells and the dummy memory cells in the memory cell array have a state transition ST2 as shown in FIG. You have a scatter. The remaining dummy cells among the dummy cells belonging to the distribution 15a move along the arrow symbol S16 to belong to the distribution 15c.

After the step S145 of FIG. 14, the program dummy process is first performed on the remaining dummy cells that do not belong to the adjacent dummy cells, and then the programs are performed on the dummy cells requiring the program (steps S146 and S147). do. In step S146, biasing voltages as shown in the dummy voltage verification section in the threshold voltage check and adjustment section for dummy 1 in FIG. 16 are applied. Then, in step S147, biasing voltages as shown in the dummy voltage program section in the threshold voltage check and adjustment section of FIG. 16 are applied.

After the program for the dummy cells is terminated by performing the operation up to step S147, a post program for the normal memory cells is performed in step S148, and a program verify operation is performed in step S149. In step S148, biasing voltages as shown in the normal cell post program section in the post program section for the normal cells in FIG. 16 are applied. By performing the step S148, the threshold voltage values for the normal cells are adjusted to the set post program target voltage values. Then, in step S149, biasing voltages as shown in the normal cell verification section in the post program section for the normal cells in FIG. 16 are applied.

When the execution up to step S149 is completed, the normal memory cells and the dummy memory cells in the memory cell array undergo cell transition as shown in the lower left of FIG. 15 through the state transition ST3 as shown in FIG. 15. Will have

As described above, the memory cell array includes two or more dummy cells each having different threshold voltages in the cell string, for the purpose of preventing a problem such as a read disturb of a normal memory cell in the cell string or the like. Before the post program for the normal memory cells in the semiconductor memory device, the order of programming the dummy cells,

When erasing the normal memory cells, erase is performed in a cell block unit including adjacent dummy cells located closer to the normal memory cells among the dummy memory cells, and then erase erase is performed on the normal memory cells. Performing a step;

Performing a program and executing program verification on all adjacent dummy cells in the memory cell array;

For the remaining dummy cells that do not belong to the adjacent dummy cells, it can be seen that the program has a step of first performing a program verifier and then performing a program on the dummy cells requiring the program.

According to the threshold voltage adjusting method for the dummy cells as described above, since the program operation for the dummy cells is more efficiently and efficiently, the manufacturing cost of the nonvolatile semiconductor memory device is reduced and the program convenience is increased. In addition, the function of the dummy cells is guaranteed to improve the reliability of the access operation of the nonvolatile semiconductor memory device.

The description in the above embodiments is merely given by way of example with reference to the drawings for a more thorough understanding of the present invention, and should not be construed as limiting the present invention. In addition, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the basic principles of the present invention. For example, when the case is different, the number of transistors forming the memory cell string or the number of dummy cells may be decreased or the biasing condition may be changed differently. In addition, although the purpose of the dummy cell has been mainly described as to prevent read disturb, the present invention is not limited thereto and may be employed for other purposes than the normal memory cell.

In the exemplary embodiment of the present invention, the NAND type flash memory is exemplified as the nonvolatile memory. However, the present invention is not limited thereto, and the technical spirit of the present invention may be extended to other nonvolatile memories such as NOR type flash memory or PRAM. Could be.

1 is a block diagram of a conventional nonvolatile semiconductor memory device

FIG. 2A is an equivalent circuit diagram illustrating a connection structure of memory cells in the memory cell array of FIG. 1.

FIG. 2B illustrates a bias voltage relationship applied to the equivalent circuit of FIG. 2A in a read operation mode. FIG.

FIG. 3 is a diagram illustrating voltage stresses respectively occurring in memory cells connected to selected bit lines and unselected bit lines in FIG. 2B.

4 is a view illustrating a connection structure of a memory cell string having a floating forming switching unit for preventing read disturb;

5 is an equivalent circuit diagram showing an example of implementation of FIG. 4.

6 is a view illustrating a relationship of a read operation bias voltage applied to the equivalent circuit of FIG. 5.

7 is an equivalent circuit diagram showing still another embodiment of FIG. 4.

FIG. 8 is a diagram provided to explain voltage stress present in an unselected memory cell according to FIG. 4.

9 is a simulation graph showing a channel voltage boosting effect for preventing read disturbance according to FIG. 4.

10 is a schematic block diagram of a nonvolatile semiconductor memory device according to the present invention.

FIG. 11 illustrates cell string structures having two or more dummy cells per cell string in the memory cell array of FIG. 10. FIG.

FIG. 12 is a flowchart illustrating a sequence relationship between diesting and redundancy for dummy cells and normal memory cells when the apparatus of FIG. 10 is wafer fab-out, according to an embodiment of the present invention.

FIG. 13 is a diagram illustrating an erase operation bias voltage relationship when a block cell is erased in FIG. 11; FIG.

14 is a flowchart illustrating a sequence of a block erase operation and a dummy cell program operation for dummy cells in FIG. 13 according to another embodiment of the present invention.

FIG. 15 is a view illustrating a variation in distribution of threshold voltages of cell transistors in the operation sequence of FIG. 14. FIG.

FIG. 16 is a view illustrating an operating bias voltage relationship applied to each other according to the operation sequence of FIG. 14; FIG.

FIG. 17 is a view illustrating a step increase width of an incremental step pulse program for a dummy cell and a normal cell in a program operation according to FIG. 14; FIG.

Claims (22)

A method of fabricating a plurality of semiconductor memory chips having at least one dummy cell in a cell string on a wafer and then diessing and repairing the semiconductor memory chip at the wafer level: Adjusting a threshold voltage for the dummy cell in the cell string; And performing a second sorting and repairing on the normal memory cells in the cell string. The method of claim 1, further comprising performing diesorting and repairing the dummy cell before completion of the first step. The method of claim 1, wherein the first step is performed by applying a special command different from the normal command. A memory cell array including two or more dummy cells having different threshold voltages in a cell string together with normal memory cells; After a plurality of semiconductor memory chips including the memory cell array are fabricated on a wafer, before diesting and redundancy is performed on the normal memory cells when the semiconductor memory chip is diced and repaired at the wafer level. And a dummy cell controller configured to adjust threshold voltages of the dummy cells in response to an external input command. The nonvolatile semiconductor memory device of claim 4, wherein the dummy cell controller further has a function of performing diesting and redundancy before the threshold voltages of the dummy cells are adjusted. In a semiconductor memory device having a memory cell array having two or more dummy cells having different threshold voltages together with normal memory cells in a cell string, the dummy cells may be programmed before a post program for the normal memory cells. In the way: When erasing the normal memory cells, erase is performed in a cell block unit including adjacent dummy cells located closer to the normal memory cells among the dummy memory cells, and then erase erase is performed on the normal memory cells. Performing a step; Performing a program and executing program verification on all adjacent dummy cells in the memory cell array; And performing program verification on the remaining dummy cells that do not belong to the adjacent dummy cells, and then performing a program on the dummy cells requiring the program. The method of claim 6, And the remaining dummy cells are located closer to the ground select line in the cell string than the adjacent dummy cells. The method of claim 6, In the erase of the cell block unit, a voltage equal to an erase gate voltage applied to a gate of the normal memory cells is applied to the gates of the adjacent dummy cells, and a floating voltage or the erase gate is applied to the gates of the remaining dummy cells. And applying a voltage higher than the voltage. The method of claim 8, And applying a read voltage to the gates of the adjacent dummy cells and applying the read voltage to the gates of the remaining dummy cells during the erase verification. The method of claim 8, And the step increment width of the increment step pulse program used for programming the dummy cells is set higher than that of normal memory cells. 9. The method of claim 8, wherein the program for the dummy cells is performed by an external input command. The method of claim 8, wherein when there are two dummy cells in the cell string, the adjacent dummy cell is connected to a normal memory cell located farthest from a bit line, and the other dummy cell is connected to a ground select transistor. How to. 9. The method of claim 8, wherein when there are three dummy cells in the cell string, the adjacent dummy cell is connected to a normal memory cell located furthest from the bit line, and the remaining dummy cells are respectively connected to the ground select transistor and the string select transistor. Characterized in that connected. A memory cell array including two or more dummy cells having different threshold voltages in a cell string together with normal memory cells; When erasing the normal memory cells, erase is performed in a cell block unit including adjacent dummy cells located closer to the normal memory cells among the dummy memory cells, and then erase erase is performed on the normal memory cells. An erase control circuit for executing; Program and perform program verification on all adjacent dummy cells in the memory cell array, and perform dummy program execution on the remaining dummy cells that do not belong to the adjacent dummy cells, and then target dummy cells that require a program. A nonvolatile semiconductor memory device comprising a dummy cell control circuit for performing a program. The gate of claim 14, wherein the erase control circuit is applied to the normal memory cells in addition to the gate of the adjacent dummy cell when the normal memory cells are erased to prevent the threshold voltages of the dummy cells from being changed. And applying a voltage equal to a voltage and applying a voltage higher than the gate voltage for floating or the gate to the gates of the remaining dummy cells. The method of claim 14, wherein the erase control circuit applies a ground voltage or a read voltage to a gate of the adjacent dummy cell and applies the read voltage to the gates of the remaining dummy cells during the erase verification. A nonvolatile semiconductor memory device. 15. The nonvolatile semiconductor memory device according to claim 14, wherein the dummy cell control circuit sets the step increase width of the increment step pulse program used when programming the dummy cells higher than that of the normal memory cell. 15. The nonvolatile semiconductor memory device of claim 14, wherein the dummy cell control circuit performs a program on the dummy cells in response to a mode register set signal. 15. The method of claim 14, wherein when there are two dummy cells in the cell string, the adjacent dummy cell is connected to a normal memory cell located farthest from a bit line, and the other dummy cell is connected to a ground select transistor. A nonvolatile semiconductor memory device. The nonvolatile semiconductor memory device of claim 14, wherein the dummy cells requiring the program are cells having a threshold value lower than a set threshold voltage. The nonvolatile semiconductor memory device of claim 14, wherein after the program for the dummy cells is terminated, a post program for normal memory cells is performed. A plurality of memories each having a floating gate connected in series with each other in series with a first selection transistor having a drain connected to a bit line, a second selection transistor having a source connected to a common source line, and a source of the first selection transistor A third and fourth selection transistor having a channel connected in series with each other in series between a cell transistor and a source of a last memory cell transistor of the plurality of memory cell transistors and a drain of the second selection transistor; A memory cell array having a plurality of cell strings; An erase control circuit for performing the erase block operation on the plurality of memory cell transistors after the erase of the plurality of memory cell transistors is performed together with the third select transistor when the erase is performed on the plurality of memory cell transistors. Wow; Program and perform program verification on all third selection transistors in the memory cell array, and perform program verification on all fourth selection transistors in the memory cell array first, and then select a fourth selection transistor requiring programming. A non-volatile semiconductor memory device comprising a dummy cell control circuit for performing a program for the target.

Images