KR20070102094A - System in a package having module-to-module connection - Google Patents

System in a package having module-to-module connection Download PDF

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Publication number
KR20070102094A
KR20070102094A KR1020060033791A KR20060033791A KR20070102094A KR 20070102094 A KR20070102094 A KR 20070102094A KR 1020060033791 A KR1020060033791 A KR 1020060033791A KR 20060033791 A KR20060033791 A KR 20060033791A KR 20070102094 A KR20070102094 A KR 20070102094A
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South Korea
Prior art keywords
die
semiconductor die
substrate
stack structure
module
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KR1020060033791A
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Korean (ko)
Inventor
손경주
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엘지이노텍 주식회사
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Priority to KR1020060033791A priority Critical patent/KR20070102094A/en
Publication of KR20070102094A publication Critical patent/KR20070102094A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A die stack structure is provided to reduce fabrication costs by omitting an additional spacer forming process and to decrease the number of corresponding processes by omitting an additional die stacking process on a spacer. A die stack structure includes a substrate and a first semiconductor die. The substrate(100) includes one or more metal line patterns(110,112,114). The first semiconductor die(120) is mounted on the substrate. The first semiconductor die is bonded to the metal line patterns by using wires. The first semiconductor die and the bonding wires are encapsulated by using a sealing member(140). A second semiconductor die(130) is stacked on the sealing member. The size of the first semiconductor die is smaller than that of the second semiconductor die.

Description

다이 스택 구조{System In a Package having module-to-module connection}Die Stack Structure {System In a Package having module-to-module connection}

도 1은 종래의 다이 스택 구조를 보여주는 단면 이미지이다.1 is a cross-sectional image showing a conventional die stack structure.

도 2는 본 발명에 따른 다이 스택 구조를 보여주는 단면도이다.2 is a cross-sectional view showing a die stack structure according to the present invention.

본 발명은 다이 스택(die stack) 구조에 관한 것이다.The present invention relates to a die stack structure.

최근 들어, 이동통신용 모듈 및 시스템의 구현을 위하여 반도체 패키지 시스템에 대해 초소형화 및 고집적화에 대한 요구가 늘어나면서 BGA(Ball Grid Array)나 MCM(Multi Chip Module) 또는 다이 스택(Die Stack)과 같은 다양한 패키지 방식이 제안되고 있다.Recently, as the demand for miniaturization and high integration of semiconductor package systems is increasing for the implementation of modules and systems for mobile communication, various types such as Ball Grid Array (BGA), Multi Chip Module (MCM), or Die Stack Package methods have been proposed.

도 1은 종래의 다이 스택 구조를 보여주는 단면 이미지이다.1 is a cross-sectional image showing a conventional die stack structure.

도시된 바와 같이, 하부로부터 제 1 다이(10), 제 2 다이(20), 및 제 3 다이(30)가 순차적으로 적층되어 있다.As shown, the first die 10, the second die 20, and the third die 30 are stacked sequentially from the bottom.

이와 같은 구조에서, 사이즈가 큰 제 1 다이(10) 위에 그보다 사이즈가 작은 제 2 다이(20)를 적층하는 경우에는 별다른 문제가 없으나, 사이즈가 작은 제 2 다 이(20) 위에 그보다 사이즈가 큰 제 3 다이(30)를 적층하는 경우에는 다른 공정이 요구된다.In such a structure, when the second die 20 having a smaller size is stacked on the first die 10 having a larger size, there is no problem, but the size is larger than the second die 20 having a smaller size. When laminating the third die 30, another process is required.

구체적으로, 제 2 다이(20)에서의 와이어 본딩을 위한 공간을 확보하기 위하여 제 2 다이(20)와 제 3 다이(30) 사이에 스페이서(spacer; 40)가 개재되어야 하기 때문에 제조원가가 증가하며, 스페이서(40) 위에 제 3 다이를 설치하기 위한 다이 스택킹 공정을 한번 더 해야 하는 번거로움이 있다.Specifically, manufacturing cost increases because a spacer 40 must be interposed between the second die 20 and the third die 30 to secure a space for wire bonding in the second die 20. In other words, the die stacking process for installing the third die on the spacer 40 has to be done once more.

따라서, 본 발명은 이러한 문제점을 해결하고 공정 수를 줄이고 제조원가를 줄일 수 있는 다이 스택 구조를 제공하는 것을 목적으로 한다.Accordingly, an object of the present invention is to provide a die stack structure that can solve these problems and reduce the number of processes and the manufacturing cost.

본 발명의 이러한 목적과 다른 목적, 이점 및 특징은 이하에 기술되는 실시예를 통하여 명확하게 이해될 것이다.These and other objects, advantages, and features of the present invention will be clearly understood through the embodiments described below.

본 발명에 따르면, 적어도 표면에 배선 패턴이 형성되는 기판과, 상기 기판 위에 실장되며 상기 배선 패턴과 와이어 본딩되는 하나의 반도체 다이를 포함하며, 상기 하나의 반도체 다이와 본딩 와이어는 밀봉재에 의해 밀봉되며, 상기 밀봉재 위에 다른 반도체 다이가 적층되는 다이 스택 구조가 개시된다.According to the present invention, at least a substrate having a wiring pattern formed on a surface thereof, and a semiconductor die mounted on the substrate and wire-bonded with the wiring pattern, the one semiconductor die and the bonding wire are sealed by a sealing material, A die stack structure is disclosed in which another semiconductor die is stacked over the sealant.

바람직하게, 상기 하나의 반도체 다이는 상기 다른 반도체 다이보다 사이즈가 작다.Advantageously, said one semiconductor die is smaller in size than said other semiconductor die.

다음은 도 2를 참조하여 본 발명의 일 실시예에 따른 패키지 시스템을 설명 한다.Next, a package system according to an embodiment of the present invention will be described with reference to FIG. 2.

도 2는 본 발명에 따른 다이 스택 구조를 보여주는 단면도이다.2 is a cross-sectional view showing a die stack structure according to the present invention.

도 2를 참조하면, 다이 스택 구조의 베이스를 구성하는 기판(100)의 표면과 이면 그리고 내부에는 각각 배선패턴(110, 112, 114)이 형성되고, 기판(100)의 표면과 이면을 관통하는 비아 홀(116)이 형성된다.Referring to FIG. 2, wiring patterns 110, 112, and 114 are formed on the front, back, and inside of the substrate 100 constituting the base of the die stack structure, and penetrate the front and back surfaces of the substrate 100. Via hole 116 is formed.

기판(100)의 표면에는 제 1 다이(120)가 실장되고, 제 1 다이(20)와 기판(100) 표면의 배선패턴(112)은 본딩 와이어(122)를 통하여 전기적으로 연결된다. The first die 120 is mounted on the surface of the substrate 100, and the wiring pattern 112 on the surface of the first die 20 and the substrate 100 is electrically connected through the bonding wire 122.

제 1 다이(120)와 본딩 와이어(122)는 글롭-탑(Glop-Top) 인캡슐레이션 밀봉재(140)로 밀봉된다.The first die 120 and the bonding wires 122 are sealed with a glow-top encapsulation seal 140.

글롭-탑(Glop-Top) 인캡슐레이션 밀봉재(140)는, 잘 알려진 바와 같이, IC 칩과 본딩 와이어를 보호하기 위해서 기계적 및 환경적 특성을 보유하여야 하며 또한 효율적인 열처리를 할 수 있어야 한다. 선폭의 미세화 다이 사이즈의 증가 및 고기능성화, 그리고 다양한 기판재료에 의해 저팽창 인캡슐레이션 밀봉재의 수요가 증대하고 있다. The glow-top encapsulation seal 140, as is well known, must possess mechanical and environmental properties to protect the IC chip and bonding wires and be capable of efficient heat treatment. Miniaturization of line width Increasing die size, high functionality, and various substrate materials are driving the demand for low expansion encapsulation seals.

글롭-탑(Glop-Top) 인캡슐레이션 밀봉재(140) 위에는 제 2 다이(130)가 적층되고 본딩 와이어(132)에 의해 기판(100)의 배선패턴(112)에 전기적으로 연결된다.The second die 130 is stacked on the glow-top encapsulation seal 140 and electrically connected to the wiring pattern 112 of the substrate 100 by the bonding wire 132.

이와 같이 글롭-탑(Glop-Top) 인캡슐레이션 밀봉재(140)로 제 1 다이(120)를 밀봉함으로써, 제 2 다이(130)와의 사이에 제 1 다이(120)로부터의 와이어 본딩을 위한 공간이 확보된다. As such, the first die 120 is sealed with a glow-top encapsulation seal 140, thereby providing a space for wire bonding from the first die 120 to the second die 130. This is secured.

따라서, 종래와 달리 별도의 스페이서를 개재할 필요가 없어 그만큼 제조원 가가 절감되고, 스페이서를 개재하고 스페이서 위에 제 2 다이(120)를 다이 스택킹하기 위한 별도의 공정이 필요하지 않게 되어 공정 수를 줄일 수 있는 이점이 있다.Therefore, unlike the prior art, it is not necessary to intervene a separate spacer, thereby reducing manufacturing cost, and a separate process for die stacking the second die 120 over the spacer is not required, thereby reducing the number of processes. There is an advantage to this.

이 실시예에서는 제 1 다이의 사이즈가 제 2 다이의 사이즈보다 작은 경우를 예로 들었지만, 그 반대의 경우도 당연히 적용됨은 물론이다.In this embodiment, the case where the size of the first die is smaller than the size of the second die is exemplified, but the reverse is naturally applied.

이상에서는 본 발명의 바람직한 실시예를 중심으로 설명하였지만, 당업자의 수준에서 다양한 변경이나 변경을 가할 수 있다. 따라서, 본 발명의 권리범위는 상기한 실시예에 한정되어 해석되어서는 안 되며, 이하에 기술되는 특허청구범위에 의해 판단되어야 할 것이다.Although the above has been described with reference to the preferred embodiment of the present invention, various changes or modifications can be made at the level of those skilled in the art. Therefore, the scope of the present invention should not be construed as limited to the above embodiment, but should be determined by the claims described below.

이상에서 설명한 바와 같이, 종래와 달리 별도의 스페이서를 개재할 필요가 없어 그만큼 제조원가가 절감되고, 스페이서를 개재하고 스페이서 위에 제 2 다이를 다이 스택킹하기 위한 별도의 공정이 필요하지 않게 되어 공정 수를 줄일 수 있는 이점이 있다.As described above, unlike the prior art, there is no need to intervene with a separate spacer, thereby reducing manufacturing costs, and a separate process for die stacking a second die over the spacer through a spacer is not required. There is an advantage to reduce.

Claims (2)

적어도 표면에 배선 패턴이 형성되는 기판과, 상기 기판 위에 실장되며 상기 배선 패턴과 와이어 본딩되는 하나의 반도체 다이를 포함하며,A substrate having at least a wiring pattern formed on a surface thereof, and a semiconductor die mounted on the substrate and wire-bonded with the wiring pattern, 상기 하나의 반도체 다이와 본딩 와이어는 밀봉재에 의해 밀봉되며,The one semiconductor die and the bonding wire are sealed by a sealing material, 상기 밀봉재 위에 다른 반도체 다이가 적층되는 것을 특징으로 하는 다이 스택 구조.A die stack structure, wherein another semiconductor die is laminated on the sealant. 청구항 1에 있어서,The method according to claim 1, 상기 하나의 반도체 다이는 상기 다른 반도체 다이보다 사이즈가 작은 것을 특징으로 하는 다이 스택 구조.And wherein said one semiconductor die is smaller in size than said other semiconductor die.
KR1020060033791A 2006-04-13 2006-04-13 System in a package having module-to-module connection KR20070102094A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100908764B1 (en) * 2007-07-19 2009-07-22 앰코 테크놀로지 코리아 주식회사 Semiconductor package and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100908764B1 (en) * 2007-07-19 2009-07-22 앰코 테크놀로지 코리아 주식회사 Semiconductor package and manufacturing method thereof

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