KR100762875B1 - Stack type package - Google Patents

Stack type package Download PDF

Info

Publication number
KR100762875B1
KR100762875B1 KR1020050128612A KR20050128612A KR100762875B1 KR 100762875 B1 KR100762875 B1 KR 100762875B1 KR 1020050128612 A KR1020050128612 A KR 1020050128612A KR 20050128612 A KR20050128612 A KR 20050128612A KR 100762875 B1 KR100762875 B1 KR 100762875B1
Authority
KR
South Korea
Prior art keywords
chip
stacked
substrate
lead frame
package
Prior art date
Application number
KR1020050128612A
Other languages
Korean (ko)
Other versions
KR20070067380A (en
Inventor
황찬기
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020050128612A priority Critical patent/KR100762875B1/en
Publication of KR20070067380A publication Critical patent/KR20070067380A/en
Application granted granted Critical
Publication of KR100762875B1 publication Critical patent/KR100762875B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

개시된 적층형 패키지는, 윈도우가 형성된 리드 프레임과, 리드 프레임 일측에 실장되며, 윈도우를 통해 제1 와이어 본딩된 제1 칩과, 제1 칩 상에 적층된 제2 칩과, 리드 프레임 양측단부 각각에 솔더 볼을 매개로 적층되며, 제2 칩 일측과 다수의 범프에 의하여 연결된 기판과, 기판 상에 실장되며, 제2 와이어 본딩된 제3 칩 및 제1,2,3 칩 및 제1,2 와이어를 외부로부터 보호하기 위하여 밀봉한 EMC를 포함함으로써, LOC 구조 및 플립칩 범프 기술을 혼합하여 칩을 적층시키므로 와이어간의 쇼트 발생에 의한 불량률을 줄일 수 있고, 와이어의 높이도 줄일 수 있으므로 전체적인 패키지의 두께를 줄일 수 있는 효과를 제공한다.The disclosed stacked package includes a lead frame having a window, a first chip bonded to a first wire through a window, a second chip stacked on the first chip, and a lead frame at both ends. Stacked through the solder ball, the substrate is connected to the one side of the second chip by a plurality of bumps, the third chip and the first, second, third and first and second wire bonded on the substrate, the second wire bonded By including EMC sealed in order to protect the device from the outside, the chip is stacked by mixing the LOC structure and flip chip bump technology to reduce the defect rate caused by the short circuit between the wires and the height of the wire. Provides the effect of reducing

Description

적층형 패키지{Stack type package}Stack type package

도 1은 종래의 적층형 패키지를 나타낸 단면도,1 is a cross-sectional view showing a conventional stacked package,

도 2는 본 발명의 일 실시예에 따른 적층형 패키지를 나타낸 단면도,2 is a cross-sectional view showing a stacked package according to an embodiment of the present invention;

도 3a 내지 도 3e는 도 2의 적층형 패키지 제조방법을 순차적으로 나타낸 단면도.3A to 3E are cross-sectional views sequentially illustrating the method of manufacturing the stacked package of FIG. 2.

본 발명은 적층형 패키지에 관한 것으로서, 특히 기판과 리드 프레임을 혼합하여 다수의 칩을 적층시키는 적층형 패키지 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stacked package, and more particularly, to a stacked package in which a plurality of chips are stacked by mixing a substrate and a lead frame, and a manufacturing method thereof.

반도체 패키지는 웨이퍼 공정에 의해 만들어진 개개의 칩을 실제 전자 부품으로써 사용할 수 있도록 전기적 연결을 해주고, 외부의 충격으로부터 보호되도록 밀봉 포장한 것을 말하며, 최근 고용량, 고집적, 초소형화된 반도체 제품에 대한 요구에 부응하기 위해 다양한 반도체 패키지들이 개발되고 있다.A semiconductor package is a package that is electrically sealed so that individual chips made by a wafer process can be used as actual electronic components and are sealed to protect against external shocks. The semiconductor package has recently been developed to meet the demand for high-capacity, high-density and microminiature semiconductor products. Various semiconductor packages are being developed to meet this.

이러한 다양한 반도체 패키지 중 고용량, 고집적화 등을 만족시키기 위하여 도 1과 같이 기판(11) 상에 다수의 칩(12)이 적층되며, 기판(11)과 다수의 칩(12) 각각을 전기적으로 연결하기 위하여 와이어(13) 본딩된 구조의 적층형 패키지(10) 가 출현하였다.Among the various semiconductor packages, a plurality of chips 12 are stacked on the substrate 11 to satisfy high capacity, high integration, and the like, and electrically connect each of the substrate 11 and the plurality of chips 12 to each other. For this purpose, a stacked package 10 having a structure of bonding wires 13 has emerged.

그런데, 이와 같은 구조의 적층형 패키지(10)의 경우, 다수의 칩(12) 각각과 기판(11) 사이를 와이어(13) 본딩 시, 이 와이어(13)들 사이에 쇼트 등이 발생되어 패키지(10)의 불량을 야기시킬 수 있는 문제점이 있고, 또한 와이어(13)의 높이에 의한 패키지(10) 전체의 두께가 커져 최근 초소형화 경향에 반하는 문제점이 있다.However, in the case of the stacked package 10 having such a structure, when the wire 13 is bonded between each of the plurality of chips 12 and the substrate 11, a short is generated between the wires 13 so that the package ( There is a problem that can cause a defect of 10), and also the thickness of the entire package 10 due to the height of the wire 13 has a problem contrary to the recent miniaturization tendency.

미설명 부호 14는 EMC이다.Reference numeral 14 is EMC.

본 발명은 상기의 문제점을 해결하기 위하여 창출된 것으로서, 와이어들 간의 쇼트 등에 의한 불량 발생을 줄이고, 패키지 전체 두께를 줄일 수 있는 개선된 적층형 패키지를 제공하는 것을 그 목적으로 한다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide an improved laminated package that can reduce the occurrence of defects due to shorts between wires and reduce the overall thickness of the package.

상기의 목적을 달성하기 위한 본 발명의 적층형 패키지는, 윈도우가 형성된 리드 프레임; 상기 리드 프레임 일측에 실장되며, 상기 윈도우를 통해 제1 와이어 본딩된 제1 칩; 상기 제1 칩 상에 적층된 제2 칩; 상기 리드 프레임 양측단부 각각에 솔더 볼을 매개로 적층되며, 상기 제2 칩 일측과 다수의 범프에 의하여 연결된 기판; 상기 기판 상에 실장되며, 제2 와이어 본딩된 제3 칩; 및 상기 제1,2,3 칩 및 상기 제1,2 와이어를 외부로부터 보호하기 위하여 밀봉한 EMC를 포함한 것이 바람직하다.Laminated package of the present invention for achieving the above object, the window frame is formed; A first chip mounted on one side of the lead frame and first wire bonded through the window; A second chip stacked on the first chip; A substrate stacked on each of both ends of the lead frame through solder balls and connected to one side of the second chip by a plurality of bumps; A third chip mounted on the substrate and second wire bonded; And EMC sealed in order to protect the first, second and third chips and the first and second wires from the outside.

여기서, 상기 제1칩과 상기 제2 칩 사이에는 방열판이 개재된 것이 바람직하다.Here, the heat sink is preferably interposed between the first chip and the second chip.

이하 첨부된 도면을 참조하면서 본 발명의 바람직한 실시예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2는 본 발명의 일 실시예에 따른 적층형 패키지를 나타낸 단면도이고, 도 3a 내지 도 3e는 도 2의 적층형 패키지의 제조방법을 순차적으로 나타낸 단면도이다.2 is a cross-sectional view illustrating a stacked package according to an embodiment of the present invention, and FIGS. 3A to 3E are cross-sectional views sequentially illustrating a method of manufacturing the stacked package of FIG. 2.

도면을 참조하면, 적층형 패키지(100)는 리드 프레임(110)과, 제1,2,3 칩(131,132,133)과, 기판(120)과, 제1,2 와이어(141,143) 및 EMC(150)를 포함한다.Referring to the drawings, the stacked package 100 includes a lead frame 110, first, second, and third chips 131, 132, and 133, a substrate 120, first, second wires 141, 143, and an EMC 150. Include.

제1 칩(131)은 도 3a와 같이 LOC 구조로 리드 프레임(110) 상에 실장되며, 이 리드 프레임(110)에 형성된 윈도우를 통해 제1 칩(131)과 리드 프레임(110)을 전기적으로 연결하기 위하여 제1 와이어(141)에 의하여 본딩된다.The first chip 131 is mounted on the lead frame 110 in a LOC structure as shown in FIG. 3A, and electrically connects the first chip 131 and the lead frame 110 through a window formed in the lead frame 110. Bonded by first wire 141 to connect.

제2 칩(132)은 도 3b와 같이 플립칩 범프 기술을 이용하여 기판(120) 상에 다수의 범프(142)를 매개로 실장되며, 이 제2 칩(132)은 제1 칩(131) 상에 부착되고, 기판(120)은 솔더 볼(144)을 매개로 리드 프레임(110) 양측단부 각각에 적층된다.As illustrated in FIG. 3B, the second chip 132 is mounted on the substrate 120 through a plurality of bumps 142 using a flip chip bump technology, and the second chip 132 is formed by the first chip 131. The substrate 120 is attached to each of both ends of the lead frame 110 through the solder ball 144.

이때, 제1 칩(131)과 제2 칩(132) 사이에는 도 3c와 같이 방열판(160)이 개재될 수 있는데, 이 방열판(160)은 제1,2 칩(131,132) 구동 시 발생되는 고온의 열을 외부로 방출하기 위한 것이다.In this case, a heat sink 160 may be interposed between the first chip 131 and the second chip 132 as shown in FIG. 3C, and the heat sink 160 is a high temperature generated when the first and second chips 131 and 132 are driven. To release the heat of the outside.

기판(120) 상에는 도 3d와 같이 제3 칩(133)이 실장되며, 제2 와이어(143)에 의하여 제3 칩(133)과 기판(120)이 서로 전기적으로 연결된다.The third chip 133 is mounted on the substrate 120 as illustrated in FIG. 3D, and the third chip 133 and the substrate 120 are electrically connected to each other by the second wire 143.

마지막으로, EMC(150)는 밀봉 부재로써, 도 3e와 같이 제1,2,3 칩 (131,132,133)과 제1,2 와이어(141,143)를 외부로부터 보호하기 위하여 밀봉한다.Finally, the EMC 150 is a sealing member, and seals the first, second, and third chips 131, 132, and 133 and the first and second wires 141 and 143 from the outside, as shown in FIG. 3E.

이와 같은 구조의 적층형 패키지는 칩이 실장되는 부재로써, 기판과 리드 프레임 양자를 모두 사용하고, 또한 전기적 연결을 위하여 와이어와, 범프 및 솔더 볼을 사용하며, 이 와이어와, 범프 및 솔더 볼이 서로 마련되는 위치가 상이하여 서로 쇼트 등의 현상이 발생되지 않아 패키지의 불량률을 줄일 수 있게 된다.The stacked package of such a structure is a member on which a chip is mounted, which uses both a substrate and a lead frame, and also uses wires, bumps, and solder balls for electrical connection, and the wires, bumps, and solder balls are connected to each other. Since the positions provided are different from each other, such a short circuit does not occur, thereby reducing the defective rate of the package.

또한, 와이어의 수가 적고, 서로 쇼트나지 않도록 분산되므로 그 높이가 한정되어 패키지의 전체적인 두께가 얇아지게 된다.In addition, since the number of wires is small and distributed so as not to short each other, the height is limited, and the overall thickness of the package is reduced.

상술한 바와 같이 본 발명의 적층형 패키지에 의하면, LOC 구조 및 플립칩 범프 기술을 혼합하여 칩을 적층시키므로 와이어간의 쇼트 발생에 의한 불량률을 줄일 수 있고, 와이어의 높이도 줄일 수 있으므로 전체적인 패키지의 두께를 줄일 수 있는 효과를 제공한다.As described above, according to the stacked package of the present invention, since the chips are stacked by mixing the LOC structure and the flip chip bump technology, the defect rate caused by the short circuit between the wires can be reduced, and the height of the wire can be reduced, thereby reducing the overall package thickness. It provides a reduction effect.

본 발명은 상기에 설명되고 도면에 예시된 것에 의해 한정되는 것은 아니며, 다음에 기재되는 청구의 범위 내에서 더 많은 변형 및 변용예가 가능한 것임은 물론이다.It is to be understood that the invention is not limited to that described above and illustrated in the drawings, and that more modifications and variations are possible within the scope of the following claims.

Claims (2)

윈도우가 형성된 리드 프레임; A lead frame in which a window is formed; 상기 리드 프레임 일측에 실장되며, 상기 윈도우를 통해 제1 와이어 본딩된 제1 칩; A first chip mounted on one side of the lead frame and first wire bonded through the window; 상기 제1 칩 상에 적층된 제2 칩; A second chip stacked on the first chip; 상기 리드 프레임 양측단부 각각에 솔더 볼을 매개로 적층되며, 상기 제2 칩 일측과 다수의 범프에 의하여 연결된 기판; A substrate stacked on each of both ends of the lead frame through solder balls and connected to one side of the second chip by a plurality of bumps; 상기 기판 상에 실장되며, 제2 와이어 본딩된 제3 칩; 및 A third chip mounted on the substrate and second wire bonded; And 상기 제1,2,3 칩 및 상기 제1,2 와이어를 외부로부터 보호하기 위하여 밀봉한 EMC를 포함한 것을 특징으로 하는 적층형 패키지.And the EMC package sealed to protect the first, second and third chips and the first and second wires from the outside. 제1항에 있어서,The method of claim 1, 상기 제1칩과 상기 제2 칩 사이에는 방열판이 개재된 것을 특징으로 하는 적층형 패키지.Stacked package, characterized in that the heat sink is interposed between the first chip and the second chip.
KR1020050128612A 2005-12-23 2005-12-23 Stack type package KR100762875B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020050128612A KR100762875B1 (en) 2005-12-23 2005-12-23 Stack type package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020050128612A KR100762875B1 (en) 2005-12-23 2005-12-23 Stack type package

Publications (2)

Publication Number Publication Date
KR20070067380A KR20070067380A (en) 2007-06-28
KR100762875B1 true KR100762875B1 (en) 2007-10-08

Family

ID=38366054

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020050128612A KR100762875B1 (en) 2005-12-23 2005-12-23 Stack type package

Country Status (1)

Country Link
KR (1) KR100762875B1 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010090377A (en) * 2000-03-25 2001-10-18 마이클 디. 오브라이언 Semiconductor package and its manufacturing method

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010090377A (en) * 2000-03-25 2001-10-18 마이클 디. 오브라이언 Semiconductor package and its manufacturing method

Also Published As

Publication number Publication date
KR20070067380A (en) 2007-06-28

Similar Documents

Publication Publication Date Title
KR101070913B1 (en) Stacked die package
US6414381B1 (en) Interposer for separating stacked semiconductor chips mounted on a multi-layer printed circuit board
US7554185B2 (en) Flip chip and wire bond semiconductor package
US7745918B1 (en) Package in package (PiP)
US20060097402A1 (en) Semiconductor device having flip-chip package and method for fabricating the same
US20080164605A1 (en) Multi-chip package
JP2006522478A (en) Semiconductor multi-package module including processor and memory package assembly
JP2013211407A (en) Semiconductor module
US20060284298A1 (en) Chip stack package having same length bonding leads
WO2006106569A1 (en) Stacked type semiconductor device and method for manufacturing same
US20070052082A1 (en) Multi-chip package structure
KR20100056247A (en) Semiconductor package having adhesive layer
US6818999B2 (en) Semiconductor device having multiple semiconductor chips in a single package
JP4602223B2 (en) Semiconductor device and semiconductor package using the same
JP2008277457A (en) Multilayer semiconductor device and package
US20140097530A1 (en) Integrated circuit package
KR100762875B1 (en) Stack type package
KR101111921B1 (en) Semiconductor package
KR100650769B1 (en) Stack type package
JP2005150771A (en) Wiring board, semiconductor device, and package stacks semiconductor device
KR20110107117A (en) Semiconductor package
KR20070078953A (en) Stack type package
KR101708870B1 (en) Stacked semiconductor package and method for manufacturing the same
JP2000012771A (en) Semiconductor device
KR100813621B1 (en) Stacked semiconductor device package

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20100825

Year of fee payment: 4

LAPS Lapse due to unpaid annual fee