JP2000012771A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2000012771A JP2000012771A JP10173713A JP17371398A JP2000012771A JP 2000012771 A JP2000012771 A JP 2000012771A JP 10173713 A JP10173713 A JP 10173713A JP 17371398 A JP17371398 A JP 17371398A JP 2000012771 A JP2000012771 A JP 2000012771A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- package
- type semiconductor
- mold package
- package type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1029—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being a lead frame
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、小型化に適合する
半導体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device suitable for miniaturization.
【０００２】[0002]
【従来の技術】近年、携帯端末の小型化に伴い半導体装
置の小型化が要求されており、チップサイズのＢＧＡ
（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）構造をもつ半導体
装置が開発されている。2. Description of the Related Art In recent years, miniaturization of semiconductor devices has been demanded along with miniaturization of portable terminals, and chip-size BGAs have been required.
A semiconductor device having a (Ball Grid Array) structure has been developed.
【０００３】現在メモリパッケージの主流であるＴＳＯ
Ｐ、ＳＯＪ等のモールドパッケージ型半導体装置は、メ
モリ容量を増加させるため、図７に示すように上下に積
層するスタック構造が採用されている。[0003] TSO, which is currently the mainstream of memory packages,
In order to increase the memory capacity, a mold package type semiconductor device such as a P or SOJ adopts a stack structure in which layers are stacked vertically as shown in FIG.
【０００４】図７に示すＴＳＯＰ、ＳＯＪ等のモールド
パッケージ型半導体装置は、能動素子としてのチップ１
がＬＯＣテープ２を介してインナーリード３上に搭載さ
れ、チップ１とインナーリード３との間がワイヤー４を
介して電気的に接続され、これらが樹脂にてモールドさ
れて気密に封止されたパッケージ５の構造になってい
る。さらに、インナーリード３から延びるアウターリー
ド６は、パッケージ５の側面から横方向に延在し、ガル
ウイング形状、或いはＪリード形状に成形されている。[0004] A mold package type semiconductor device such as TSOP or SOJ shown in FIG.
Are mounted on the inner leads 3 via the LOC tape 2, the chip 1 and the inner leads 3 are electrically connected via the wires 4, and these are molded with resin and hermetically sealed. It has the structure of the package 5. Further, an outer lead 6 extending from the inner lead 3 extends laterally from a side surface of the package 5 and is formed in a gull-wing shape or a J-lead shape.
【０００５】図７に示すＴＳＯＰ、ＳＯＪ等のモールド
パッケージ型半導体装置をスタック構造に組合わせるに
は、下段モールドパッケージ型半導体装置のパッケージ
５から延びるアウターリード６を基板７のパッド（図示
略）に接合し、下段モールドパッケージ型半導体装置上
に上段モールドパッケージ型半導体装置を積層した後、
上下のパッケージ５から延びるアウターリード６同士を
接合している。In order to combine a mold package type semiconductor device such as TSOP or SOJ shown in FIG. 7 into a stack structure, outer leads 6 extending from a package 5 of a lower mold package type semiconductor device are attached to pads (not shown) of a substrate 7. After bonding and stacking the upper mold package type semiconductor device on the lower mold package type semiconductor device,
Outer leads 6 extending from upper and lower packages 5 are joined to each other.
【０００６】図７に示すＴＳＯＰ、ＳＯＪ等のモールド
パッケージ型半導体装置では、スタック構造に組合わせ
た場合に、上下の寸法を縮小するには限界があるため、
上述したようにアウターリードを削除し、パッケージの
下面に電極を集中して設け半田ボールで接合するチップ
サイズのＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）構
造をもつモールドパッケージ型半導体装置（以下、モー
ルドＢＧＡ構造のパッケージという）が開発されてい
る。In the case of a mold package type semiconductor device such as TSOP or SOJ shown in FIG. 7, there is a limit in reducing the vertical dimension when combined with a stack structure.
As described above, the outer package is eliminated, electrodes are concentrated on the lower surface of the package, and a packaged semiconductor device having a chip size BGA (Ball Grid Array) structure (hereinafter referred to as a package having a molded BGA structure) is formed by bonding with solder balls. Has been developed.
【０００７】[0007]
【発明が解決しようとする課題】ところで、図７に示す
ＴＳＯＰ、ＳＯＪ等のパッケージは、側面に電気的接続
部となるアウターリード６があるため、比較的容易にス
タック構造を採用することが可能であるが、しかしなが
ら、モールドＢＧＡ構造のパッケージは、パッケージの
下面に電気的接続部となる半田ボール（ＢＧＡ構造）が
あるため、スタックした場合に電気的に接続することが
困難であるという課題がある。By the way, the packages such as TSOP and SOJ shown in FIG. 7 have outer leads 6 serving as electrical connection portions on the side surfaces, so that a stack structure can be relatively easily adopted. However, in the package of the molded BGA structure, there is a problem that it is difficult to electrically connect when stacked, because the solder ball (BGA structure) serving as an electrical connection portion is provided on the lower surface of the package. is there.
【０００８】仮に、スタック構造として構成可能である
としても、基板との接続に半田ボールを用いるため、温
度サイクル時のパッケージと基板との熱膨張係数差から
生じる熱応力により、半田接続部にクラックが発生する
という課題がある。[0008] Even if it is possible to form a stack structure, since solder balls are used for connection to the substrate, cracks may be formed in the solder connection portion due to thermal stress generated by a difference in thermal expansion coefficient between the package and the substrate during a temperature cycle. There is a problem that occurs.
【０００９】本発明の目的は、チップサイズのＢＧＡ
（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）構造をもつ半導体
装置を用いて積層し、かつ熱膨張係数差から生じる熱応
力によるクラックの発生を防止した半導体装置を提供す
ることにある。An object of the present invention is to provide a chip-size BGA.
It is an object of the present invention to provide a semiconductor device which is stacked using a semiconductor device having a (Ball Grid Array) structure and in which cracks are prevented from being generated due to thermal stress caused by a difference in thermal expansion coefficient.
【００１０】[0010]
【課題を解決するための手段】前記目的を達成するた
め、本発明に係る半導体装置は、モールドパッケージ型
半導体装置を複数積層する構造の半導体装置であって、
最下段の前記モールドパッケージ型半導体装置は、基板
への実装用アウターリードが設けられ、かつ上面に表面
実装型の電極が設けられたものであり、前記最下段のモ
ールドパッケージ型半導体装置上に積層する上段のモー
ルドパッケージ型半導体装置は、下面に表面実装型の電
極が設けられたものであり、前記上下段の前記モールド
パッケージ型半導体装置は、前記表面実装型の電極同士
を接続して上下に積層したものである。In order to achieve the above object, a semiconductor device according to the present invention is a semiconductor device having a structure in which a plurality of mold package type semiconductor devices are stacked,
The lowermost packaged semiconductor device has an outer lead for mounting on a substrate, and a surface mounted electrode provided on the upper surface, and is stacked on the lowermost packaged semiconductor device. The upper-stage mold package type semiconductor device is provided with surface-mounting type electrodes on the lower surface, and the upper and lower stage mold package-type semiconductor devices connect the surface-mounting type electrodes to each other vertically. It is a laminate.
【００１１】また本発明に係る半導体装置は、モールド
パッケージ型半導体装置を複数積層する構造の半導体装
置であって、上下段の前記モールドパッケージ型半導体
装置は、基板への実装用アウターリードが設けられ、か
つ上面に表面実装型の電極が設けられたものであり、下
段のモールドパッケージ型半導体装置は、前記アウター
リードにより基板に実装され、上段のモールドパッケー
ジ型半導体装置は、姿勢を反転させて表面実装型の電極
同士を接続し、前記下段の前記モールドパッケージ型半
導体装置上に積層したものである。The semiconductor device according to the present invention is a semiconductor device having a structure in which a plurality of mold package type semiconductor devices are stacked. The upper and lower mold package type semiconductor devices are provided with outer leads for mounting on a substrate. And a surface-mount type electrode provided on the upper surface, the lower mold package type semiconductor device is mounted on the substrate by the outer leads, and the upper mold package type semiconductor device is The mounting type electrodes are connected to each other and are stacked on the mold package type semiconductor device in the lower stage.
【００１２】また前記表面実装型の電極は、半田ボール
で接続するＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）
構造である。Further, the surface-mounting type electrodes are connected to each other by a solder ball (BGA (Ball Grid Array)).
It is a structure.
【００１３】また前記アウターリードは、前記モールド
パッケージ型半導体装置の側面から張出した構造のもの
である。[0013] The outer lead has a structure protruding from a side surface of the mold package type semiconductor device.
【００１４】また前記アウターリードは、ガルウイング
形状、叉はＪリード形状に成形されたものである。The outer lead is formed into a gull wing shape or a J-lead shape.
【００１５】[0015]
【発明の実施の形態】以下、本発明の実施の形態を図に
より説明する。 （実施形態１）図１は、本発明の実施形態１に係る半導
体装置を示す断面図である。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings. Embodiment 1 FIG. 1 is a sectional view showing a semiconductor device according to Embodiment 1 of the present invention.
【００１６】図１に示す本発明の実施形態１に係る半導
体装置は、モールドパッケージ型半導体装置を複数積層
する構造の半導体装置である。The semiconductor device according to the first embodiment of the present invention shown in FIG. 1 is a semiconductor device having a structure in which a plurality of mold package type semiconductor devices are stacked.
【００１７】図１に示すように、本発明の実施形態１に
係るモールドパッケージ型半導体装置は、半田ボールで
接続するＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）構
造として構成したものであり、その構造は、能動素子と
してのチップ１をＬＯＣテープ２を介してインナーリー
ド３上に搭載し、チップ１とインナーリード３との間が
ワイヤー４を介して電気的に接続し、これらが樹脂にて
モールドして気密に封止されたパッケージ５の構造に構
成したものである。As shown in FIG. 1, the mold package type semiconductor device according to the first embodiment of the present invention is configured as a BGA (Ball Grid Array) structure connected by solder balls. The chip 1 is mounted on the inner lead 3 via the LOC tape 2, and the chip 1 and the inner lead 3 are electrically connected via the wire 4. It is configured in a sealed package 5 structure.
【００１８】さらに、パッケージ５の下面５ｂに複数の
電極８，８・・・を集中して設け、各電極８に半田ボー
ル９の端子を設けたＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒ
ｒａｙ）構造として構成したものである。Further, a plurality of electrodes 8, 8... Are collectively provided on the lower surface 5b of the package 5, and a terminal of a solder ball 9 is provided on each electrode 8 (Ball Grid Ar).
(ray) structure.
【００１９】本発明の実施形態１では、上述したＢＧＡ
（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）構造のモールドパ
ッケージ型半導体装置を上段に積層するための半導体装
置（以下、上段のパッケージという）として用いてい
る。In the first embodiment of the present invention, the above-described BGA
It is used as a semiconductor device (hereinafter, referred to as an upper package) for stacking a mold package type semiconductor device having a (Ball Grid Array) structure in an upper stage.
【００２０】さらに本発明の実施形態１では、上述した
ＢＧＡ構造のモールドパッケージ型半導体装置に、基板
７への実装用アウターリード６を設け、上段のパッケー
ジ５を支える下段のモールドパッケージ型半導体装置
（以下、下段のパッケージという）として用いている。Further, in the first embodiment of the present invention, the outer package 6 for mounting on the substrate 7 is provided in the above-mentioned mold package type semiconductor device having the BGA structure, and the lower mold package type semiconductor device ( Hereinafter, referred to as a lower package).
【００２１】下段のパッケージ５におけるアウターリー
ド６は、パッケージ５内のインナーリード３から延び、
パッケージ５の側面から張出した構造のものであり、ア
ウターリード６は、ガルウイング形状に成形している。The outer leads 6 in the lower package 5 extend from the inner leads 3 in the package 5,
The outer lead 6 is formed in a gull-wing shape.
【００２２】なお、図１に示す本発明の実施形態１に係
るモールドパッケージ型半導体装置は図２に示すよう
に、ＬＯＣテープ２を用いたリード オン チップ（Ｌ
ＯＣ）構造のインナーリード３に半田ボール９の端子を
設けて表面実装する構造のものを図示したが、これに限
定されるものではなく、図３に示すように、ＣＯＬテー
プ２ａを用いたチップ オン リード（ＣＯＬ）構造の
インナーリード３に半田ボール９の端子を設けて表面実
装する構造にしてもよいものである。As shown in FIG. 1, the molded package type semiconductor device according to the first embodiment of the present invention uses a lead-on-chip (L
Although the structure in which the terminals of the solder balls 9 are provided on the inner leads 3 having the OC) structure and are surface-mounted is illustrated, the present invention is not limited to this, and a chip using a COL tape 2a as shown in FIG. A structure may be employed in which the terminals of the solder balls 9 are provided on the inner leads 3 having an on-lead (COL) structure and are surface-mounted.
【００２３】図１に示す本発明の実施形態１に係るモー
ルドパッケージ型半導体装置をスタック構造に構築する
には、下段パッケージ５から張出したアウターリード６
を基板７に接続し、下段のモールドパッケージ型半導体
装置を基板７に実装する。In order to construct the mold package type semiconductor device according to the first embodiment of the present invention shown in FIG. 1 into a stack structure, the outer leads 6 extending from the lower package 5 are required.
Is connected to the substrate 7, and the lower mold package type semiconductor device is mounted on the substrate 7.
【００２４】図１に示すＢＧＡパッケージの半導体装置
を基板に実装した際の信頼性は、アウターリードをもつ
パッケージと比較すると、かなり低いものである。例え
ば、アウターリードをもつパッケージにおいては、温度
サイクル１０００ｃｙｃまでは基板との半田接続部にク
ラックが発生しないのに対して、ＢＧＡパッケージは４
００ｃｙｃで基板との半田接続部にクラックが発生す
る。The reliability when the semiconductor device of the BGA package shown in FIG. 1 is mounted on a substrate is considerably lower than that of a package having outer leads. For example, in a package having an outer lead, cracks do not occur in a solder connection portion with a substrate until a temperature cycle of 1000 cyc, whereas a BGA package has 4
At 00 cyc, a crack occurs in the solder connection portion with the substrate.
【００２５】さらに、スタック構造とした場合、図２に
示すＢＧＡパッケージでは、パッケージの寸法が大きく
なるため、基板との半田接合部に加わる熱応力は、さら
に大きくなり、実装信頼性が低下すると考えられる。Further, in the case of a stack structure, in the BGA package shown in FIG. 2, since the package size is large, the thermal stress applied to the solder joint with the substrate is further increased, and the mounting reliability is considered to be reduced. Can be
【００２６】本発明に係る実施形態１では、アウターリ
ードをもつパッケージとＢＧＡパッケージとの利点を活
かしてスタック構造として構成している。In the first embodiment according to the present invention, a stack structure is formed by taking advantage of the package having the outer leads and the BGA package.
【００２７】すなわち、本発明の実施形態１では、基板
７との接続に半田ボールでなくアウターリード６を用い
ることにより、温度サイクル時のパッケージ５と基板７
との熱膨張係数差から生じる熱応力を緩和させ、基板と
の半田接続部にクラックが発生するのを防止する。That is, in the first embodiment of the present invention, the outer leads 6 are used instead of the solder balls for connection to the substrate 7, so that the package 5 and the substrate
The thermal stress caused by the difference in thermal expansion coefficient between the substrate and the substrate is reduced, thereby preventing the occurrence of cracks in the solder connection portion with the substrate.
【００２８】また、上段パッケージ５と下段パッケージ
５との接続は、半田ボール９による端子を使用して行っ
ており、熱膨張係数が同じであるため、その実装信頼性
は、問題とならない。The connection between the upper package 5 and the lower package 5 is made by using terminals formed by solder balls 9 and has the same coefficient of thermal expansion. Therefore, the mounting reliability does not matter.
【００２９】したがって、本発明の実施形態１において
スタック構造に構成した場合、その実装信頼性を向上す
ることができるという効果が得られる。Therefore, when a stack structure is used in the first embodiment of the present invention, the effect of improving the mounting reliability can be obtained.
【００３０】また、本発明の実施形態１に係る半導体装
置を製造するには、新たに特別な設備を必要としない。
すなわち、通常のモールドＢＧＡパッケージを作製する
工程を用いればよく、設備投資を押さえることができ
る。In order to manufacture the semiconductor device according to the first embodiment of the present invention, no new special equipment is required.
That is, a process of manufacturing a normal mold BGA package may be used, and equipment investment can be suppressed.
【００３１】上段パッケージ５は通常のモールドＢＧＡ
構造のものであり、ペレッタイズ、マウント、ワイヤー
ボンディング、封入、めっき、ボールマウント、個片分
離、選別、捺印、リード切断という工程を経て製造され
る。The upper package 5 is a normal molded BGA
It has a structure and is manufactured through the steps of pelletizing, mounting, wire bonding, encapsulation, plating, ball mounting, separation of individual pieces, sorting, stamping, and lead cutting.
【００３２】一方、下段パッケージ５は、モールドＢＧ
Ａ構造の製造ラインで選別工程まで行い、その後、アウ
ターリード６を金型で成形すればよい。On the other hand, the lower package 5 includes a mold BG
The process up to the sorting step may be performed on the manufacturing line having the structure A, and then the outer leads 6 may be formed by a mold.
【００３３】従って、リード成形金型と数点の治工具を
必要とするが、新たに特別な設備を必要としない。ま
た、この製造工程により、上段パッケージと下段パッケ
ージを個別に製造するのではなく、選別後、所要に合わ
せてアウターリードのある下段パッケージを製造すれば
よい。Accordingly, although a lead forming die and several jigs and tools are required, no special equipment is required. Also, in this manufacturing process, the upper package and the lower package are not separately manufactured, but the lower package having outer leads may be manufactured as required after sorting.
【００３４】（実施形態２）図４は、本発明の実施形態
２を示す断面図である。(Embodiment 2) FIG. 4 is a sectional view showing Embodiment 2 of the present invention.
【００３５】図４に示す本発明の実施形態２では、下段
パッケージ５のアウターリード６をＪリード形状に成形
したものである。In the second embodiment of the present invention shown in FIG. 4, the outer lead 6 of the lower package 5 is formed into a J-lead shape.
【００３６】図４に示す本発明の実施形態２のように、
アウターリード６をＪリード形状に成形して基板７に実
装すると、その実装信頼性は、図１に示すガルウイング
形状よりも高いため、さらに高い実装信頼性を得ること
ができる。As in Embodiment 2 of the present invention shown in FIG.
When the outer lead 6 is formed into a J-lead shape and mounted on the substrate 7, the mounting reliability is higher than that of the gull-wing shape shown in FIG. 1, so that higher mounting reliability can be obtained.
【００３７】また、図４に示す下段パッケージ５を製造
するには、前記実施形態１と同様に金型で成形すればよ
く、新たな設備を必要としない。Further, in order to manufacture the lower package 5 shown in FIG. 4, it is only necessary to mold with a metal mold as in the first embodiment, and no new equipment is required.
【００３８】（実施形態３）図５は、本発明の実施形態
３を示す断面図である。(Embodiment 3) FIG. 5 is a sectional view showing Embodiment 3 of the present invention.
【００３９】図５に示す本発明の実施形態３に係る半導
体装置は、 上下段のパッケージ５に基板７への実装用
アウターリード６をそれぞれ設け、かつ上面に表面実装
型の電極としての半田ボール９の端子を設けたものであ
り、下段のパッケージ５は、アウターリード６により基
板７に実装し、上段のパッケージ５は、姿勢を反転させ
て半田ボール９の端子同士を接続し、下段のパッケージ
５上に上段のパッケージ５を積層したものである。In the semiconductor device according to the third embodiment of the present invention shown in FIG. 5, outer leads 6 for mounting on a substrate 7 are respectively provided on upper and lower packages 5, and solder balls as surface mounting electrodes are provided on the upper surface. 9 are provided. The lower package 5 is mounted on the substrate 7 by the outer leads 6, and the upper package 5 is connected to the terminals of the solder balls 9 by reversing the posture. The upper package 5 is laminated on the upper package 5.
【００４０】上段、下段パッケージ５のアウターリード
６は、ガルウイング形状に成形しているが、上段、下段
パッケージ５は、アウターリード６を使用せずに半田ボ
ール９の端子同士の接続によりスタック構造として積層
している。The outer leads 6 of the upper and lower packages 5 are formed in a gull wing shape. However, the upper and lower packages 5 have a stacked structure by connecting the terminals of the solder balls 9 without using the outer leads 6. Laminated.
【００４１】図５に示す本発明の実施形態３では、上
段、下段パッケージ５を共通に同一の工程で製造でき、
上段、下段パッケージ５の製造管理を省くことができ
る。According to the third embodiment of the present invention shown in FIG.
Manufacturing control of the upper and lower packages 5 can be omitted.
【００４２】（実施形態４）図６は、本発明の実施形態
４を示す断面図である。(Embodiment 4) FIG. 6 is a sectional view showing Embodiment 4 of the present invention.
【００４３】図６に示す本発明の実施形態４では、上
段、下段パッケージ５のアウターリード６をＪリード形
状に成形し、下段のパッケージ５は、アウターリード６
により基板７に実装し、上段のパッケージ５は、姿勢を
反転させて半田ボール９の端子同士を接続し、下段のパ
ッケージ５上に上段のパッケージ５を積層し、半田ボー
ル９の端子同士の接続によりスタック構造として積層し
たものである。In the fourth embodiment of the present invention shown in FIG. 6, the outer leads 6 of the upper and lower packages 5 are formed into a J-lead shape, and the lower package 5 is formed of the outer leads 6.
The upper package 5 is connected to the terminals of the solder balls 9 by reversing the orientation, the upper package 5 is stacked on the lower package 5, and the connection of the terminals of the solder balls 9 is performed. Are stacked as a stack structure.
【００４４】図６に示す本発明の実施形態４では、上
段、下段パッケージ５を共通に同一の工程で製造でき、
上段、下段パッケージ製造管理を省くことができる。In the fourth embodiment of the present invention shown in FIG. 6, the upper package 5 and the lower package 5 can be commonly manufactured in the same process.
The upper and lower package manufacturing management can be omitted.
【００４５】[0045]
【発明の効果】以上説明したように本発明によれば、基
板との接続に半田ボールでなくアウターリードを用いる
ことにより、温度サイクル時のパッケージと基板との熱
膨張係数差から生じる熱応力を緩和させ、基板との半田
接続部にクラックが発生するのを防止することができ
る。As described above, according to the present invention, by using the outer leads instead of the solder balls for connection to the board, the thermal stress caused by the difference in the thermal expansion coefficient between the package and the board during the temperature cycle can be reduced. This can reduce the occurrence of cracks in the solder connection portion with the substrate.
【００４６】また、上段パッケージと下段パッケージと
の接続は、表面実装型の電極（具体的には半田ボールの
端子）を使用して行っており、熱膨張係数が同じである
ため、その実装信頼性は、問題とならない。The connection between the upper package and the lower package is made by using surface-mounted electrodes (specifically, terminals of solder balls), and has the same coefficient of thermal expansion. Sex does not matter.
【００４７】したがって、本発明においてスタック構造
に構成した場合、その実装信頼性を向上することができ
るという効果が得られる。Therefore, when the present invention is configured in a stack structure, the effect of improving the mounting reliability can be obtained.
【図１】本発明の実施形態１に係る半導体装置を示す断
面図である。FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention.
【図２】本発明の実施形態におけるモールドパッケージ
型半導体装置を示す断面図である。FIG. 2 is a sectional view showing a mold package type semiconductor device according to the embodiment of the present invention.
【図３】本発明の実施形態におけるモールドパッケージ
型半導体装置を示す断面図である。FIG. 3 is a sectional view showing a mold package type semiconductor device according to the embodiment of the present invention.
【図４】本発明の実施形態２に係る半導体装置を示す断
面図である。FIG. 4 is a sectional view showing a semiconductor device according to a second embodiment of the present invention.
【図５】本発明の実施形態３に係る半導体装置を示す断
面図である。FIG. 5 is a sectional view showing a semiconductor device according to a third embodiment of the present invention.
【図６】本発明の実施形態４に係る半導体装置を示す断
面図である。FIG. 6 is a sectional view showing a semiconductor device according to a fourth embodiment of the present invention.
【図７】従来例に係る半導体装置を示す断面図である。FIG. 7 is a sectional view showing a semiconductor device according to a conventional example.
１ チップ ２ テープ ３ インナーリード ４ ワイヤー ５ パッケージ ６ アウターリード ７ 基板 ８ 電極 ９ 半田ボール 1 Chip 2 Tape 3 Inner Lead 4 Wire 5 Package 6 Outer Lead 7 Board 8 Electrode 9 Solder Ball
Claims (5)
積層する構造の半導体装置であって、 最下段のモールドパッケージ型半導体装置は、基板への
実装用アウターリードが設けられ、かつ上面に表面実装
型の電極が設けられたものであり、 前記最下段のモールドパッケージ型半導体装置上に積層
する上段のモールドパッケージ型半導体装置は、下面に
表面実装型の電極が設けられたものであり、 前記上下段の前記モールドパッケージ型半導体装置は、
前記表面実装型の電極同士を接続して上下に積層したも
のであることを特徴とする半導体装置。1. A semiconductor device having a structure in which a plurality of mold package type semiconductor devices are stacked, wherein the lowermost mold package type semiconductor device is provided with outer leads for mounting on a substrate and has a surface mount type on the upper surface. An upper mold package type semiconductor device to be laminated on the lowermost mold package type semiconductor device, wherein a surface mount type electrode is provided on a lower surface; The mold package type semiconductor device,
A semiconductor device characterized in that the surface-mounted electrodes are connected to each other and stacked vertically.
積層する構造の半導体装置であって、 上下段のモールドパッケージ型半導体装置は、基板への
実装用アウターリードが設けられ、かつ上面に表面実装
型の電極が設けられたものであり、 下段のモールドパッケージ型半導体装置は、前記アウタ
ーリードにより基板に実装され、 上段のモールドパッケージ型半導体装置は、姿勢を反転
させて表面実装型の電極同士を接続し、前記下段の前記
モールドパッケージ型半導体装置上に積層したものであ
ることを特徴とする半導体装置。2. A semiconductor device having a structure in which a plurality of mold package type semiconductor devices are stacked, wherein the upper and lower mold package type semiconductor devices are provided with outer leads for mounting on a substrate and have a surface mount type on the upper surface. An electrode is provided, the lower mold package type semiconductor device is mounted on the substrate by the outer lead, and the upper mold package type semiconductor device reverses the posture and connects the surface mount type electrodes to each other. A semiconductor device stacked on the lower mold package type semiconductor device.
接続するＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）構
造であることを特徴とする請求項１又は２に記載の半導
体装置。3. The semiconductor device according to claim 1, wherein the surface-mount type electrode has a BGA (Ball Grid Array) structure connected by a solder ball.
ッケージ型半導体装置の側面から張出した構造のもので
あることを特徴とする請求項１又は２に記載の半導体装
置。4. The semiconductor device according to claim 1, wherein the outer lead has a structure protruding from a side surface of the mold package type semiconductor device.
状、又はＪリード形状に成形されたものであることを特
徴とする請求項４に記載の半導体装置。5. The semiconductor device according to claim 4, wherein the outer lead is formed in a gull wing shape or a J-lead shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10173713A JP3132473B2 (en) | 1998-06-19 | 1998-06-19 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10173713A JP3132473B2 (en) | 1998-06-19 | 1998-06-19 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000012771A true JP2000012771A (en) | 2000-01-14 |
| JP3132473B2 JP3132473B2 (en) | 2001-02-05 |
Family
ID=15965761
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10173713A Expired - Fee Related JP3132473B2 (en) | 1998-06-19 | 1998-06-19 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3132473B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100390947B1 (en) * | 2000-12-29 | 2003-07-10 | 주식회사 하이닉스반도체 | Method of packaging a semiconductor device |
| KR100650734B1 (en) * | 2005-04-29 | 2006-11-27 | 주식회사 하이닉스반도체 | FBGA package |
| KR100668811B1 (en) * | 2000-10-06 | 2007-01-17 | 주식회사 하이닉스반도체 | Stack package |
-
1998
- 1998-06-19 JP JP10173713A patent/JP3132473B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100668811B1 (en) * | 2000-10-06 | 2007-01-17 | 주식회사 하이닉스반도체 | Stack package |
| KR100390947B1 (en) * | 2000-12-29 | 2003-07-10 | 주식회사 하이닉스반도체 | Method of packaging a semiconductor device |
| KR100650734B1 (en) * | 2005-04-29 | 2006-11-27 | 주식회사 하이닉스반도체 | FBGA package |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3132473B2 (en) | 2001-02-05 |
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