JP4892418B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP4892418B2
JP4892418B2 JP2007166097A JP2007166097A JP4892418B2 JP 4892418 B2 JP4892418 B2 JP 4892418B2 JP 2007166097 A JP2007166097 A JP 2007166097A JP 2007166097 A JP2007166097 A JP 2007166097A JP 4892418 B2 JP4892418 B2 JP 4892418B2
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Prior art keywords
semiconductor chip
semiconductor device
tab
wire
electrode pads
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JP2007166097A
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JP2007258751A (en
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大樹 石村
勝則 高橋
満 坂本
直史 浅利
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Renesas Electronics Corp
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Renesas Electronics Corp
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To improve the performance of a lamination-type semiconductor device for satisfying a decrease in packaging height, that in a packaging area, and that in weight, and to reduce costs in an existing manufacturing line. <P>SOLUTION: The semiconductor device made of an insulating resin, where a tab is formed in a frame shape, includes: a sealant 4 made of an insulating resin; a tab 1e for supporting a semiconductor chip; a plurality of leads 1a for exposing one surface to the packaging surface of the sealant; a first semiconductor chip 2 that is positioned in the sealing body, has a first main surface that is a circuit formation surface and a first back at a side opposite to the first main surface, and is supported on one surface of the tab; a plurality of first electrode pads 2a formed on the first main surface of the first semiconductor chip; a second semiconductor chip 3 that has a wire 5 for electrically connecting the electrode pad to the lead, a second main surface that is a circuit formation surface, and a second back at a side opposite to the second main surface, and is mounted in a stack on the first main surface of the first semiconductor chip; and the wire 5 for electrically connecting the plurality of first electrode pads of the first semiconductor chip to the lead, and a plurality of second electrode pads formed on the second main surface of the second semiconductor chip to the lead. <P>COPYRIGHT: (C)2008,JPO&amp;INPIT

Description

本発明は、樹脂封止型半導体製造技術に関し、特に、複数のＬＳＩチップを１つのパッケージに納めたマルチチップパッケージのように高密度実装に適した半導体装置に適用して有効な技術に関する。   The present invention relates to a resin-encapsulated semiconductor manufacturing technique, and more particularly to a technique that is effective when applied to a semiconductor device suitable for high-density mounting such as a multichip package in which a plurality of LSI chips are contained in one package.

近年、半導体パッケージの小型化の要求の中で、複数のＬＳＩチップを１つのパッケージに納めた所謂マルチチップパッケージ（以下ＭＣＰ）、あるいはシステムインパッケージと称される半導体装置が要求されている。このようなＭＣＰの構造の一例としては、ＬＳＩチップを例えば２段に積層し、これを樹脂モールドしてパッケージとしたスタック構造が知られている。スタック構造のＭＣＰの具体例としては、パッケージ内部でＬＳＩチップが積層されたＱＦＰ（Quad Flat leaded Package）タイプのＭＣＰが、例えば特開２００１―２６７４８８号公報（特許文献１）等に記載されている。このタイプのＭＣＰは、積層された複数のＬＳＩチップと、ＬＳＩチップの電極パッドと外部導出リードとを電気的に接続した複数のワイヤと、複数のインナーリードが樹脂モールドされて樹脂封止体が形成されており、樹脂封止体の側面からアウターリードが導出している。実装基板へはこのアウターリードによって実装される。また、他のＭＣＰのタイプとしては、特開平１１―２０４７２０号公報（特許文献２）に記載のように、エポキシあるいはポリイミドからなる配線基板に複数のＬＳＩチップを積層させ、それぞれのＬＳＩチップの電極パッドと配線基板上の電極とをワイヤボンディングまたはフェイスダウンボンディングにより電気的接続をし、配線基板上のそれぞれのＬＳＩチップ及び電気的接続部分を樹脂によりモールドされた所謂ＣＳＰ（Chip Size Package）タイプのＭＣＰが知られている。
特開２００１―２６７４８８号公報 特開平１１―２０４７２０号公報 In recent years, a semiconductor device called a so-called multi-chip package (hereinafter referred to as MCP) in which a plurality of LSI chips are housed in one package or a system-in-package is demanded in the demand for miniaturization of semiconductor packages. As an example of such an MCP structure, there is known a stack structure in which LSI chips are stacked in, for example, two stages and these are molded with a resin. As a specific example of the MCP having a stack structure, a QFP (Quad Flat leaded Package) type MCP in which LSI chips are stacked inside a package is described in, for example, Japanese Patent Application Laid-Open No. 2001-267488 (Patent Document 1). . In this type of MCP, a plurality of stacked LSI chips, a plurality of wires that electrically connect the electrode pads of the LSI chips and external lead leads, and a plurality of inner leads are resin-molded to form a resin sealing body. The outer lead is led out from the side surface of the resin sealing body. The outer leads are mounted on the mounting board. As another MCP type, as described in Japanese Patent Application Laid-Open No. 11-204720 (Patent Document 2), a plurality of LSI chips are stacked on a wiring board made of epoxy or polyimide, and electrodes of the respective LSI chips are stacked. the pads and the electrodes of the wiring board and electrically connected by wire bonding or face-down bonding, each of the LSI chip and the electrical connection portion of the molded with resin were so-called CSP on the wiring board (C hip S ize P ackage ) Type MCPs are known.
JP 2001-267488 A Japanese Patent Laid-Open No. 11-204720

上記ＱＦＰタイプのＭＣＰは、その構造上、樹脂封止体の側面からアウターリードが導出し、また、タブの上下に樹脂封止体が存在しているため、その実装面積、実装高さが大きくなり、昨今の携帯電話やモバイルパソコンのような携帯機器に内蔵される実装基板に対する実装には適していない。また、ＣＳＰタイプのＭＣＰに関しては、実装面積が小さく携帯機器用の実装基板への実装に適している。しかし比較的多機能で外部接続ピン数が大きい場合は有利であるが、組立材料として絶縁性基板（エポキシやポリイミド等の樹脂基板又はフィルム）や半田等からなるボール状の実装用外部端子等を用いており、材料費が高価である、専用の製造設備が必要である、工程が多くなる等の面から外部接続ピン数が小さい場合は割高となる問題点が有る。また、ボール状の実装用外部端子を用いているため、その高さ分はどうしても高くなってしまい、実装高さ低減には限界がある。更に、ＬＳＩチップを積層するにあたって、チップサイズや電極パッド配置の制限があり、既存のＬＳＩチップを流用し難いこと、さらに積層された２つのＬＳＩチップ間の互いの電極パッドを中継することが困難なため、リードの引き回しが制限されるという問題が有る。   The QFP type MCP has a large mounting area and mounting height because the outer leads are led out from the side surface of the resin sealing body and the resin sealing bodies exist above and below the tab. Therefore, it is not suitable for mounting on a mounting board built in a portable device such as a recent mobile phone or mobile personal computer. Further, the CSP type MCP has a small mounting area and is suitable for mounting on a mounting board for portable devices. However, it is advantageous when the number of external connection pins is large with relatively many functions, but as an assembly material, an insulating substrate (resin substrate or film such as epoxy or polyimide) or a ball-shaped external terminal for mounting made of solder or the like is used. However, there are problems that the cost is high when the number of external connection pins is small from the viewpoint of high cost of materials, the need for dedicated manufacturing equipment, and an increase in the number of processes. Further, since the ball-shaped mounting external terminals are used, the height is inevitably increased, and there is a limit to reducing the mounting height. Furthermore, when stacking LSI chips, there are restrictions on the chip size and electrode pad arrangement, making it difficult to divert existing LSI chips, and further relaying each other's electrode pads between two stacked LSI chips. Therefore, there is a problem that lead routing is limited.

本発明者は上記問題点を効果的に解決すべく鋭意検討した。そこで本発明の目的は、実装面積及び実装高さが非常に小さく、既存の製造ラインで低コストに製造可能なマルチチップ型の半導体装置およびその製造方法を提供することにある。   The inventor has intensively studied to effectively solve the above problems. SUMMARY OF THE INVENTION An object of the present invention is to provide a multi-chip type semiconductor device that has a very small mounting area and mounting height and can be manufactured at low cost on an existing manufacturing line, and a manufacturing method thereof.

本発明の前記ならびにその他の課題、および目的と新規な特徴は、本明細書の記述および添付図面から明らかになるであろう。   The above and other problems, objects, and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

本願において開示される発明のうち代表的なものの概要を説明すれば以下のとおりである。   Outlines of representative ones of the inventions disclosed in the present application will be described as follows.

（１）本発明の半導体装置は、絶縁性樹脂からなる封止体と、半導体チップを支持するタブと、前記封止体の実装面に一面を露出する複数のリードと、前記封止体内に位置し、回路形成面である第１主面およびその反対側の第１裏面を有し、前記タブの一面に支持される第１半導体チップと、前記第１半導体チップの第１主面に形成された複数の第1電極パッドと、前記電極パッドと前記リードとを電気的に接続するワイヤと、回路形成面である第２主面およびその反対側の第２裏面を有し、前記第１半導体チップの第１主面に積層搭載された第２半導体チップと、前記第１半導体チップの複数の第1電極パッドと前記リード、前記第２半導体チップの第２主面に形成された複数の第２電極パッドと前記リードとをそれぞれ電気的に接続するワイヤとを含み、前記タブは枠状に形成されているものである。   (1) A semiconductor device according to the present invention includes a sealing body made of an insulating resin, a tab that supports a semiconductor chip, a plurality of leads that are exposed on the mounting surface of the sealing body, and the sealing body. A first semiconductor chip that is positioned and has a first main surface that is a circuit forming surface and a first back surface opposite to the first main surface, and is formed on the first main surface of the first semiconductor chip; A plurality of first electrode pads, a wire for electrically connecting the electrode pads and the leads, a second main surface which is a circuit forming surface, and a second back surface on the opposite side. A second semiconductor chip stacked and mounted on a first main surface of the semiconductor chip; a plurality of first electrode pads and the leads of the first semiconductor chip; and a plurality of first electrodes formed on the second main surface of the second semiconductor chip. The second electrode pad and the lead are electrically connected to each other. And a Ya, the tub is being formed in a frame shape.

また、本発明の半導体装置は、絶縁性樹脂からなる封止体と、半導体チップが搭載されるタブと、前記封止体の実装面に一面を露出する複数のリードと、前記封止体内に位置し、回路形成面である第１の面およびその反対側の第２の面を有し、前記タブの一面に接着剤を介して第２の面で支持される第１の半導体チップと、前記第１の半導体チップの第１の面の周縁部に形成された複数の電極パッドと、前記電極パッドと前記リードとを電気的に接続する導電性のワイヤと、回路形成面である第１の面およびその反対側の第２の面を有し前記第１の半導体チップの第１の面に第２の面を向けて積層搭載された第２の半導体チップと、前記第２の半導体チップの第１の面に形成された複数の電極パッドと、前記第２の半導体チップの電極パッドと前記リードとを電気的に接続する導電性のワイヤを有するものである。   The semiconductor device of the present invention includes a sealing body made of an insulating resin, a tab on which a semiconductor chip is mounted, a plurality of leads that are exposed on the mounting surface of the sealing body, and the sealing body. A first semiconductor chip that is located and has a first surface that is a circuit forming surface and a second surface opposite to the first surface, and is supported on the second surface via an adhesive on one surface of the tab; A plurality of electrode pads formed on a peripheral portion of the first surface of the first semiconductor chip, conductive wires that electrically connect the electrode pads and the leads, and a circuit forming surface. And a second semiconductor chip stacked and mounted with the second surface facing the first surface of the first semiconductor chip, and the second semiconductor chip A plurality of electrode pads formed on the first surface of the second semiconductor chip, and electrode pads of the second semiconductor chip And it has a conductive wire for electrically connecting the lead.

前記第２の半導体チップは、前記第１の半導体チップの電極パッドよりも内側に配置している。前記第２の半導体チップの電極パッドにはバンプが形成され、前記ワイヤの一方は前記リードまたは前記第１の半導体チップの電極パッドと接続され、他方は前記バンプを介して接続されている。前記第１の半導体チップ側の複数の電極パッドのうちのいくつかは、前記ワイヤにより前記タブと電気的に接続されているものである。   The second semiconductor chip is disposed inside the electrode pad of the first semiconductor chip. Bumps are formed on the electrode pads of the second semiconductor chip, one of the wires is connected to the lead or the electrode pad of the first semiconductor chip, and the other is connected via the bumps. Some of the plurality of electrode pads on the first semiconductor chip side are electrically connected to the tab by the wire.

（２）絶縁性樹脂からなる封止体と、半導体チップを支持するタブと、前記封止体の実装面に一面を露出する複数のリードと、前記封止体内に位置し、回路形成面である第１の面およびその反対側の第２の面を有し、前記タブの一面に接着剤を介して支持される第１の半導体チップと、前記第１の半導体チップの第１の面の周縁部に形成された複数の電極パッドと、前記電極パッドと前記リードとを電気的に接続する導電性のワイヤと、回路形成面である第１の面およびその反対側の第２の面を有し前記第１の半導体チップの第１の面に積層搭載された第２の半導体チップと、前記第２の半導体チップの第１の面に形成された複数の電極パッドと前記リードとを電気的に接続する導電性のワイヤを有するものである。   (2) a sealing body made of an insulating resin, a tab that supports a semiconductor chip, a plurality of leads that are exposed on the mounting surface of the sealing body, and a circuit forming surface that is located in the sealing body. A first semiconductor chip having a first surface and a second surface opposite to the first surface and supported on one surface of the tab via an adhesive; and a first surface of the first semiconductor chip. A plurality of electrode pads formed on a peripheral edge, a conductive wire that electrically connects the electrode pads and the leads, a first surface that is a circuit formation surface, and a second surface opposite to the first surface; A second semiconductor chip stacked on the first surface of the first semiconductor chip, and a plurality of electrode pads formed on the first surface of the second semiconductor chip and the leads. Having electrically conductive wires to be connected to each other.

前記タブは枠状に形成されており、前記第１の半導体チップは、その第１の面の電極パッドよりも内側で前記タブの一面と接着しており、前記第２の半導体チップは前記枠状のタブの開口部の内側に配置している。前記第１の半導体チップと前記第２の半導体チップは、それぞれの第１の面に形成された電極パッドのいくつかが前記導電性のワイヤにより互いに接続、または、前記枠状のタブに前記導電性のワイヤにより接続されているものである。   The tab is formed in a frame shape, the first semiconductor chip is bonded to one surface of the tab inside the electrode pad on the first surface, and the second semiconductor chip is connected to the frame. It is arranged inside the opening of the tab. In the first semiconductor chip and the second semiconductor chip, some of the electrode pads formed on the respective first surfaces are connected to each other by the conductive wires, or the conductive material is connected to the frame-shaped tab. It is connected by a sex wire.

（３）絶縁性樹脂からなる封止体と、第１の面およびその反対側の第２の面を有し半導体チップを支持するタブと、前記封止体の実装面に一面を露出する複数のリードと、前記封止体内に位置し、回路形成面である第１の面およびその反対側の第２の面を有し、前記タブの一面に接着剤を介して支持される第１の半導体チップと、前記第１の半導体チップの第１の面の周縁部に形成された複数の電極パッドと前記リードとを電気的に接続する導電性のワイヤとを有する半導体装置であって、回路形成面である第１の面およびその反対側の第２の面を有する第２の半導体チップを有し、前記第２の半導体チップの第２の面は前記タブの第１の面に接着されており、前記第２の半導体チップの第１の面に形成された複数の電極パッドと前記リードとが導電性のワイヤにより電気的に接続され、前記第１の半導体チップは、前記タブの第２の面と接着しており、前記タブおよび前記第２の半導体チップは第１の半導体チップの第１の面の電極パッドよりも内側に有るものである。   (3) A sealing body made of an insulating resin, a tab having a first surface and a second surface opposite to the first surface, and supporting a semiconductor chip, and a plurality of one surface exposed on the mounting surface of the sealing body A first surface which is located in the sealing body and which is a circuit forming surface and a second surface opposite to the first surface, and is supported on one surface of the tab via an adhesive. A semiconductor device comprising: a semiconductor chip; a plurality of electrode pads formed on a peripheral portion of a first surface of the first semiconductor chip; and a conductive wire that electrically connects the lead. A second semiconductor chip having a first surface that is a formation surface and a second surface opposite to the first surface; and the second surface of the second semiconductor chip is bonded to the first surface of the tab. A plurality of electrode pads formed on the first surface of the second semiconductor chip and the leads. Are electrically connected by a conductive wire, the first semiconductor chip is bonded to the second surface of the tab, and the tab and the second semiconductor chip are the first semiconductor chip's second ones. 1 on the inner side of the electrode pad on the first surface.

前記第１の半導体チップと前記第２の半導体チップは、それぞれの第１の面に形成された電極パッドのいくつかが前記導電性のワイヤにより互いに接続、または前記タブに前記導電性のワイヤにより接続されているものである。   In the first semiconductor chip and the second semiconductor chip, some of the electrode pads formed on the respective first surfaces are connected to each other by the conductive wires, or the tabs are connected by the conductive wires. It is connected.

１つのパッケージの中にチップを積層して搭載するマルチチップパッケージ型半導体装置において、リードフレームを用いたノンリード型のパッケージの形態を採用することで、実装高さ縮小および実装面積縮小、軽量化が可能となり、さらに、従来設備を活用するため、低コストで実現することができる。また、ＬＳＩチップを積層するにあたって、チップサイズや電極パッド配置の制限が少なく、既存のＬＳＩチップを流用し組み合わせて使用できる。さらに積層された２つのＬＳＩチップ間の電気的接続において、タブあるいはＬＳＩチップの電極パッドを，内部で中継端子代わりに利用でき，リード引き回し時の汎用性が向上する。   In a multi-chip package type semiconductor device in which chips are stacked and mounted in a single package, adopting a non-lead type package form using a lead frame reduces the mounting height, mounting area, and weight. Furthermore, since conventional equipment is used, it can be realized at low cost. Further, when stacking LSI chips, there are few restrictions on the chip size and electrode pad arrangement, and existing LSI chips can be diverted and used in combination. Further, in the electrical connection between two stacked LSI chips, the tab or the electrode pad of the LSI chip can be used instead of the relay terminal internally, and the versatility at the time of lead routing is improved.

以下、本発明の実施の形態を図面に基づいて詳細に説明する。なお、実施の形態を説明するための全図において、同一の機能を有する部材には同一の符号を付し、その繰り返しの説明は省略する。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

（実施の形態１）
図１は本発明の実施の形態１の半導体装置の構造の一例を示す断面図、図２は図１に示す半導体装置の構造を示す平面図、図３は図１に示す半導体装置の構造を示す底面図（実装面）、図４は図１に示す半導体装置の組立に用いられるリードフレームの構造の一例を示す平面図、図５は図４に示すリードフレームの構造の一例を示す断面図、図６は図１に示す半導体装置の組立における第１の半導体チップのダイボンディング後の構造の一例を示す断面図、図７は図１に示す半導体装置の組立における第２の半導体チップのダイボンディング後の構造の一例を示す断面図、図８は図１に示す半導体装置の組立におけるワイヤボンディング後の構造の一例を示す断面図、図９は図１に示す半導体装置の組立におけるモールド状態の構造の一例を示す断面図、図１０は図１に示す半導体装置の組立における外装めっき状態の構造の一例を示す断面図、図１１は図１に示す半導体装置の組立におけるダイシング状態の構造の一例を示す断面図、図１2は図１に示す半導体装置の組立におけるダイシング後の構造の一例を示す断面図、図１3は図１に示す半導体装置の実装における基板実装後の構造の一例を示す断面図である。 (Embodiment 1)
1 is a cross-sectional view showing an example of the structure of the semiconductor device according to the first embodiment of the present invention, FIG. 2 is a plan view showing the structure of the semiconductor device shown in FIG. 1, and FIG. 3 shows the structure of the semiconductor device shown in FIG. 4 is a plan view showing an example of the structure of a lead frame used for assembling the semiconductor device shown in FIG. 1, and FIG. 5 is a cross-sectional view showing an example of the structure of the lead frame shown in FIG. 6 is a sectional view showing an example of a structure after die bonding of the first semiconductor chip in the assembly of the semiconductor device shown in FIG. 1, and FIG. 7 is a die of the second semiconductor chip in the assembly of the semiconductor device shown in FIG. FIG. 8 is a cross-sectional view showing an example of the structure after wire bonding in the assembly of the semiconductor device shown in FIG. 1, and FIG. 9 is a mold state in the assembly of the semiconductor device shown in FIG. Example of structure FIG. 10 is a cross-sectional view showing an example of the structure of the exterior plating state in the assembly of the semiconductor device shown in FIG. 1, and FIG. 11 is a cross-sectional view showing an example of the structure of the dicing state in the assembly of the semiconductor device shown in FIG. 12 is a sectional view showing an example of the structure after dicing in the assembly of the semiconductor device shown in FIG. 1, and FIG. 13 is a sectional view showing an example of the structure after mounting on the substrate in the mounting of the semiconductor device shown in FIG.

図１〜図3に示す半導体装置は、樹脂封止型で、かつリードフレームを用いた面実装型の半導体パッケージであり、本実施の形態1ではこの半導体装置の一例として、タブ露出型の半導体装置６を取上げて説明する。   The semiconductor device shown in FIGS. 1 to 3 is a resin-encapsulated and surface-mounted semiconductor package using a lead frame. In the first embodiment, a tab-exposed semiconductor is used as an example of the semiconductor device. The device 6 will be explained.

半導体装置６は、図1に示すように、第1の半導体チップ2は、タブ1e（チップ搭載部）上に例えば、銀ペーストや接着フィルムのような導電性ダイボンド材8ａを介して、回路形成面である第1の面と反対側の第２の面で接着、支持され、その第1の面には第2の半導体チップ3が、例えば、シリコーンゴムや絶縁シート等の絶縁性ダイボンド材8ｂを介して、第２の面で積層搭載されており、金線のような導電性ワイヤ５によりそれぞれの半導体チップの複数の電極パッド２ａおよび３ａと複数のリード1ａとがそれぞれ結線されている。   As shown in FIG. 1, in the semiconductor device 6, the first semiconductor chip 2 is formed on the tab 1e (chip mounting portion) via a conductive die bond material 8a such as a silver paste or an adhesive film. The second semiconductor chip 3 is bonded and supported on the second surface opposite to the first surface, and the second semiconductor chip 3 is formed on the first surface by an insulating die bond material 8b such as silicone rubber or an insulating sheet. The plurality of electrode pads 2a and 3a of each semiconductor chip and the plurality of leads 1a are respectively connected by a conductive wire 5 such as a gold wire.

この際、第２の半導体チップ３周縁部の電極パッドは、第１の半導体チップ２周縁部の電極パッドの内側に有るため、導電性ワイヤ５によりそれぞれの半導体チップの複数の電極パッド２ａおよび３ａと複数のリード1ａの結線が容易にできる。   At this time, since the electrode pads on the periphery of the second semiconductor chip 3 are inside the electrode pads on the periphery of the first semiconductor chip 2, the plurality of electrode pads 2 a and 3 a of each semiconductor chip are formed by the conductive wire 5. The plurality of leads 1a can be easily connected.

第２の半導体チップ３の複数電極パッド３ａには、予め金等からなるバンプ３bを例えばワイヤバンプを形成する要領で形成しておき、ワイヤボンディングはリード１ａ側、或いは第１の半導体チップ２側を先にワイヤー５に形成した金ボール（先端）を用いてボンディングし（以下ファーストボンディング）、その後、バンプ３bにワイヤー５のテール（末端）をボンディング（以下セカンドボンディング）することによりバンプ３b上のワイヤ５の角度がほぼ水平になるため、ワイヤの高さを低く抑えることができ、半導体チップを積層した場合でも半導体装置６の薄型化を図ることができる。   A bump 3b made of gold or the like is formed in advance on the plurality of electrode pads 3a of the second semiconductor chip 3 in the manner of forming a wire bump, for example, and wire bonding is performed on the lead 1a side or the first semiconductor chip 2 side. Bonding is performed using a gold ball (tip) formed on the wire 5 first (hereinafter referred to as “first bonding”), and then the tail (terminal) of the wire 5 is bonded to the bump 3b (hereinafter referred to as “second bonding”). Since the angle 5 is substantially horizontal, the height of the wire can be kept low, and the semiconductor device 6 can be thinned even when semiconductor chips are stacked.

第１の半導体チップ２の電極パッド２ａ側はファーストボンディング、リード１ｄ側はセカンドボンディングにより接続されており、更に第１の半導体チップ２とタブ１ｅも同様にワイヤボンディングされており、タブ１ｅ及びタブ吊りリード１ｇとが実装面４ａから露出したタブ露出構造のものである。   The electrode pad 2a side of the first semiconductor chip 2 is connected by first bonding, the lead 1d side is connected by second bonding, and the first semiconductor chip 2 and the tab 1e are similarly wire-bonded. The suspension lead 1g has a tab exposure structure in which the mounting surface 4a is exposed.

また、封止樹脂部４を形成する樹脂は、例えば、熱硬化性のエポキシ樹脂等である。   Moreover, resin which forms the sealing resin part 4 is a thermosetting epoxy resin etc., for example.

なお、半導体装置６は、ひとつの封止樹脂体に複数の装置領域が封止され、その半導体封止樹脂部を装置領域ごとにダイシングにより切断、個片化される方法（一括モールド）により組立てられたものである。   The semiconductor device 6 is assembled by a method (batch molding) in which a plurality of device regions are sealed in one sealing resin body, and the semiconductor sealing resin portion is cut by dicing for each device region. It is what was done.

次に、本実施の形態１の半導体装置６の製造方法について説明する。   Next, a method for manufacturing the semiconductor device 6 according to the first embodiment will be described.

まず、図４に示すような第１の枠部である外枠部１ｈと、外枠部１ｈの内側に形成された第２の枠部である内枠部１ｊと、内枠部１ｊの内側に形成された複数の装置領域であるデバイス領域１ｋと、複数のデバイス領域１ｋのそれぞれに形成された複数の電極部分であるリード１ａと、複数のデバイス領域１ｋのそれぞれに形成された複数のチップ搭載部であるタブ１ｅとを有するリードフレーム１を準備する。   First, as shown in FIG. 4, the outer frame portion 1h, which is the first frame portion, the inner frame portion 1j, which is the second frame portion formed inside the outer frame portion 1h, and the inner side of the inner frame portion 1j. A plurality of device regions formed in the device region 1k, a plurality of electrode portions formed in each of the plurality of device regions 1k, and a plurality of chips formed in each of the plurality of device regions 1k. A lead frame 1 having a tab 1e as a mounting portion is prepared.

次に、図６に示すように、リードフレーム１の複数のデバイス領域１ｋのそれぞれのタブ１ｅ上に、それぞれが複数の電極パッド２ａを有する複数の第１の半導体チップ２を、銀ペーストや接着フィルムのような導電性ダイボンド材８ａを介してその回路形成面である第1の面と反対側の第２の面で接着、支持する（ダイボンディング）。   Next, as shown in FIG. 6, a plurality of first semiconductor chips 2 each having a plurality of electrode pads 2a are attached to each tab 1e of a plurality of device regions 1k of the lead frame 1 by silver paste or bonding. It is bonded and supported on a second surface opposite to the first surface, which is the circuit forming surface, through a conductive die bond material 8a such as a film (die bonding).

次に、図７に示すようにシリコーンゴムや絶縁シート等の絶縁性ダイボンド材８bを介して第２の半導体チップ３を第１の半導体チップ２の第1の面に、その回路形成面である第1の面と反対側の第２の面で接着、支持する。   Next, as shown in FIG. 7, the second semiconductor chip 3 is formed on the first surface of the first semiconductor chip 2 via the insulating die-bonding material 8 b such as silicone rubber or an insulating sheet, which is a circuit forming surface thereof. Adhere and support on the second surface opposite to the first surface.

次に、図８に示すように、金線等の導電性ワイヤ５により、第１の半導体チップ２の複数の電極パッド２ａと複数のリードフレーム1ｄ、或いはタブ１ｅとを、或いは第２の半導体チップ３のいくつかの電極パッド３ａとを接続する。更に、第２の半導体チップ３の複数の電極パッド３ａと複数のリードフレーム1ｄとを、或いはタブ１ｅとを接続する（ワイヤボンディング）。この場合、第２の半導体チップ３の電極パッド３ａには、予め金等からなるバンプを例えばワイヤバンプを形成する要領で形成しておく。ワイヤボンディングはリード側１ａ、或いは第１の半導体チップ２側をファーストボンディング、バンプ側をセカンドボンディングとし、セカンドボンディングはバンプに対して行う。   Next, as shown in FIG. 8, a plurality of electrode pads 2a and a plurality of lead frames 1d or tabs 1e of the first semiconductor chip 2 are connected by a conductive wire 5 such as a gold wire, or a second semiconductor. Several electrode pads 3a of the chip 3 are connected. Further, the plurality of electrode pads 3a of the second semiconductor chip 3 and the plurality of lead frames 1d or the tab 1e are connected (wire bonding). In this case, bumps made of gold or the like are previously formed on the electrode pads 3a of the second semiconductor chip 3 in the manner of forming wire bumps, for example. In the wire bonding, the lead side 1a or the first semiconductor chip 2 side is first bonding, the bump side is second bonding, and the second bonding is performed on the bump.

次に、図９に示すように、複数の第１の半導体チップ２、複数の第２の半導体チップ３、複数のワイヤ５、およびリードフレーム１のリード１aやタブ１eの一部をモールド金型１０で覆い、このキャビティ１０cに封止樹脂を充填させる一括モールドを行う。これによって、図１０に示すように、封止樹脂部４が形成される。   Next, as shown in FIG. 9, a plurality of first semiconductor chips 2, a plurality of second semiconductor chips 3, a plurality of wires 5, and a part of leads 1a and tabs 1e of the lead frame 1 are molded. 10 is performed, and batch molding is performed to fill the cavity 10c with a sealing resin. Thereby, as shown in FIG. 10, the sealing resin part 4 is formed.

なお、この場合一括モールドではなく、デバイス領域毎に個別のキャビティで封止する方法も勿論可能である。   In this case, it is of course possible to perform sealing with individual cavities for each device region instead of batch molding.

その後、図１０に示すように、封止樹脂部４の実装面４aに露出した各リード１aの外部接続用端子部１bの表面とタブ１eの表面とに半田によるメッキ膜7を例えば電解メッキ法で形成する。   Thereafter, as shown in FIG. 10, a plating film 7 made of solder is applied to the surface of the external connection terminal portion 1b of each lead 1a and the surface of the tab 1e exposed on the mounting surface 4a of the sealing resin portion 4 by, for example, an electrolytic plating method. Form with.

その後、図１１に示すダイシングブレード９を用いたダイシングによって、各デバイス領域毎に、封止樹脂部４とリードフレーム１を一緒に切断して図１２に示すような個片化を行う。デバイス領域毎に個別のキャビティで封止したものについては、切断刃により個片化する。   Thereafter, the dicing blade 9 shown in FIG. 11 is used for dicing as shown in FIG. 12 by cutting the sealing resin portion 4 and the lead frame 1 together for each device region by dicing using the dicing blade 9. About what was sealed with the individual cavity for every device area | region, it separates into pieces with a cutting blade.

図１３は個片化により完成した半導体装置６の実装基板１１への実装状態の構造を示す一例である。実装基板１１の一面には、前記半導体装置６の外部接続端子となるリード１ｂやタブ１ｅおよびタブ吊りリード１ｇに対応して、電極（ランド）１１ａが設けられている。そして、これらランド１１ａ上に半導体装置６の外部接続端子となるリード１ｂやタブ１ｅおよびタブ吊りリード１ｇが重ねられ、かつ半田等による接合材１２を介して電気的に接続されている。   FIG. 13 shows an example of the structure of the semiconductor device 6 completed by singulation on the mounting substrate 11. On one surface of the mounting substrate 11, electrodes (lands) 11 a are provided corresponding to the leads 1 b, tabs 1 e, and tab suspension leads 1 g serving as external connection terminals of the semiconductor device 6. A lead 1b, a tab 1e, and a tab suspension lead 1g, which are external connection terminals of the semiconductor device 6, are overlaid on the lands 11a, and are electrically connected via a bonding material 12 such as solder.

本実施形態１においては、信頼性を考慮して、タブ表面とパッケージを形成する樹脂（レジン）との接触面積を広くするために、タブ表面はパッケージ内に存在する構成としている。また、放熱性を考慮して、半導体チップで発生する熱を広い面積に亘って伝えるため、タブはチップより大きくし、実装面側に露出する構成としている。   In the first embodiment, in consideration of reliability, the tab surface is present in the package in order to increase the contact area between the tab surface and the resin (resin) forming the package. In consideration of heat dissipation, in order to transmit heat generated in the semiconductor chip over a wide area, the tab is made larger than the chip and exposed to the mounting surface side.

（実施の形態２）
図１４は本発明の実施の形態２の半導体装置の構造の一例を示す断面図、図１５は図１４に示す半導体装置の構造を示す平面図、図１６は図１４に示す半導体装置の構造を示す底面図（実装面）、図１７は図１４に示す半導体装置の組立に用いられるリードフレームの構造の一例を示す平面図、図１８は図１７に示すリードフレームの構造の一例を示す断面図、図１９は図１４に示す半導体装置の組立における第１の半導体チップのダイボンディング後の構造の一例を示す断面図、図２０は図１４に示す半導体装置の組立における第２の半導体チップのダイボンディング後の構造の一例を示す断面図、図２１は図１４に示す半導体装置の組立におけるワイヤボンディング後の構造の一例を示す断面図、図２２は図１４に示す半導体装置の組立におけるモールド状態の構造の一例を示す断面図、図２３は図１４に示す半導体装置の組立における外装めっき状態の構造の一例を示す断面図、図２４は図１４に示す半導体装置の組立におけるリード切断状態の構造の一例を示す断面図、図２５は図１４に示す半導体装置の組立におけるリード切断後の構造の一例を示す断面図、図２６は図１４に示す半導体装置の実装における基板実装後の構造の一例を示す断面図である。 (Embodiment 2)
14 is a cross-sectional view showing an example of the structure of the semiconductor device according to the second embodiment of the present invention, FIG. 15 is a plan view showing the structure of the semiconductor device shown in FIG. 14, and FIG. 16 shows the structure of the semiconductor device shown in FIG. FIG. 17 is a plan view showing an example of the structure of a lead frame used for assembling the semiconductor device shown in FIG. 14, and FIG. 18 is a cross-sectional view showing an example of the structure of the lead frame shown in FIG. 19 is a sectional view showing an example of the structure after die bonding of the first semiconductor chip in the assembly of the semiconductor device shown in FIG. 14, and FIG. 20 is a die of the second semiconductor chip in the assembly of the semiconductor device shown in FIG. FIG. 21 is a sectional view showing an example of the structure after wire bonding in the assembly of the semiconductor device shown in FIG. 14, and FIG. 22 is an assembly of the semiconductor device shown in FIG. FIG. 23 is a cross-sectional view showing an example of the structure of the exterior plating state in the assembly of the semiconductor device shown in FIG. 14, and FIG. 24 is a lead cutting in the assembly of the semiconductor device shown in FIG. FIG. 25 is a cross-sectional view showing an example of the structure after cutting the leads in the assembly of the semiconductor device shown in FIG. 14, and FIG. 26 is a cross-sectional view after mounting the substrate in the mounting of the semiconductor device shown in FIG. It is sectional drawing which shows an example of a structure.

図１４〜図１６に示す半導体装置は、樹脂封止型で、かつリードフレームを用いた面実装型の半導体パッケージであり、本実施の形態２ではこの半導体装置の一例として、タブ内蔵型の半導体装置６を取上げて説明する。   The semiconductor device shown in FIGS. 14 to 16 is a resin-encapsulated and surface-mount type semiconductor package using a lead frame. In the second embodiment, as an example of the semiconductor device, a semiconductor with a built-in tab is used. The device 6 will be explained.

半導体装置６は、図1４に示すように、タブ1e（チップ搭載部）上に第1の半導体チップ2が、例えば、銀ペーストや接着フィルムのような導電性ダイボンド材8ａを介してその回路形成面である第1の面と反対側の第２の面で接着、支持され、その第1の面には第2の半導体チップ3が、例えば、シリコーンゴムや絶縁シート等の絶縁性ダイボンド材8ｂを介して積層搭載されており、金線等の導電性ワイヤ５によりそれぞれの半導体チップの複数の電極パッド２ａおよび３ａと複数の複数のリード1ａとがそれぞれ結線されている。   As shown in FIG. 14, in the semiconductor device 6, the first semiconductor chip 2 is formed on a tab 1e (chip mounting portion) through a conductive die bond material 8a such as a silver paste or an adhesive film. The second semiconductor chip 3 is bonded and supported on the second surface opposite to the first surface, and the second semiconductor chip 3 is formed on the first surface by an insulating die bond material 8b such as silicone rubber or an insulating sheet. A plurality of electrode pads 2a and 3a of each semiconductor chip and a plurality of leads 1a are respectively connected by conductive wires 5 such as gold wires.

この際、第２の半導体チップ３周縁部の電極パッドは、第１の半導体チップ２周縁部の電極パッドの内側に有るため、導電性ワイヤ５によりそれぞれの半導体チップの複数の電極パッド２ａおよび３ａと複数の複数のリード1ａの結線が容易にできる。   At this time, since the electrode pads on the periphery of the second semiconductor chip 3 are inside the electrode pads on the periphery of the first semiconductor chip 2, the plurality of electrode pads 2 a and 3 a of each semiconductor chip are formed by the conductive wire 5. The plurality of leads 1a can be easily connected.

第２の半導体チップ３の電極パッド３ａには、予め金等からなるバンプを例えばワイヤバンプを形成する要領で形成しておき、ワイヤボンディングはリード１ａ側、或いは第１の半導体チップ２側を先にワイヤー５に形成した金ボール（先端）を用いてボンディングし（以下ファーストボンディング）、その後、バンプ３bにワイヤー５のテール（末端）をボンディング（以下セカンドボンディング）することによりバンプ３b上のワイヤ５の角度がほぼ水平になるため、ワイヤの高さを低く抑えることができ、半導体チップを積層した場合でも半導体装置６の薄型化を図ることができる。   A bump made of gold or the like is formed in advance on the electrode pad 3a of the second semiconductor chip 3 in the manner of forming a wire bump, for example, and wire bonding is performed on the lead 1a side or the first semiconductor chip 2 side first. Bonding is performed using a gold ball (tip) formed on the wire 5 (hereinafter referred to as “first bonding”), and then the tail (terminal) of the wire 5 is bonded to the bump 3b (hereinafter referred to as “second bonding”). Since the angle is almost horizontal, the height of the wire can be kept low, and the semiconductor device 6 can be thinned even when semiconductor chips are stacked.

第１の半導体チップ２側はファーストボンディング、リード側１ｄはセカンドボンディングにより接続されており、更に第１の半導体チップ２とタブ吊りリード１ｇも同様にワイヤボンディングされており、タブ吊りリード１ｇの一部が底面から露出しており、タブ１ｅは封止樹脂部４に内蔵されている。   The first semiconductor chip 2 side is connected by first bonding, the lead side 1d is connected by second bonding, and the first semiconductor chip 2 and the tab suspension lead 1g are similarly wire-bonded, and one of the tab suspension leads 1g is connected. The part is exposed from the bottom surface, and the tab 1 e is built in the sealing resin part 4.

また、封止樹脂部４を形成する樹脂は、例えば、熱硬化性のエポキシ樹脂等である。   Moreover, resin which forms the sealing resin part 4 is a thermosetting epoxy resin etc., for example.

次に、本実施の形態２の半導体装置６の製造方法について説明する。   Next, a method for manufacturing the semiconductor device 6 according to the second embodiment will be described.

図１７に示すリードフレーム１の準備から、図２０に示すダイボンディング工程までの製造方法は実施の形態１と同様のため省略する。ただし、ここで示すリードフレーム１は図１８に示すように、タブ１ｅは他のリードフレーム面よりも0.1ｍｍ〜0.3ｍｍ程度上がっている。   The manufacturing method from the preparation of the lead frame 1 shown in FIG. 17 to the die bonding step shown in FIG. However, in the lead frame 1 shown here, as shown in FIG. 18, the tab 1e is raised by about 0.1 mm to 0.3 mm from the other lead frame surfaces.

次に、図２１に示すように、金線等の導電性ワイヤ５により、第１の半導体チップ２の複数の電極パッド２ａと複数のリード1ａ、或いは図１５に示したタブ吊りリード１ｇとを、或いは第２の半導体チップ３のいくつかの電極パッド３ａとを接続する。更に、第２の半導体チップ３の複数の電極パッド３ａと複数のリードフレーム1ｄとを接続する。この場合、第２の半導体チップ３の電極パッド３ａには、予め金等からなるバンプを例えばワイヤバンプを形成する要領で形成しておく。ワイヤボンディングはリード１ａ側、或いは第１の半導体チップ２側をファーストボンディング、バンプ３ｂ側をセカンドボンディングとし、セカンドボンディングはバンプ３ｂに対して行う。   Next, as shown in FIG. 21, a plurality of electrode pads 2a and a plurality of leads 1a of the first semiconductor chip 2 or a tab suspension lead 1g shown in FIG. Alternatively, several electrode pads 3a of the second semiconductor chip 3 are connected. Further, the plurality of electrode pads 3a of the second semiconductor chip 3 and the plurality of lead frames 1d are connected. In this case, bumps made of gold or the like are previously formed on the electrode pads 3a of the second semiconductor chip 3 in the manner of forming wire bumps, for example. Wire bonding is the first bonding on the lead 1a side or the first semiconductor chip 2 side, the second bonding is on the bump 3b side, and the second bonding is performed on the bump 3b.

次に、図２２に示すように、複数の第１の半導体チップ２、複数の第２の半導体チップ３、複数のワイヤ５、およびリードフレーム１のリード１aやタブ１eをモールド金型１０で覆い、このキャビティ１０cに封止樹脂を充填させるモールドを行う。これによって、図２３に示すように、樹脂封止体４が形成される。   Next, as shown in FIG. 22, the plurality of first semiconductor chips 2, the plurality of second semiconductor chips 3, the plurality of wires 5, and the leads 1 a and tabs 1 e of the lead frame 1 are covered with a mold 10. Then, a mold for filling the cavity 10c with a sealing resin is performed. Thereby, as shown in FIG. 23, the resin sealing body 4 is formed.

ここでのモールド金型１０は、図２２に示すように、複数の装置領域であるデバイス領域１ｋ毎にキャビティが分割された形状をしており、実施の形態１の一括モールドとは異なる。   As shown in FIG. 22, the mold 10 here has a shape in which a cavity is divided for each device region 1k, which is a plurality of device regions, and is different from the collective mold of the first embodiment.

次に、図２３に示すように、樹脂封止体４の裏面４aに露出した各リード１aの外部接続用端子部１bの表面に半田によるメッキ膜7を例えば電解メッキ法で形成する。   Next, as shown in FIG. 23, a plating film 7 made of solder is formed on the surface of the external connection terminal portion 1b of each lead 1a exposed on the back surface 4a of the resin sealing body 4 by, for example, an electrolytic plating method.

次に、図２４に示すように、複数の装置領域であるデバイス領域１ｋ以外のリードフレーム１を切断刃１３により切断して図２５に示すような個片化を行う。   Next, as shown in FIG. 24, the lead frame 1 other than the device region 1k, which is a plurality of device regions, is cut by the cutting blade 13 to be singulated as shown in FIG.

図２６は個片化により完成した半導体装置６の実装基板１１への実装状態の構造を示す一例である。実装基板１１の一面には、前記半導体装置６の外部接続端子となるリード１ｂやタブ吊りリード１ｇに対応して、ランド（最上層配線）１１ａが設けられている。そして、これらランド１１ａ上に半導体装置６の外部接続端子となるリード１ｂやタブ吊りリード１ｇが重ねられ、かつ半田等による接合材１２を介して電気的に接続されている。   FIG. 26 shows an example of the structure of the semiconductor device 6 completed by singulation on the mounting substrate 11. On one surface of the mounting substrate 11, lands (uppermost layer wiring) 11 a are provided corresponding to the leads 1 b and the tab suspension leads 1 g serving as external connection terminals of the semiconductor device 6. A lead 1b and a tab suspension lead 1g, which are external connection terminals of the semiconductor device 6, are overlaid on the lands 11a, and are electrically connected via a bonding material 12 such as solder.

本実施形態２においては、信頼性を考慮して、タブ裏面はパッケージ内に存在する構成としている。また、信頼性および搭載チップサイズの汎用性を考慮して、タブはチップより小さくした。このため、半導体装置６の外部接続端子となるリード１ｂやタブ吊りリード１ｇの一部を除いた領域は封止樹脂で覆われている。   In the second embodiment, in consideration of reliability, the rear surface of the tab is configured to exist in the package. In consideration of reliability and versatility of mounted chip size, the tab was made smaller than the chip. For this reason, the area | region except the lead 1b used as the external connection terminal of the semiconductor device 6 and a part of tab suspension lead 1g is covered with sealing resin.

これにより、図２６に示すように、半導体装置６を実装する実装基板１１において、外部接続端子となるリード１ｂやタブ吊りリード１ｇの一部を除いた領域の下の領域にも最上層配線１１ａ（実装用ランドと同層の配線）を形成することができ、実装性の向上を図ることができる。   As a result, as shown in FIG. 26, in the mounting substrate 11 on which the semiconductor device 6 is mounted, the uppermost layer wiring 11a is also formed in a region below the region excluding a part of the lead 1b serving as the external connection terminal and the tab suspension lead 1g. (Wiring in the same layer as the mounting land) can be formed, and the mountability can be improved.

つまり、実施の形態１で説明した半導体装置６の場合、実装基板１１においてタブ１ｅの下に最上層配線１１ａ（特に信号配線）を配置すると、タブ１ｅを介して第１の半導体チップ２が配線からのノイズを拾ってしまうため、タブ１ｅの下に実装基板１１の最上層配線１１ａを配置するのが困難である。   That is, in the case of the semiconductor device 6 described in the first embodiment, when the uppermost layer wiring 11a (especially signal wiring) is arranged below the tab 1e on the mounting substrate 11, the first semiconductor chip 2 is wired via the tab 1e. Therefore, it is difficult to dispose the uppermost layer wiring 11a of the mounting substrate 11 under the tab 1e.

したがって、本実施の形態２の半導体装置６によれば、タブ１ｅの裏面（実装面側）に絶縁性の封止樹脂が存在するため、タブ１ｅの裏面の絶縁を確保でき、実装基板１１の最上層配線１１ａからのノイズの影響を軽減できる。これにより、図２６に示すように、第１の半導体チップ２およびタブ１ｅの直下でも実装基板１１に信号配線等の最上層配線１１ａを配置することができる。   Therefore, according to the semiconductor device 6 of the second embodiment, since the insulating sealing resin exists on the back surface (mounting surface side) of the tab 1e, it is possible to ensure insulation of the back surface of the tab 1e, and The influence of noise from the uppermost layer wiring 11a can be reduced. Thereby, as shown in FIG. 26, the uppermost layer wiring 11a such as the signal wiring can be arranged on the mounting substrate 11 even immediately below the first semiconductor chip 2 and the tab 1e.

その結果、実装基板１１において配線密度を高めることができ、実装基板１１の小型化を図ることができる。ここで実装基板１１には、内部配線１１ｂが形成され、この内部配線１１ｂはビアホール配線１１ｃを介して最上層配線１１ａと接続されており、さらに、半田１２を介して半導体装置６のリード１ａが最上層配線１１ａと接続されている。また、最上層配線１１ａは、ソルダレジスト膜１１ｄによってその一部が覆われている。   As a result, the wiring density in the mounting substrate 11 can be increased, and the mounting substrate 11 can be reduced in size. Here, an internal wiring 11 b is formed on the mounting substrate 11, and the internal wiring 11 b is connected to the uppermost layer wiring 11 a through the via hole wiring 11 c, and further, the lead 1 a of the semiconductor device 6 is connected through the solder 12. It is connected to the uppermost layer wiring 11a. Further, a part of the uppermost layer wiring 11a is covered with a solder resist film 11d.

（実施の形態３）
図２７は本発明の実施の形態３の半導体装置の構造の一例を示す断面図、図２８は図２７に示す半導体装置６の構造を示す平面図である。 (Embodiment 3)
27 is a sectional view showing an example of the structure of the semiconductor device according to the third embodiment of the present invention, and FIG. 28 is a plan view showing the structure of the semiconductor device 6 shown in FIG.

図２７〜図２８に示す半導体装置は、樹脂封止型で、かつリードフレームを用いた面実装型の半導体パッケージであり、本実施の形態３ではこの半導体装置の一例として、半導体装置６を取上げて説明する。   The semiconductor device shown in FIGS. 27 to 28 is a resin-encapsulated and surface-mounted semiconductor package using a lead frame. In the third embodiment, the semiconductor device 6 is taken up as an example of the semiconductor device. I will explain.

半導体装置６は、図２７に示すように、第1の半導体チップ2は、枠状のタブ１e（チップ搭載部）の一面に例えば、シリコーンゴムや絶縁シート等を介して回路形成面である第1の面で支持され、その第1の面に第2の半導体チップ3が、例えば、シリコーンゴムや絶縁シート等の絶縁性ダイボンド材8ｂを介して第1の面と反対側の第２の面で積層搭載されており、金線等の導電性ワイヤ５によりそれぞれの半導体チップの複数の電極パッド２ａおよび３ａと複数のリード1ａとがそれぞれ結線されている。   As shown in FIG. 27, the semiconductor device 6 has a first semiconductor chip 2 which is a circuit forming surface on one surface of a frame-like tab 1e (chip mounting portion) via, for example, silicone rubber or an insulating sheet. The second semiconductor chip 3 is supported on the first surface, and the second surface is opposite to the first surface via an insulating die bond material 8b such as silicone rubber or an insulating sheet. The plurality of electrode pads 2a and 3a of each semiconductor chip and the plurality of leads 1a are respectively connected by conductive wires 5 such as gold wires.

この際、第２の半導体チップ３は、枠状のタブ１eの開口部に配置させる。さらに、第１の半導体チップ２の電極パッドは枠状のタブ１eの外側に配置させるため、導電性ワイヤ５によりそれぞれの半導体チップの複数の電極パッド２ａおよび３ａと複数のリード1ａおよび枠状のタブ１eの結線が容易にできる。   At this time, the second semiconductor chip 3 is disposed in the opening of the frame-like tab 1e. Further, since the electrode pads of the first semiconductor chip 2 are arranged outside the frame-shaped tab 1e, the plurality of electrode pads 2a and 3a of each semiconductor chip, the plurality of leads 1a and the frame-like shape are formed by the conductive wire 5. The tab 1e can be easily connected.

第２の半導体チップ３の電極パッド３ａには、予め金等からなるバンプを例えばワイヤバンプを形成する要領で形成しておき、ワイヤボンディングはリード１ａ側、或いは第１の半導体チップ２側を先にワイヤー５に形成した金ボール（先端）を用いてボンディングし（以下ファーストボンディング）、その後、バンプ３bにワイヤー５のテール（末端）をボンディング（以下セカンドボンディング）することによりバンプ３b上のワイヤ５の角度がほぼ水平になるため、ワイヤの高さを低く抑えることができ、半導体チップを積層した場合でも半導体装置６の薄型化を図ることができる。   A bump made of gold or the like is formed in advance on the electrode pad 3a of the second semiconductor chip 3 in the manner of forming a wire bump, for example, and wire bonding is performed on the lead 1a side or the first semiconductor chip 2 side first. Bonding is performed using a gold ball (tip) formed on the wire 5 (hereinafter referred to as “first bonding”), and then the tail (terminal) of the wire 5 is bonded to the bump 3b (hereinafter referred to as “second bonding”). Since the angle is almost horizontal, the height of the wire can be kept low, and the semiconductor device 6 can be thinned even when semiconductor chips are stacked.

第１の半導体チップ２側はファーストボンディング、リード１ａ側はセカンドボンディングにより接続されており、更に第１の半導体チップ２とタブ吊りリード１ｇも同様にワイヤボンディングされており、タブ吊りリード１ｇの一部が実装面から露出しており、タブ１ｅは樹脂封止体４に内蔵されている。   The first semiconductor chip 2 side is connected by first bonding, and the lead 1a side is connected by second bonding. Further, the first semiconductor chip 2 and the tab suspension lead 1g are similarly wire-bonded, and one of the tab suspension leads 1g is connected. The part is exposed from the mounting surface, and the tab 1 e is built in the resin sealing body 4.

なお、本実施の形態３は、枠状のタブ１eの一面に第1の半導体チップ2を配置し、第２の半導体チップ３を枠状のタブ１eの開口部に配置するため、それぞれの半導体チップ搭載後の高さにおいて、タブ１eの厚みに影響を受けることなく、半導体装置６の薄型化を図ることができる。   In the third embodiment, the first semiconductor chip 2 is disposed on one surface of the frame-shaped tab 1e, and the second semiconductor chip 3 is disposed in the opening of the frame-shaped tab 1e. The thickness of the semiconductor device 6 can be reduced without being affected by the thickness of the tab 1e at the height after chip mounting.

次に、本実施の形態３の半導体装置６の製造方法について説明する。   Next, a method for manufacturing the semiconductor device 6 according to the third embodiment will be described.

基本的な製造方法は実施の形態２と同様であるが、以下の点が異なる。   The basic manufacturing method is the same as that of the second embodiment except for the following points.

ここで使用するリードフレームは、実施の形態２の図１７に示したものと基本的に同様であるが、図２８に示すように、タブ１ｅの内側をくり抜いており、枠状となっている点である。   The lead frame used here is basically the same as that shown in FIG. 17 of the second embodiment. However, as shown in FIG. 28, the inside of the tab 1e is hollowed out to have a frame shape. Is a point.

（１）さらに、ダイボンディング工程においては、図２７に示すように、タブ１eの一面に第1の半導体チップ2を支持するため、例えば、シリコーンゴムや絶縁性シート等8ｂをタブ１ｅの裏面に予め貼り付けておき、第1の半導体チップ2とタブ１ｅを位置合わせ後、接着する。   (1) Further, in the die bonding process, as shown in FIG. 27, in order to support the first semiconductor chip 2 on one surface of the tab 1e, for example, silicone rubber, an insulating sheet or the like 8b is provided on the back surface of the tab 1e. The first semiconductor chip 2 and the tab 1e are aligned and bonded together in advance.

（２）次に、第1の半導体チップ2の回路形成面である第1の面に第2の半導体チップ3を、例えば、絶縁性のシリコーンゴムや絶縁性シート等の絶縁性ダイボンド材8ｂを介して支持する。なお、（１）に先がけて、（２）を実施し、その後（１）を実施してもよい。   (2) Next, the second semiconductor chip 3 is placed on the first surface, which is the circuit forming surface of the first semiconductor chip 2, and the insulating die-bonding material 8b such as insulating silicone rubber or insulating sheet, for example. Support through. Note that (2) may be performed prior to (1), and then (1) may be performed.

次に、図２７に示すように、金線等の導電性ワイヤ５により、第１の半導体チップ２の複数の電極パッド２ａと複数のリード1ａ、或いはタブ１ｅとを或いは第２の半導体チップ３のいくつかの電極パッド３ａとを接続する。更に、第２の半導体チップ３の複数の電極パッド３ａと複数の複数のリード1ａとを、或いはタブ１ｅとを接続する。この場合、第２の半導体チップ３の電極パッド３ａには、予め金等からなるバンプを例えばワイヤバンプを形成する要領で形成しておく。ワイヤボンディングはリード側１ａ、或いは第１の半導体チップ側２をファーストボンディング、バンプ側をセカンドボンディングとし、セカンドボンディングはバンプに対して行う。   Next, as shown in FIG. 27, the plurality of electrode pads 2a and the plurality of leads 1a or tabs 1e of the first semiconductor chip 2 or the second semiconductor chip 3 are formed by a conductive wire 5 such as a gold wire. Are connected to several electrode pads 3a. Further, the plurality of electrode pads 3a and the plurality of leads 1a of the second semiconductor chip 3 or the tab 1e are connected. In this case, bumps made of gold or the like are previously formed on the electrode pads 3a of the second semiconductor chip 3 in the manner of forming wire bumps, for example. In the wire bonding, the lead side 1a or the first semiconductor chip side 2 is first bonding, the bump side is second bonding, and the second bonding is performed on the bump.

以後、モールド工程〜切断工程における製造方法及び実装方法については、実施の形態２と同様である。   Thereafter, the manufacturing method and the mounting method in the molding process to the cutting process are the same as those in the second embodiment.

図２９〜図３０に示す半導体装置は、実施の形態３における変形例を示したもので、第２の半導体チップ３の第２の面が半導体装置６の実装面４ａに露出した構成である。図２９は実施の形態３における変形例を示す断面図、図２９の平面図は図２８と同様、図３０は図２９の半導体装置の構造を示す底面図（実装面）である。本構成を用いた場合、他の実施の形態と比較し最も半導体装置の薄型化を図ることが可能となる。   The semiconductor device shown in FIG. 29 to FIG. 30 shows a modification of the third embodiment, and has a configuration in which the second surface of the second semiconductor chip 3 is exposed on the mounting surface 4a of the semiconductor device 6. 29 is a cross-sectional view showing a modification of the third embodiment, the plan view of FIG. 29 is the same as FIG. 28, and FIG. 30 is a bottom view (mounting surface) showing the structure of the semiconductor device of FIG. When this structure is used, the semiconductor device can be most thinned as compared with other embodiments.

（実施の形態４）
図３１は本発明の実施の形態４の半導体装置の構造の一例を示す断面図、図３２は図３１に示す半導体装置６の構造を示す平面図である。 (Embodiment 4)
31 is a sectional view showing an example of the structure of the semiconductor device according to the fourth embodiment of the present invention, and FIG. 32 is a plan view showing the structure of the semiconductor device 6 shown in FIG.

図３１〜図３３に示す半導体装置は、樹脂封止型で、かつ面実装型のリードフレームを用いた半導体パッケージであり、本実施の形態４ではこの半導体装置の一例として、半導体装置６を取上げて説明する。   The semiconductor device shown in FIGS. 31 to 33 is a semiconductor package using a resin-encapsulated and surface-mount type lead frame. In the fourth embodiment, the semiconductor device 6 is taken up as an example of the semiconductor device. I will explain.

半導体装置６は、図３１に示すように、タブ１eの一方の面に第1の半導体チップ2が、例えば、絶縁性のシリコーンゴムや絶縁シート等8ｂを介して支持され、タブ１eの他方の面に第2の半導体チップ3が、例えば、銀ペーストや接着フィルムのような導電性ダイボンド材8ａを介して積層搭載されており、金線等の導電性ワイヤ５によりそれぞれの半導体チップの複数の電極パッド２ａおよび３ａと複数の複数のリード1ａとがそれぞれ結線されている。   In the semiconductor device 6, as shown in FIG. 31, the first semiconductor chip 2 is supported on one surface of the tab 1e via, for example, an insulating silicone rubber or an insulating sheet 8b, and the other side of the tab 1e. A second semiconductor chip 3 is laminated and mounted on the surface via a conductive die bond material 8a such as a silver paste or an adhesive film, and a plurality of each semiconductor chip is connected by a conductive wire 5 such as a gold wire. The electrode pads 2a and 3a are connected to a plurality of leads 1a.

この際、第２の半導体チップ３は、タブ１eの内側に有り、さらに、第１の半導体チップ２周縁部の電極パッドはタブ１eの外側に有るため、導電性ワイヤ５によりそれぞれの半導体チップの複数の電極と複数の複数のリード1ａおよびタブ１eの結線が容易にできる。   At this time, the second semiconductor chip 3 is inside the tab 1e, and the electrode pads on the periphery of the first semiconductor chip 2 are outside the tab 1e. A plurality of electrodes and a plurality of leads 1a and tabs 1e can be easily connected.

第２の半導体チップ３の複数の電極パッド３ａと複数の複数のリード1ａとを、或いはタブ１ｅとを接続する。この場合、第２の半導体チップ３の電極パッド３ａには、予め金等からなるバンプを例えばワイヤバンプを形成する要領で形成しておく。ワイヤボンディングはリード１ａ側、或いは第１の半導体チップ２側を先にワイヤー５に形成した金ボール（先端）を用いてボンディングし（以下ファーストボンディング）、その後、バンプ３bにワイヤー５のテール（末端）をボンディング（以下セカンドボンディング）することによりバンプ３b上のワイヤ５の角度がほぼ水平になるため、ワイヤの高さを低く抑えることができ、半導体チップを積層した場合でも半導体装置６の薄型化を図ることができる。   The plurality of electrode pads 3a of the second semiconductor chip 3 and the plurality of leads 1a or the tab 1e are connected. In this case, bumps made of gold or the like are previously formed on the electrode pads 3a of the second semiconductor chip 3 in the manner of forming wire bumps, for example. Wire bonding is performed by using a gold ball (front end) formed on the wire 5 on the lead 1a side or the first semiconductor chip 2 side first (hereinafter referred to as first bonding), and then on the bump 3b on the tail (terminal) of the wire 5. ) Is bonded (hereinafter referred to as second bonding), the angle of the wire 5 on the bump 3b becomes almost horizontal, so that the height of the wire can be kept low, and the semiconductor device 6 can be made thinner even when semiconductor chips are stacked. Can be achieved.

第１の半導体チップ２側はファーストボンディング、リード１ａ側はセカンドボンディングにより接続されており、更に第１の半導体チップ２とタブ吊りリード１ｇも同様にワイヤボンディングされており、タブ吊りリード１ｇの一部が実装面から露出しており、第１の半導体チップ２は樹脂封止体４に内蔵されている。   The first semiconductor chip 2 side is connected by first bonding, and the lead 1a side is connected by second bonding. Further, the first semiconductor chip 2 and the tab suspension lead 1g are similarly wire-bonded, and one of the tab suspension leads 1g is connected. The part is exposed from the mounting surface, and the first semiconductor chip 2 is built in the resin sealing body 4.

次に、本実施の形態４の半導体装置６の製造方法について説明する。   Next, a method for manufacturing the semiconductor device 6 according to the fourth embodiment will be described.

基本的な製造方法は実施の形態２と同様であるが、以下の点が異なる。   The basic manufacturing method is the same as that of the second embodiment except for the following points.

（１）ダイボンディング工程においては、図３１に示すように、タブ１eの一面に第1の半導体チップ2を支持するため、例えば、シリコーンゴムや絶縁性の熱硬化性接着テープ等をタブ１ｅの一方の面に予め貼り付けておき、第1の半導体チップ2とタブ１ｅを位置合わせ後、接着する。   (1) In the die bonding step, as shown in FIG. 31, in order to support the first semiconductor chip 2 on one surface of the tab 1e, for example, silicone rubber or an insulating thermosetting adhesive tape is attached to the tab 1e. The first semiconductor chip 2 and the tab 1e are aligned and bonded to each other in advance.

（２）次に、タブ１ｅの他方の面に第2の半導体チップ3を、例えば、銀ペーストや接着フィルムのような導電性ダイボンド材8ａを介して支持する。なお、（１）に先がけて、（２）を実施し、その後（１）を実施してもよい。   (2) Next, the second semiconductor chip 3 is supported on the other surface of the tab 1e via a conductive die bond material 8a such as a silver paste or an adhesive film. Note that (2) may be performed prior to (1), and then (1) may be performed.

次に、図３１に示すように、金線等の導電性ワイヤ５により、第１の半導体チップ２の複数の電極パッド２ａと複数のリードフレーム1ｄ、或いはタブ１ｅとを或いは第２の半導体チップ３のいくつかの電極パッド３ａとを接続する。更に、第２の半導体チップ３の複数の電極パッド３ａと複数のリード1ａとを、或いはタブ１ｅとを接続する。この場合、第２の半導体チップ３の電極パッド３ａには、予め金等からなるバンプを例えばワイヤバンプを形成する要領で形成しておく。ワイヤボンディングはリード側１ａ、或いは第１の半導体チップ側２をファーストボンディング、バンプ側をセカンドボンディングとし、セカンドボンディングはバンプに対して行う。   Next, as shown in FIG. 31, a plurality of electrode pads 2a and a plurality of lead frames 1d or tabs 1e of the first semiconductor chip 2 or a second semiconductor chip are formed by a conductive wire 5 such as a gold wire. 3 is connected to several electrode pads 3a. Further, the plurality of electrode pads 3a and the plurality of leads 1a of the second semiconductor chip 3 or the tab 1e are connected. In this case, bumps made of gold or the like are previously formed on the electrode pads 3a of the second semiconductor chip 3 in the manner of forming wire bumps, for example. In the wire bonding, the lead side 1a or the first semiconductor chip side 2 is first bonding, the bump side is second bonding, and the second bonding is performed on the bump.

以後、モールド工程〜切断工程の製造方法及び実装方法については、実施の形態２と同様である。   Thereafter, the manufacturing method and the mounting method in the molding process to the cutting process are the same as those in the second embodiment.

図３３に示す半導体装置は、実施の形態４における変形例を示したもので、第２の半導体チップ３の第２の面が半導体装置６の実装面４ａに露出した構成である。図３３は実施の形態４における変形例を示す断面図、図３３の平面図は図３２と同様、図３３の半導体装置の構造を示す底面図（実装面）は図３０と同様である。   The semiconductor device shown in FIG. 33 is a modification of the fourth embodiment, and has a configuration in which the second surface of the second semiconductor chip 3 is exposed on the mounting surface 4 a of the semiconductor device 6. 33 is a cross-sectional view showing a modification of the fourth embodiment, the plan view of FIG. 33 is the same as FIG. 32, and the bottom view (mounting surface) showing the structure of the semiconductor device of FIG. 33 is the same as FIG.

次に、前記発明の実施の形態におけるワイヤボンディングレイアウトの変形例を図３４〜図３７に示す。図３４は半導体装置における第１の半導体チップ２にマイコン、第２の半導体チップ３にＳＲＡＭを積層した場合の半導体装置の平面図、図３５は外部接続端子が２辺配置の半導体装置における一例を示しており、第１の半導体チップ２にフラッシュマイコン、第２の半導体チップ３にＤＲＡＭを積層した場合の半導体装置の平面図、図３６は半導体装置における第１の半導体チップ２にフラッシュマイコン、第２の半導体チップ３にＤＲＡＭを積層した場合の半導体装置の平面図、図３７は半導体装置における第１の半導体チップ２にマイコン、第２、第３の半導体チップにＳＲＡＭを２ケ積層した場合の半導体装置の平面図を示したものである。   Next, modified examples of the wire bonding layout in the embodiment of the present invention are shown in FIGS. FIG. 34 is a plan view of a semiconductor device in which a microcomputer is stacked on the first semiconductor chip 2 and an SRAM is stacked on the second semiconductor chip 3 in the semiconductor device, and FIG. 35 is an example of the semiconductor device in which the external connection terminals are arranged on two sides. FIG. 36 is a plan view of a semiconductor device in which a flash microcomputer is stacked on the first semiconductor chip 2 and a DRAM is stacked on the second semiconductor chip 3. FIG. 36 is a diagram showing a flash microcomputer on the first semiconductor chip 2 in the semiconductor device. FIG. 37 is a plan view of a semiconductor device when DRAMs are stacked on the semiconductor chip 3 of FIG. 2, and FIG. 37 shows a case where a microcomputer is stacked on the first semiconductor chip 2 and two SRAMs are stacked on the second and third semiconductor chips. 1 is a plan view of a semiconductor device.

図３８〜３９はマルチチップモジュールに前記発明の実施の形態を実装した状態を示しており、図３８はその構造の一例を示した断面図、図３９はその構造の一例を示した平面図である。フリップチップと共に基板上に実装されており、基板上での実装面積の縮小、かつ実装高さ低減を図ることができる。   38 to 39 show a state in which the embodiment of the present invention is mounted on a multichip module. FIG. 38 is a sectional view showing an example of the structure, and FIG. 39 is a plan view showing an example of the structure. is there. It is mounted on the substrate together with the flip chip, so that the mounting area on the substrate can be reduced and the mounting height can be reduced.

以上、発明の実施の形態に基づき具体的に説明したが、本発明は上記の実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることは言うまでもない。   Although the present invention has been specifically described above based on the embodiments of the present invention, it is needless to say that the present invention is not limited to the above-described embodiments and can be variously modified without departing from the gist thereof.

例えば、前記発明の実施の形態では、主に外部接続端子が４辺配置の半導体装置の製造に関して本発明を適用した例について説明してきたが、例えば外部接続端子が２辺配置の半導体装置の製造に関しても本発明を同様に適用でき、同様の効果を得ることができる。   For example, in the embodiment of the present invention, the example in which the present invention is applied mainly to the manufacture of a semiconductor device having four sides of external connection terminals has been described. For example, the manufacture of a semiconductor device having two sides of external connection terminals is described. The present invention can be applied in the same manner and the same effects can be obtained.

本発明の実施の形態１の半導体装置の構造の一例を示す断面図である。It is sectional drawing which shows an example of the structure of the semiconductor device of Embodiment 1 of this invention. 図１に示す半導体装置の構造を示す平面図である。FIG. 2 is a plan view showing the structure of the semiconductor device shown in FIG. 1. 図１に示す半導体装置の構造を示す底面図（実装面）である。FIG. 2 is a bottom view (mounting surface) illustrating the structure of the semiconductor device illustrated in FIG. 1. 図１に示す半導体装置の組立に用いられるリードフレームの構造の一例を示す平面図である。FIG. 2 is a plan view showing an example of the structure of a lead frame used for assembling the semiconductor device shown in FIG. 1. 図４に示すリードフレームの構造の一例を示す断面図である。FIG. 5 is a cross-sectional view showing an example of the structure of the lead frame shown in FIG. 4. 図１に示す半導体装置の組立における第１の半導体チップのダイボンディング後の構造の一例を示す断面図である。FIG. 2 is a cross-sectional view showing an example of a structure after die bonding of a first semiconductor chip in the assembly of the semiconductor device shown in FIG. 1. 図１に示す半導体装置の組立における第２の半導体チップのダイボンディング後の構造の一例を示す断面図である。It is sectional drawing which shows an example of the structure after the die bonding of the 2nd semiconductor chip in the assembly of the semiconductor device shown in FIG. 図１に示す半導体装置の組立におけるワイヤボンディング後の構造の一例を示す断面図である。It is sectional drawing which shows an example of the structure after the wire bonding in the assembly of the semiconductor device shown in FIG. 図１に示す半導体装置の組立におけるモールド状態の構造の一例を示す断面図である。It is sectional drawing which shows an example of the structure of the mold state in the assembly of the semiconductor device shown in FIG. 図１に示す半導体装置の組立における外装めっき状態の構造の一例を示す断面図である。It is sectional drawing which shows an example of the structure of the exterior plating state in the assembly of the semiconductor device shown in FIG. 図１に示す半導体装置の組立におけるダイシング状態の構造の一例を示す断面図である。FIG. 2 is a cross-sectional view showing an example of a dicing state structure in the assembly of the semiconductor device shown in FIG. 1. 図１に示す半導体装置の組立におけるダイシング後の構造の一例を示す断面図である。It is sectional drawing which shows an example of the structure after the dicing in the assembly of the semiconductor device shown in FIG. 図１に示す半導体装置の実装における基板実装後の構造の一例を示す断面図である。It is sectional drawing which shows an example of the structure after the board | substrate mounting in mounting of the semiconductor device shown in FIG. 本発明の実施の形態２の半導体装置の構造の一例を示す断面図である。It is sectional drawing which shows an example of the structure of the semiconductor device of Embodiment 2 of this invention. 図１４に示す半導体装置の構造を示す平面図14 is a plan view showing the structure of the semiconductor device shown in FIG. 図１４に示す半導体装置の構造を示す底面図（実装面）14 is a bottom view (mounting surface) showing the structure of the semiconductor device shown in FIG. 図１４に示す半導体装置の組立に用いられるリードフレームの構造の一例を示す平面図である。FIG. 15 is a plan view showing an example of the structure of a lead frame used for assembling the semiconductor device shown in FIG. 14. 図１７に示すリードフレームの構造の一例を示す断面図である。FIG. 18 is a cross-sectional view showing an example of the structure of the lead frame shown in FIG. 17. 図１４に示す半導体装置の組立における第１の半導体チップのダイボンディング後の構造の一例を示す断面図である。FIG. 15 is a cross-sectional view showing an example of a structure after die bonding of a first semiconductor chip in the assembly of the semiconductor device shown in FIG. 14. 図１４に示す半導体装置の組立における第２の半導体チップのダイボンディング後の構造の一例を示す断面図である。FIG. 15 is a cross-sectional view showing an example of a structure after die bonding of a second semiconductor chip in the assembly of the semiconductor device shown in FIG. 14. 図１４に示す半導体装置の組立におけるワイヤボンディング後の構造の一例を示す断面図である。It is sectional drawing which shows an example of the structure after the wire bonding in the assembly of the semiconductor device shown in FIG. 図１４に示す半導体装置の組立におけるモールド状態の構造の一例を示す断面図である。It is sectional drawing which shows an example of the structure of the mold state in the assembly of the semiconductor device shown in FIG. 図１４に示す半導体装置の組立における外装めっき状態の構造の一例を示す断面図である。It is sectional drawing which shows an example of the structure of the exterior plating state in the assembly of the semiconductor device shown in FIG. 図１４に示す半導体装置の組立におけるリード切断状態の構造の一例を示す断面図である。FIG. 15 is a cross-sectional view illustrating an example of a structure of a lead cut state in the assembly of the semiconductor device illustrated in FIG. 14. 図１４に示す半導体装置の組立におけるリード切断後の構造の一例を示す断面図である。FIG. 15 is a cross-sectional view showing an example of a structure after cutting a lead in the assembly of the semiconductor device shown in FIG. 14. 図１４に示す半導体装置の実装における基板実装後の構造の一例を示す断面図である。It is sectional drawing which shows an example of the structure after the board | substrate mounting in the mounting of the semiconductor device shown in FIG. 本発明の実施の形態３の半導体装置の構造の一例を示す断面図である。It is sectional drawing which shows an example of the structure of the semiconductor device of Embodiment 3 of this invention. 図２７に示す実施の形態３の半導体装置の構造を示す平面図である。FIG. 28 is a plan view showing the structure of the semiconductor device of the third embodiment shown in FIG. 27. 実施の形態３における変形例を示す断面図である。FIG. 11 is a cross-sectional view showing a modification example in the third embodiment. 図２９の半導体装置の構造を示す底面図（実装面）である。FIG. 30 is a bottom view (mounting surface) showing the structure of the semiconductor device of FIG. 29; 本発明の実施の形態４の半導体装置の構造の一例を示す断面図である。It is sectional drawing which shows an example of the structure of the semiconductor device of Embodiment 4 of this invention. 図３１に示す実施の形態４の半導体装置の構造を示す平面図である。FIG. 32 is a plan view showing the structure of the semiconductor device of the fourth embodiment shown in FIG. 31. 図３１に示す実施の形態４における変形例を示す断面図である。FIG. 32 is a cross-sectional view showing a modification of the fourth embodiment shown in FIG. 31. 半導体装置における第１の半導体チップ２にマイコン、第２の半導体チップ３にＳＲＡＭを積層した場合の半導体装置の平面図である。FIG. 3 is a plan view of a semiconductor device when a microcomputer is stacked on a first semiconductor chip 2 and an SRAM is stacked on a second semiconductor chip 3 in the semiconductor device. 外部接続端子が２辺配置の半導体装置における一例を示しており、第１の半導体チップ２にフラッシュマイコン、第２の半導体チップ３にＤＲＡＭを積層した場合の半導体装置の平面図である。1 is a plan view of a semiconductor device in which a flash microcomputer is stacked on a first semiconductor chip 2 and a DRAM is stacked on a second semiconductor chip 3, showing an example of a semiconductor device having two sides of external connection terminals. 半導体装置における第１の半導体チップ２にフラッシュマイコン、第２の半導体チップ３にＤＲＡＭを積層した場合の半導体装置の平面図である。FIG. 3 is a plan view of a semiconductor device when a flash microcomputer is stacked on a first semiconductor chip 2 and a DRAM is stacked on a second semiconductor chip 3 in the semiconductor device. 半導体装置における第１の半導体チップ２にマイコン、第２、第３の半導体チップにＳＲＡＭを２ケ積層した場合の半導体装置の平面図である。FIG. 3 is a plan view of a semiconductor device when a microcomputer is stacked on a first semiconductor chip 2 and two SRAMs are stacked on a second and third semiconductor chip in the semiconductor device. マルチチップモジュールに半導体装置を実装した状態の断面図である。It is sectional drawing of the state which mounted the semiconductor device in the multichip module. マルチチップモジュールに半導体装置を実装した状態の平面図である。It is a top view of the state which mounted the semiconductor device in the multichip module. 従来の半導体装置型半導体装置の構造の一例を示す断面図である。It is sectional drawing which shows an example of the structure of the conventional semiconductor device type semiconductor device. 図３９に示す半導体装置の構造を示す平面図である。FIG. 40 is a plan view showing the structure of the semiconductor device shown in FIG. 39.

符号の説明Explanation of symbols

１ リードフレーム
１ａ リード（電極部分）
１ｂ 外部接続用端子部
１ｄ ボンディング部
１ｅ タブ（チップ搭載部）
１ｇ タブ吊りリード
１ｈ 外枠部（第１の枠部）
１ｊ 内枠部（第２の枠部）
１ｋ デバイス領域（装置領域）
２ 第１の半導体チップ
２ａ 第１の電極パッド
３ 第２の半導体チップ
３ａ 第２の電極パッド
３ｂ バンプ
４ 樹脂封止体
４ａ 裏面（実装面）
４ｂ 側面
５ ワイヤ
６ 半導体装置
７ めっき膜
８ａ ダイボンド材（導電性）
８ｂ ダイボンド材（絶縁性）
９ ダイシングブレード
１０ モールド金型
１０ａ 上型
１０ｂ 下型
１０ｃ キャビティ
１１ 実装基板
１１ａ ランドおよび最上層配線
１１ｂ ビアホール
１１ｃ ビアホール配線
１２ 半田（接合材）
１３ 切断刃（カッター）
１４ フリップチップ
１５ マルチチップモジュール基板。 1 Lead frame 1a Lead (electrode part)
1b External connection terminal part 1d Bonding part 1e Tab (chip mounting part)
1g Tab suspension lead 1h Outer frame (first frame)
1j Inner frame (second frame)
1k device area (equipment area)
2 1st semiconductor chip 2a 1st electrode pad 3 2nd semiconductor chip 3a 2nd electrode pad 3b Bump 4 Resin sealing body 4a Back surface (mounting surface)
4b Side surface 5 Wire 6 Semiconductor device 7 Plating film 8a Die bond material (conductive)
8b Die bond material (insulating)
9 Dicing blade 10 Mold die 10a Upper die 10b Lower die 10c Cavity 11 Mounting substrate 11a Land and uppermost layer wiring 11b Via hole 11c Via hole wiring 12 Solder (bonding material)
13 Cutting blade (cutter)
14 Flip chip 15 Multi-chip module substrate.

Claims (2)

複数の第１電極パッドが形成された第１の面と、前記第１の面と反対側の第２の面とを有する第１の半導体チップと、
前記第１の半導体チップの外形寸法よりも大きく、前記第１の半導体チップの第２の面を接着剤を介して支持するタブと、
前記タブの周囲に配置された複数のリードと、
前記第１の半導体チップの外形寸法よりも小さく、複数の第２電極パッドが形成された第３の面と、前記第３の面と反対側の第４の面とを有し、前記第４の面と前記第１の半導体チップの第１の面とが対向するように、前記第１の半導体チップの第１の面上に搭載された第２の半導体チップと、
前記第１の半導体チップの複数の第１電極パッドのうちのリード用パッドと前記複数のリードのうちの第１半導体チップ用リードとを電気的に接続する導電性の第１ワイヤと、
前記第２の半導体チップの複数の第２電極パッドのうちのリード用パッドと前記複数のリードのうちの第２半導体チップ用リードとを電気的に接続する導電性の第２ワイヤと、
前記第１の半導体チップの複数の第１電極パッドのうちのタブ用パッドと前記タブとを電気的に接続する導電性の第３ワイヤと、
前記第１の半導体チップの複数の第１電極パッドのうちの第２半導体チップ用パッドと前記第２の半導体チップの複数の第２電極パッドのうちの第１半導体チップ用パッドとを電気的に接続する導電性の第４ワイヤと、
前記第１の半導体チップ、前記第２の半導体チップ、前記導電性の第１ワイヤ、前記導電性の第２ワイヤ、前記導電性の第３ワイヤ、前記導電性の第４ワイヤ、および前記複数のリードを封止する封止体と、を含み、
前記複数のリードのそれぞれの一部は、前記封止体の実装面および側面から露出しており、
前記タブは前記封止体の実装面に一面を露出しており、
前記タブと一体に形成された複数のタブ吊りリードのそれぞれの一部は、前記封止体の実装面から露出していることを特徴とする半導体装置。 A first semiconductor chip having a first surface on which a plurality of first electrode pads are formed, and a second surface opposite to the first surface;
A tab that is larger than the outer dimension of the first semiconductor chip and supports the second surface of the first semiconductor chip via an adhesive;
A plurality of leads disposed around the tab;
A fourth surface that is smaller than the outer dimension of the first semiconductor chip and on which a plurality of second electrode pads are formed; and a fourth surface opposite to the third surface; A second semiconductor chip mounted on the first surface of the first semiconductor chip such that the surface of the first semiconductor chip faces the first surface of the first semiconductor chip;
A conductive first wire for electrically connecting a lead pad of the plurality of first electrode pads of the first semiconductor chip and a lead for the first semiconductor chip of the plurality of leads;
A conductive second wire that electrically connects a lead pad of the plurality of second electrode pads of the second semiconductor chip and a second semiconductor chip lead of the plurality of leads;
A conductive third wire for electrically connecting the tab pad of the plurality of first electrode pads of the first semiconductor chip and the tab;
The second semiconductor chip pad of the plurality of first electrode pads of the first semiconductor chip and the first semiconductor chip pad of the plurality of second electrode pads of the second semiconductor chip are electrically connected. A conductive fourth wire to connect;
Said first semiconductor chip, the second semiconductor chip, before Kishirube conductivity of the first wire, said conductive second wire, said conductive third wire, said conductive fourth wire, Oyo anda sealing member for sealing the fine said plurality of leads,
A part of each of the plurality of leads is exposed from the mounting surface and the side surface of the sealing body,
The tab is exposed on the mounting surface of the sealing body,
A part of each of the plurality of tab suspension leads formed integrally with the tab is exposed from the mounting surface of the sealing body. 請求項１記載の半導体装置であって、前記第１の半導体チップはマイコンチップであり、前記第２の半導体チップはメモリチップであることを特徴とする半導体装置。   2. The semiconductor device according to claim 1, wherein the first semiconductor chip is a microcomputer chip, and the second semiconductor chip is a memory chip.
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