KR20070100028A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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KR20070100028A
KR20070100028A KR1020060031559A KR20060031559A KR20070100028A KR 20070100028 A KR20070100028 A KR 20070100028A KR 1020060031559 A KR1020060031559 A KR 1020060031559A KR 20060031559 A KR20060031559 A KR 20060031559A KR 20070100028 A KR20070100028 A KR 20070100028A
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South Korea
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substrate
gate
groove
forming
insulating film
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KR1020060031559A
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Korean (ko)
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강효영
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주식회사 하이닉스반도체
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Priority to KR1020060031559A priority Critical patent/KR20070100028A/en
Publication of KR20070100028A publication Critical patent/KR20070100028A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate

Abstract

A method for manufacturing a semiconductor device is provided to anneal source/drain regions before implanting threshold voltage ions to improve short channel effect due to impurity diffusion. A method for manufacturing a semiconductor device includes a gate insulating layer(19), a gate conduction layer(20), and a recess gate(21). The gate insulating layer(19) is formed on a surface of a groove(H) after removing a screen insulating layer on the groove. The gate conduction layer(20) is formed on the gate insulating layer to bury the groove. The recess gate(21) is formed to bury the groove on a substrate(11) by performing a chemical vapor deposition on the gate insulating layer to expose source/drain regions(16). An annealing process is performed on the source/drain regions before implanting threshold voltage adjustment ions to form a screen insulating layer on the gate groove.

Description

반도체 소자의 제조방법{METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE}Manufacturing method of semiconductor device {METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE}

도 1a 내지 도 1e는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정별 단면도.1A to 1E are cross-sectional views illustrating processes for manufacturing a semiconductor device in accordance with an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

11 : 반도체 기판 12 : 소자분리막11 semiconductor substrate 12 device isolation film

13 : 희생게이트 14 : LDD 영역13: sacrificial gate 14: LDD region

15 : 스페이서 H : 홈15: spacer H: groove

16 : 소오스/드레인 영역 17 : 스크린절연막16 source / drain region 17 screen insulating film

18 : 문턱전압 이온주입층 19 : 게이트절연막18: threshold voltage ion implantation layer 19: gate insulating film

20 : 게이트도전막 21 : 매몰게이트20: gate conductive film 21: investment gate

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히, 단채널효과(Short Channel Effect)와 오프 커런트(Off Current)를 효과적으로 개선하여 소자 특성을 향상시킬 수 있는 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device that can improve device characteristics by effectively improving short channel effects and off current.

반도체 소자의 고집적화가 진행됨에 따라 트랜지스터의 채널 길이(Channel Length)는 감소하고 있고, 접합 영역(소오스/드레인 영역)으로의 이온주입 농도는 증가하고 있는 추세이다. 이로 인하여, 접합 영역(소오스/드레인 영역) 간의 간섭(Charge Sharing) 현상이 증가하고 게이트의 제어능력이 저하되어 문턱 전압(Threshold Voltage : Vt)이 급격히 낮아지는 이른바 단채널효과(Short Channel Effect)가 발생한다.As semiconductor devices are highly integrated, channel lengths of transistors are decreasing, and ion implantation concentrations into junction regions (source / drain regions) are increasing. As a result, the so-called short channel effect, in which the interference sharing between the junction regions (source / drain regions) increases, the gate control ability decreases, and the threshold voltage (Vt) decreases rapidly, Occurs.

한편, 상기 단채널효과는 소오스/드레인 영역의 형성 전에 LDD(Lightly Doped Drain)영역을 형성해 줌으로써 어느 정도 개선이 가능하지만, 소자의 고집적화에 따라 채널 길이가 감소될수록 상기 단채널효과는 더욱 심화되고 있다. 이에, 상기 단채널효과를 효과적으로 개선시켜 소자 특성을 향상시키기 위한 다양한 아이디어 및 실제 공정개발 연구가 활발히 진행되고 있다.On the other hand, the short channel effect can be improved to some extent by forming a lightly doped drain (LDD) region before the source / drain region is formed, but the short channel effect is intensified as the channel length decreases due to high integration of devices. . Accordingly, various ideas and actual process development researches are being actively conducted to effectively improve the short channel effect to improve device characteristics.

이를 위한 종래기술로는, 반도체 기판 상에 게이트 및 스페이서를 형성하고, 상기 게이트를 이용하여 자기-정렬(Self-Align) 방식으로 소오스/드레인 영역을 형성하는 방법이 제안된 바 있다. 그러나, 전술한 종래기술에서는 문턱전압 이온주입 공정 후, 소오스/드레인 영역에 어닐링(Anealing)을 수행하므로 불순물 확산에 의한 단채널효과가 심화된다는 문제점이 있다.In the related art, a method of forming a gate and a spacer on a semiconductor substrate and forming a source / drain region in a self-aligning manner using the gate has been proposed. However, in the above-described prior art, since annealing is performed on the source / drain regions after the threshold voltage ion implantation process, there is a problem in that a short channel effect due to impurity diffusion is intensified.

또한, 상기 문턱전압 이온주입시 목표 깊이(projected range : Rp)가 크며, 이에 따라, 채널 영역 표면의 농도 저하로 인하여 오프 커런트가 유발된다. 예컨데, 65nm급 이하 소자의 적용시 오프 커런트를 감소시키기 위해 문턱전압 이온주입시 불순물의 농도를 증가시켜야 하는데, 종래의 방법으로는 상기 농도를 증가시키는 것이 어려우며, 이로 인하여, 소자 특성 저하가 야기된다는 문제점이 있다.In addition, when the threshold voltage ion implantation, a projected range Rp is large, and thus, an off current is caused due to a decrease in the concentration of the channel region surface. For example, in order to reduce off current when applying a device of 65 nm or less, it is necessary to increase the concentration of impurities during implantation of threshold voltages, which is difficult to increase by the conventional method, which leads to deterioration of device characteristics. There is a problem.

따라서, 본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로서, 단채널효과(Short Channel Effect)와 오프 커런트(Off Current)를 효과적으로 개선하여 소자 특성을 향상시킬 수 있는 반도체 소자의 제조방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above problems, and provides a method for manufacturing a semiconductor device that can improve the device characteristics by effectively improving the short channel effect (Off Short Current) and the off current (Off Current). Has its purpose.

상기와 같은 목적을 달성하기 위한 본 발명의 반도체 소자의 제조방법은, 희생게이트가 형성된 반도체 기판을 제공하는 단계; 상기 희생게이트 양측의 기판 표면 내에 LDD 영역을 형성하는 단계; 상기 희생게이트의 양측벽에 스페이서를 형성하는 단계; 상기 스페이서가 형성된 기판 결과물에 대해 소오스/드레인 이온주입을 수행하는 단계; 상기 소오스/드레인 이온주입이 수행된 기판 결과물에 대해 어닐링을 수행해서 스페이서를 포함한 희생게이트 양측의 기판 표면 내에 소오스/드레인 영역을 형성하는 단계; 상기 기판 상에 희생게이트를 덮도록 층간절연막을 형성하는 단계; 상기 층간절연막과 희생게이트 및 기판을 식각하여 상기 희생게이트를 제거함과 아울러 기판 표면에 홈을 형성하는 단계; 상기 층간절연막과 스페이서를 제거하는 단계; 상기 홈 저면에 문턱전압 조절 이온주입 영역을 형성하는 단계; 상기 홈 표면에 게이트절연막을 형성하는 단계; 및 상기 게이트절연막 상에 홈을 매립하는 형태로 매몰게이트를 형성하는 단계;를 포함한다.The semiconductor device manufacturing method of the present invention for achieving the above object comprises the steps of: providing a semiconductor substrate having a sacrificial gate; Forming an LDD region in the substrate surface on both sides of the sacrificial gate; Forming spacers on both side walls of the sacrificial gate; Performing source / drain ion implantation on the substrate product on which the spacer is formed; Annealing the resultant substrate on which the source / drain ion implantation has been performed to form source / drain regions in the substrate surface on both sides of the sacrificial gate including spacers; Forming an interlayer insulating film on the substrate to cover the sacrificial gate; Etching the interlayer insulating layer, the sacrificial gate and the substrate to remove the sacrificial gate and to form grooves on the surface of the substrate; Removing the interlayer insulating film and the spacer; Forming a threshold voltage control ion implantation region on a bottom surface of the groove; Forming a gate insulating film on the groove surface; And forming a buried gate in a form of filling a groove on the gate insulating layer.

여기서, 상기 층간절연막 및 스페이서를 제거하는 단계는 CMP 공정으로 수행한다.Here, the step of removing the interlayer insulating film and the spacer is performed by a CMP process.

상기 홈은 상기 희생게이트를 리버스 마스크로 사용하여 형성한다.The groove is formed using the sacrificial gate as a reverse mask.

상기 홈 저면에 문턱전압 조절 이온주입 영역을 형성하는 단계는, 상기 홈을 포함한 기판 표면 상에 스크린절연막을 형성하는 단계; 상기 스크린절연막이 형성된 기판 결과물에 대해 문턱전압 조절 이온주입을 수행하는 단계; 및 상기 스크린절연막을 제거하는 단계;를 포함하여 이루어진다.The forming of the threshold voltage control ion implantation region on the bottom of the groove may include forming a screen insulating film on a surface of the substrate including the groove; Performing threshold voltage control ion implantation on a substrate resultant on which the screen insulating film is formed; And removing the screen insulating film.

상기 문턱전압 조절 이온주입은 1∼150Å 범위의 깊이로 수행한다.The threshold voltage control ion implantation is performed at a depth in the range of 1 to 150 mA.

상기 스크린절연막은 30∼70Å의 두께로 형성한다.The screen insulating film is formed to a thickness of 30 to 70Å.

(실시예)(Example)

이하, 첨부된 도면에 의거하여 본 발명의 실시예를 상세하게 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

먼저, 본 발명의 기술적 원리를 간략하게 설명하면, 본 발명은 문턱전압 조절 이온주입을 수행하기 전에 소오스/드레인 영역에 어닐링(Anealing)을 수행한다. 이렇게 하면, 불순물 확산에 의한 단채널효과를 효과적으로 개선할 수 있으며, 이를 통해, 반도체 소자의 특성을 향상시킬 수 있다.First, the technical principle of the present invention will be briefly described. The present invention performs annealing on the source / drain regions before performing the threshold voltage control ion implantation. In this way, the short channel effect due to impurity diffusion can be effectively improved, and through this, the characteristics of the semiconductor device can be improved.

자세하게, 도 1a 내지 도 1e는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정별 단면도로서, 이를 설명하면 다음과 같다.1A to 1E are cross-sectional views illustrating processes for manufacturing a semiconductor device according to an embodiment of the present invention, which will be described below.

도 1a를 참조하면, 액티브 영역을 한정하는 소자분리막(12)과 희생게이트(13)가 구비된 반도체 기판(11) 내에 이온주입 공정을 수행하여 상기 희생게이트(13) 양측의 기판(11) 표면 내에 LDD(Lightly Doped Drain) 영역(14)을 형성한다. 이때, 상기 희생게이트(13)는 기판(11) 상에 폴리사이드막을 형성한 다음, 이 를 식각하여 형성한다.Referring to FIG. 1A, an ion implantation process is performed in a semiconductor substrate 11 including an isolation layer 12 and a sacrificial gate 13 defining an active region, thereby forming a surface of the substrate 11 on both sides of the sacrificial gate 13. Lightly Doped Drain (LDD) regions 14 are formed within. In this case, the sacrificial gate 13 is formed by forming a polyside film on the substrate 11 and then etching it.

여기서, 상기 LDD 영역(14)은 기판(11) 내에 저농도 불순물 이온주입 공정을 수행하여 형성하며, 상기 기판(11)내에 소오스/드레인 영역을 형성하기 전에 LDD 영역(14)을 형성해 줌으로써 단채널효과를 어느 정도 개선할 수 있다.Here, the LDD region 14 is formed by performing a low concentration impurity ion implantation process in the substrate 11, and by forming the LDD region 14 before forming the source / drain region in the substrate 11, a short channel effect. Can be improved to some extent.

도 1b를 참조하면, 상기 희생게이트(13)의 양측벽에 스페이서(15)를 형성하고, 상기 스페이서(15)가 형성된 기판(11) 내에 소오스/드레인 이온주입을 수행한다. 이어서, 상기 소오스/드레인 이온주입이 수행된 기판(11) 결과물에 대해 어닐링을 수행하여 스페이서(15)를 포함한 희생게이트(13) 양측의 기판(11) 표면 내에 소오스/드레인 영역(16)을 형성한다.Referring to FIG. 1B, spacers 15 are formed on both sidewalls of the sacrificial gate 13, and source / drain ion implantation is performed in the substrate 11 on which the spacers 15 are formed. Subsequently, annealing is performed on the resultant of the substrate 11 on which the source / drain ion implantation is performed to form the source / drain region 16 on the surface of the substrate 11 on both sides of the sacrificial gate 13 including the spacer 15. do.

여기서, 상기 기판(11) 내에 문턱전압 조절 이온주입을 수행하기 전에 소오스/드레인 영역(16)에 어닐링을 수행함으로써 불순물 확산에 의한 단채널효과를 효과적으로 개선할 수 있으며, 이를 통해, 반도체 소자의 특성을 향상시킬 수 있다.Here, by annealing the source / drain regions 16 before the threshold voltage control ion implantation is performed in the substrate 11, the short channel effect due to the diffusion of impurities may be effectively improved, and thus, the characteristics of the semiconductor device may be improved. Can improve.

도 1c를 참조하면, 상기 소오스/드레인 영역(16)이 형성된 기판(11) 상에 희생게이트를 덮도록 층간절연막(도시안됨)을 형성한 다음, 상기 층간절연막과 희생게이트 및 기판(11)을 식각하여 상기 희생게이트를 제거함과 아울러 기판(11) 표면에 홈(H)을 형성한다. 이어서, 상기 홈(H)이 형성된 기판(11) 결과물 상에 CMP(Chemical Mechanical Polishing) 공정을 수행하여 상기 층간절연막과 스페이서를 제거한다.Referring to FIG. 1C, an interlayer insulating layer (not shown) is formed on the substrate 11 on which the source / drain regions 16 are formed to cover the sacrificial gate, and then the interlayer insulating layer, the sacrificial gate, and the substrate 11 are formed. By etching, the sacrificial gate is removed and grooves H are formed on the surface of the substrate 11. Subsequently, the interlayer insulating layer and the spacer are removed by performing a chemical mechanical polishing (CMP) process on the substrate 11 on which the grooves H are formed.

도 1d를 참조하면, 상기 홈(H)을 포함한 기판(11) 표면 상에 스크린절연막(17)을 형성한 다음, 상기 스크린절연막(17)이 형성된 기판(11) 결과물에 대해 문턱전압 조절 이온주입을 수행하여 상기 홈(H) 저면에 문턱전압 조절 이온주입 영역(18)을 형성한다.Referring to FIG. 1D, a screen insulating film 17 is formed on a surface of the substrate 11 including the groove H, and then threshold voltage control ion implantation is performed on the resultant of the substrate 11 on which the screen insulating film 17 is formed. The threshold voltage adjusting ion implantation region 18 is formed on the bottom of the groove H.

이때, 상기 스크린절연막(17)은 문턱전압을 조절하기 위한 이온주입시 목표 깊이(Projected Range : Rp)를 감소시키기 위해 형성하는 것이며, 상기 스크린절연막(17)은 30∼70Å, 바람직하게는, 50Å 정도의 두께로 형성한다. 또한, 상기 이온주입은 1∼150Å 정도의 깊이로 수행한다.At this time, the screen insulating film 17 is formed to reduce the target depth (Projected Range: Rp) during ion implantation to adjust the threshold voltage, the screen insulating film 17 is 30 ~ 70Å, preferably, 50Å It is formed to a thickness of about. In addition, the ion implantation is carried out to a depth of about 1 ~ 150Å.

여기서, 상기 스크린절연막(17)을 형성한 다음, 문턱전압 조절 이온주입을 수행함으로써 채널 영역의 표면 농도를 증가시킬 수 있으며, 이를 통해, 온 커런트(On Current)를 유지하면서 오프 커런트(Off Current)를 감소시킬 수 있으므로 반도체 소자의 특성을 향상시킬 수 있다.Here, after forming the screen insulating layer 17, the surface concentration of the channel region may be increased by performing threshold voltage control ion implantation, thereby maintaining off current while maintaining on current. Since it is possible to reduce the characteristics of the semiconductor device can be improved.

도 1e를 참조하면, 상기 홈(H) 상의 스크린절연막을 제거하고 홈(H) 표면에 게이트절연막(19)을 형성한 다음, 상기 게이트절연막(19) 상에 상기 홈(H)을 매립하도록 게이트도전막(20)을 형성한다. 이어서, 상기 게이트도전막(20)을 소오스/드레인 영역(16)이 노출되도록 CMP하여 기판(11) 상에 상기 홈(H)을 매립하는 형태의 매몰게이트(21)를 형성한다.Referring to FIG. 1E, the screen insulation layer on the groove H is removed, the gate insulation layer 19 is formed on the surface of the groove H, and the gate H is buried in the gate insulation layer 19. The conductive film 20 is formed. Subsequently, the gate conductive layer 20 is CMP so that the source / drain regions 16 are exposed to form the buried gate 21 in which the groove H is buried on the substrate 11.

이후, 도시하지는 않았으나, 공지의 후속 공정을 수행하여 본 발명의 반도체 소자를 완성한다.Thereafter, although not shown, the semiconductor device of the present invention is completed by performing a known subsequent process.

여기서, 본 발명은 문턱전압 조절 이온주입을 수행하기 전에 소오스/드레인 영역에 어닐링을 수행함으로써 단채널효과를 효과적으로 개선할 수 있으며, 게이트용 홈 표면에 스크린절연막을 형성함으로써 상기 문턱전압 조절 이온주입시 오프 커런트를 개선할 수 있다.Here, the present invention can effectively improve the short channel effect by annealing the source / drain region before performing the threshold voltage control ion implantation, and by forming a screen insulating film on the gate groove surface, Off current can be improved.

이상, 여기에서는 본 발명을 특정 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다.As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the scope of the following claims is not limited to the scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

이상에서와 같이, 본 발명은 문턱전압 이온주입을 수행하기 전에 소오스/드레인 영역에 어닐링을 수행함으로써 불순물 확산에 의한 단채널효과를 효과적으로 개선할 수 있다.As described above, the present invention can effectively improve the short channel effect due to impurity diffusion by annealing the source / drain regions before performing the threshold voltage ion implantation.

또한, 본 발명은 게이트용 홈 표면 상에 스크린절연막을 형성함으로써 문턱전압 이온주입시 채널 영역의 표면 농도를 증가시켜 오프 커런트가 개선되며, 따라서, 반도체 소자의 특성을 향상시킬 수 있다.In addition, the present invention improves off current by forming a screen insulating film on the gate groove surface, thereby increasing the surface concentration of the channel region during threshold voltage ion implantation, thereby improving the characteristics of the semiconductor device.

Claims (6)

희생게이트가 형성된 반도체 기판을 제공하는 단계;Providing a semiconductor substrate having a sacrificial gate formed thereon; 상기 희생게이트 양측의 기판 표면 내에 LDD 영역을 형성하는 단계;Forming an LDD region in the substrate surface on both sides of the sacrificial gate; 상기 희생게이트의 양측벽에 스페이서를 형성하는 단계;Forming spacers on both side walls of the sacrificial gate; 상기 스페이서가 형성된 기판 결과물에 대해 소오스/드레인 이온주입을 수행하는 단계;Performing source / drain ion implantation on the substrate product on which the spacer is formed; 상기 소오스/드레인 이온주입이 수행된 기판 결과물에 대해 어닐링을 수행해서 스페이서를 포함한 희생게이트 양측의 기판 표면 내에 소오스/드레인 영역을 형성하는 단계;Annealing the resultant substrate on which the source / drain ion implantation has been performed to form source / drain regions in the substrate surface on both sides of the sacrificial gate including spacers; 상기 기판 상에 희생게이트를 덮도록 층간절연막을 형성하는 단계;Forming an interlayer insulating film on the substrate to cover the sacrificial gate; 상기 층간절연막과 희생게이트 및 기판을 식각하여 상기 희생게이트를 제거함과 아울러 기판 표면에 홈을 형성하는 단계;Etching the interlayer insulating layer, the sacrificial gate and the substrate to remove the sacrificial gate and to form grooves on the surface of the substrate; 상기 층간절연막과 스페이서를 제거하는 단계;Removing the interlayer insulating film and the spacer; 상기 홈 저면에 문턱전압 조절 이온주입 영역을 형성하는 단계;Forming a threshold voltage control ion implantation region on a bottom surface of the groove; 상기 홈 표면에 게이트절연막을 형성하는 단계; 및Forming a gate insulating film on the groove surface; And 상기 게이트절연막 상에 홈을 매립하는 형태로 매몰게이트를 형성하는 단계;Forming a buried gate in a form of filling a groove on the gate insulating layer; 를 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.Method of manufacturing a semiconductor device comprising a. 제 1 항에 있어서,The method of claim 1, 상기 층간절연막 및 스페이서를 제거하는 단계는 CMP 공정으로 수행하는 것을 특징으로 하는 반도체 소자의 제조방법.Removing the interlayer insulating film and the spacer is a CMP process. 제 1 항에 있어서,The method of claim 1, 상기 홈은 상기 희생게이트를 리버스 마스크로 사용하여 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.And the groove is formed by using the sacrificial gate as a reverse mask. 제 1 항에 있어서,The method of claim 1, 상기 홈 저면에 문턱전압 조절 이온주입 영역을 형성하는 단계는,Forming a threshold voltage control ion implantation region on the bottom of the groove, 상기 홈을 포함한 기판 표면 상에 스크린절연막을 형성하는 단계;Forming a screen insulating film on a surface of the substrate including the groove; 상기 스크린절연막이 형성된 기판 결과물에 대해 문턱전압 조절 이온주입을 수행하는 단계; 및Performing threshold voltage control ion implantation on a substrate resultant on which the screen insulating film is formed; And 상기 스크린절연막을 제거하는 단계;Removing the screen insulating film; 를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 제조방법.Method for manufacturing a semiconductor device comprising a. 제 4 항에 있어서,The method of claim 4, wherein 상기 문턱전압 조절 이온주입은 1∼150Å 범위의 깊이로 수행하는 것을 특징으로 하는 반도체 소자의 제조방법.The threshold voltage control ion implantation method of manufacturing a semiconductor device, characterized in that performed to a depth in the range of 1 ~ 150Å. 제 4 항에 있어서,The method of claim 4, wherein 상기 스크린절연막은 30∼70Å의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.The screen insulating film is a manufacturing method of a semiconductor device, characterized in that formed to a thickness of 30 ~ 70Å.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100935773B1 (en) * 2007-11-26 2010-01-06 주식회사 동부하이텍 Method for manufacturing of semiconductor device
WO2013165630A1 (en) * 2012-04-30 2013-11-07 International Business Machines Corporation A method of fabricating tunnel transistors with abrupt junctions

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100935773B1 (en) * 2007-11-26 2010-01-06 주식회사 동부하이텍 Method for manufacturing of semiconductor device
WO2013165630A1 (en) * 2012-04-30 2013-11-07 International Business Machines Corporation A method of fabricating tunnel transistors with abrupt junctions
GB2515930A (en) * 2012-04-30 2015-01-07 Ibm A Method of fabricating tunnel transistors with abrupt junctions
GB2515930B (en) * 2012-04-30 2016-03-16 Ibm A Method of fabricating tunnel transistors with abrupt junctions
US10103226B2 (en) 2012-04-30 2018-10-16 International Business Machines Corporation Method of fabricating tunnel transistors with abrupt junctions
US10236344B2 (en) 2012-04-30 2019-03-19 International Business Machines Corporation Tunnel transistors with abrupt junctions

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