KR20070099810A - Lcd and drive method thereof - Google Patents

Abstract

An LCD device and a driving method thereof are provided to enhance image quality of an LCD panel by supplying gate pulses to first and last gate lines at the same time. An LCD(Liquid Crystal Display) device includes an LCD panel having plural gate lines, a gate driver(210) and a timing controller(220). The gate driver supplies gate pulses to first and last gate lines at the same time. The timing controller controls the gate driver to generate the gate pulses. The gate driver includes first to n-th driving cells(211-1-211-n), and first and second auxiliary driving cells(212,213). The first to n-th driving cells, which are connected to respective gate lines, supply the gate pulses. The first and second auxiliary driving cells supply the gate pulses to the first and last gate lines, respectively.

Description

Liquid crystal display device and driving method thereof

1 is an equivalent circuit diagram of a pixel formed in a general liquid crystal display device.

2 is a block diagram of a conventional liquid crystal display device.

3 is a block diagram of a liquid crystal display device according to an embodiment of the present invention.

FIG. 4 is a circuit diagram of the first to nth driving cells and the first and second auxiliary driving cells in FIG. 3. FIG.

<Description of Symbols for Main Parts of Drawings>

100 and 200: liquid crystal display device 110: liquid crystal display panel

120: data driver 130, 210: gate driver

150: backlight assembly 160: inverter

170: common voltage generator 180: gate driving voltage generator

190, 220: timing controller

211-1 to 211-n: first to nth drive cells

212 and 213: first and second auxiliary drive cells

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a driving method thereof capable of compensating signal characteristics of a gate line degraded by static electricity or the like.

The liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal cells according to the video signal, and the active matrix type liquid crystal display device in which the switching elements are formed for each liquid crystal cell enables active control of the switching elements. This is advantageous for video implementation. As a switching device used in the active matrix liquid crystal display device, a thin film transistor (hereinafter, referred to as TFT) is mainly used as shown in FIG. 1.

Referring to FIG. 1, an active matrix type liquid crystal display device converts digital input data into an analog data voltage based on a gamma reference voltage and supplies it to the data line DL and simultaneously supplies gate pulses to the gate line GL. The liquid crystal cell Clc is charged.

The gate electrode of the TFT is connected to the gate line GL, the source electrode is connected to the data line DL, and the drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell Clc and one electrode of the storage capacitor Cst. Connected.

The common voltage Vcom is supplied to the common electrode of the liquid crystal cell Clc.

The storage capacitor Cst charges a data voltage applied from the data line DL when the TFT is turned on, thereby maintaining a constant voltage of the liquid crystal cell Clc.

When the gate pulse is applied to the gate line GL, the TFT is turned on to form a channel between the source electrode and the drain electrode so that the voltage on the data line DL is applied to the pixel electrode of the liquid crystal cell Clc. Supply. At this time, the liquid crystal molecules of the liquid crystal cell Clc modulate the incident light by changing the arrangement by the electric field between the pixel electrode and the common electrode.

A configuration of a conventional liquid crystal display device having pixels having such a structure will be described with reference to FIG. 2.

2 is a block diagram of a conventional liquid crystal display device.

Referring to FIG. 2, the liquid crystal display 100 according to the related art includes a thin film transistor for driving the liquid crystal cell Clc at the intersection of the data lines DL1 to DLm and the gate lines GL1 to GLn. TFT: a thin film transistor (110) having a thin film transistor (110), a data driver (120) for supplying data to the data lines (DL1 to DLm) of the liquid crystal display panel 110, the liquid crystal display panel 110 A gate driver 130 for supplying a gate pulse to the gate lines GL1 to GLn of the gate line, a gamma reference voltage generator 140 for generating a gamma reference voltage and supplying the gamma reference voltage to the data driver 120, and a liquid crystal display panel The backlight assembly 150 for irradiating light to the 110, the inverter 160 for applying an alternating voltage and current to the backlight assembly 160, and the common voltage Vcom are generated to generate the liquid crystal display panel 110. Common voltage generator 170 for supplying the common electrode of the liquid crystal cell Clc of ), A gate driving voltage generator 180 for generating and supplying a gate high voltage VGH and a gate low voltage VGL to the gate driver 130, the data driver 120 and the gate driver 130. It includes a timing controller 190 for controlling.

In the liquid crystal display panel 110, liquid crystal is injected between two glass substrates. The data lines DL1 to DLm and the gate lines GL1 to GLn are orthogonal to the lower glass substrate of the liquid crystal display panel 110. TFTs are formed at intersections of the data lines DL1 to DLm and the gate lines GL1 to GLn. The TFT supplies the data on the data lines DL1 to DLm to the liquid crystal cell Clc in response to the gate pulse. The gate electrodes of the TFTs are connected to the gate lines GL1 to GLn, and the source electrodes of the TFTs are connected to the data lines DL1 to DLm. The drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell Clc and the storage capacitor Cst.

The TFT is turned on in response to the gate pulse supplied to the gate terminal via the gate lines GL1 to GLn. When the TFT is turned on, video data on the data lines DL1 to DLm is supplied to the pixel electrode of the liquid crystal cell Clc.

The data driver 120 supplies data to the data lines DL1 to DLm in response to the data driving control signal DDC supplied from the timing controller 190, and digital video data supplied from the timing controller 190. After sampling and latching the RGB, the liquid crystal cell Clc of the liquid crystal display panel 110 is converted into an analog data voltage capable of expressing gray scale based on the gamma reference voltage supplied from the gamma reference voltage generator 140. Supply to the data lines DL1 to DLm.

The gate driver 130 sequentially generates gate pulses in response to the gate driving control signal GDC and the gate shift clock GSC supplied from the timing controller 190 and supplies them to the gate lines GL1 to GLn. In this case, the gate driver 130 determines the high level voltage and the low level voltage of the gate pulses according to the gate high voltage VGH and the gate low voltage VGL supplied from the gate driving voltage generator 180.

The gamma reference voltage generator 140 receives a high potential power supply voltage VDD to generate a positive gamma reference voltage and a negative gamma reference voltage and output the same to the data driver 120.

The backlight assembly 150 is disposed on the rear surface of the liquid crystal display panel 110 and emits light by an AC voltage and a current supplied from the inverter 160 to irradiate light to each pixel of the liquid crystal display panel 110.

The inverter 160 converts the square wave signal generated therein into a triangular wave signal and compares the triangular wave signal with a DC power supply voltage (VCC) supplied from the system to generate a burst dimming signal proportional to the comparison result. . When a burst dimming signal determined according to an internal square wave signal is generated, a driving IC (not shown) for controlling the generation of AC voltage and current in the inverter 160 is supplied to the backlight assembly 150 according to the burst dimming signal. Control the generation of alternating voltage and current.

The common voltage generator 170 receives the high potential power voltage VDD to generate the common voltage Vcom and supplies the common voltage Vcom to the common electrodes of the liquid crystal cells Clc of each pixel of the liquid crystal display panel 110.

The gate driving voltage generator 180 receives the high potential power voltage VDD to generate the gate high voltage VGH and the gate low voltage VGL to supply the gate driver 130 to the gate driver 130. Here, the gate driving voltage generation unit 180 generates a gate high voltage VGH that is greater than or equal to the threshold voltage of the TFTs provided in each pixel of the liquid crystal display panel 110, and the gate low voltage that is less than or equal to the threshold voltage of the TFT. VGL). The gate high voltage VGH and the gate low voltage VGL generated in this way are used to determine the high level voltage and the low level voltage of the gate pulse generated by the gate driver 130, respectively.

The timing controller 190 supplies digital video data RGB, which is supplied from a digital video card (not shown), to the data driver 120, and also horizontal / vertical synchronization signals H and V according to the clock signal CLK. The data driving control signal DDC and the gate driving control signal GDC may be generated and supplied to the data driver 120 and the gate driver 130, respectively. The data driving control signal DDC includes a source shift clock SSC, a source start pulse SSP, a polarity control signal POL, a source output enable signal SOE, and a gate driving control signal GDC. ) Includes a gate start pulse (GSP) and a gate output enable (GOE).

In the conventional liquid crystal display device as described above, since the plurality of gate lines GL1 to GLn are formed on the liquid crystal display panel 110 at regular intervals, the first gate line GL1 and the last gate line ( GLn) was affected by static electricity in the manufacturing process. Accordingly, the signal characteristics of the gate pulses supplied to the first gate line GL1 and the last gate line GLn are degraded by the static electricity, and thus there is a problem in that image quality deteriorates.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a liquid crystal display device and a driving method thereof capable of compensating signal characteristics of a gate line degraded by static electricity or the like.

Disclosure of Invention An object of the present invention is to provide a liquid crystal display device and a driving method thereof capable of maintaining high quality image quality by compensating signal characteristics of a gate line degraded by static electricity or the like.

An object of the present invention is to provide a liquid crystal display device and a driving method thereof capable of simultaneously supplying two gate pulses to a first gate line and a last gate line among a plurality of gate lines formed in the liquid crystal display panel.

The present invention for achieving the above object, the liquid crystal display panel having a plurality of gate lines formed; A gate driver for sequentially supplying gate pulses to the plurality of gate lines, and simultaneously supplying two gate pulses to a first gate line and a last gate line; And a timing controller for controlling generation of gate pulses of the gate driver.

The gate driver may include: first to nth driving cells connected to the plurality of gate lines in a one-to-one correspondence with the control of the timing controller to supply a gate pulse; A first auxiliary driving cell for supplying a gate pulse to the first gate under the control of the timing controller; And a second auxiliary driving cell driven by the gate pulse supplied from the n-th driving cell to supply the gate pulse to the last gate line.

In the present invention, the first auxiliary driving cell is characterized by supplying a gate pulse to the first gate line at the same time as the first driving cell.

In the present invention, the second auxiliary driving cell is characterized in that the supply of the gate pulse to the last gate line at the same time as the n-th driving cell.

The present invention comprises the steps of: generating a gate control signal instructing the supply of the gate pulse; And sequentially supplying gate pulses to a plurality of gate lines formed in the liquid crystal display panel according to the gate control signal, wherein two gates are respectively provided to a first gate line and a last gate line among the plurality of gate lines. And supplying pulses simultaneously.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

3 is a configuration diagram of a liquid crystal display device according to an exemplary embodiment of the present invention.

3, the liquid crystal display device 200 shown in FIG. 3 includes the liquid crystal display panel 110, the data driver 120, the gamma reference voltage generator 140, and the backlight assembly 150 as in FIG. 2. ), An inverter 160, a common voltage generator 170, and a gate driving voltage generator 180, but omitting these components from FIG. 3 so that the characteristic components of the present invention are clearly shown in FIG. 3. It was.

Referring to FIG. 3, the liquid crystal display device 200 of the present invention sequentially supplies gate pulses to a plurality of gate lines GL1 to GLn formed on the liquid crystal display panel 110, but the first gate line GL1. And a gate controller 210 for simultaneously supplying two gate pulses to the first gate line GLn and a timing controller for controlling the data supply of the data driver 120 and the generation of the gate pulse of the gate driver 210. 220.

The gate driver 210 is connected to the plurality of gate lines GL1 to GLn in a one-to-one correspondence with the control of the timing controller 220 to supply first to nth drive cells 211-1 for supplying a gate pulse. 211-n, the first auxiliary drive cell 212 for supplying the gate pulse to the first gate line GL1 under the control of the timing controller 220, and the n-1th driving cell 211- (n And a second auxiliary driving cell 213 for supplying the gate pulse to the last gate line GLn by being driven by the gate pulse supplied from -1)).

The first driving cell 211-1 is driven by a high level drive signal supplied from the timing controller 220, and supplies the high level clock signal input in this state to the first gate line GL1 as a gate pulse. do.

The second driving cell 211-2 is driven by a gate pulse which is a high level driving signal supplied from the first driving cell 211-1, and gates the high level clock signal input in this state as a gate pulse. Supply to line GL2.

The n-th driving cell 211-n is driven by a gate pulse which is a high-level driving signal supplied from the n-th driving cell 211-(n-1), and the high level clock is input in this state. The signal is supplied to the last gate line GLn as a gate pulse.

Through this process, the third to n-th driving cells 211-3 to 211- (n-1) are also driven to supply the gate pulse to the gate line connected thereto.

The first auxiliary drive cell 212 is driven by a high level drive signal supplied from the timing controller 220, and supplies the high level clock signal input in this state to the first gate line GL1 as a gate pulse. . However, the gate pulse generated from the first auxiliary driving cell 212 may be supplied to the first gate line GL1 simultaneously with the gate pulse generated by the first driving cell 211.

The second auxiliary drive cell 213 is driven by a gate pulse which is a high level driving signal supplied from the n-1th driving cell 211-(n-1), and the high level clock signal input in this state. Is supplied as the gate pulse to the last gate line GLn. Here, the gate pulse generated from the second auxiliary driving cell 213 is supplied to the last gate line GLn simultaneously with the gate pulse generated by the nth driving cell 211-n.

The timing controller 220 supplies digital video data RGB, which is supplied from a digital video card (not shown), to the data driver 120, and also horizontal / vertical synchronization signals H and V according to the clock signal CLK. The data driving control signal DDC and the gate driving control signal GDC may be generated and supplied to the data driver 120 and the gate driver 210, respectively. The data driving control signal DDC includes a source shift clock SSC, a source start pulse SSP, a polarity control signal POL, a source output enable signal SOE, and the gate driving control signal GDC. ) Includes a gate start pulse (GSP) and a gate output enable (GOE).

In addition, the timing controller 220 simultaneously supplies a gate control signal instructing the supply of the gate pulse to the first driving cell 211-1 and the first auxiliary driving cell 212 to supply the gate pulse to the gate line. To control.

FIG. 4 is a circuit diagram of the first to nth driving cells and the first and second auxiliary driving cells in FIG. 3.

Referring to FIG. 4, the first to nth driving cells 211-1 to 211-n and the first and second auxiliary driving cells 212 and 213 are respectively N-MOS transistors N_TR1 to N_TR8. It consists of

The N-MOS transistor N_TR1 has a drain and a gate commonly connected to the driving signal input terminal Vin, the drain of the N-MOS transistor N_TR3, the drain of the N-MOS transistor N_TR4, and the N-MOS transistor. It has a source commonly connected to the gate of the jitter N_TR5 and the gate of the NMOS transistor N_TR7.

The N-MOS transistor N_TR2 has a drain connected to the high potential power supply voltage terminal VDD, a gate connected to the inverted clock terminal / CLK, and a gate of the N-MOS transistor N_TR3, A source is commonly connected to the gate of the N-MOS transistor N_TR8 and the drain of the N-MOS transistor N_TR5.

The NMOS transistor N_TR3 has a drain connected in common to the source of the NMOS transistor N_TR1, the drain of the NMOS transistor N_TR4, and the gate of the NMOS transistor N_TR7. Vss), and a gate commonly connected to the source of the N-MOS transistor N_TR2, the drain of the N-MOS transistor N_TR5, and the gate of the N-MOS transistor N_TR8.

The NMOS transistor N_TR4 is common to the source of the NMOS transistor N_TR1, the drain of the NMOS transistor N_TR3, the gate of the NMOS transistor N_TR5, and the gate of the NMOS transistor N_TR7. It has a drain connected, has a gate connected to the reset terminal Vreset, and has a source connected to the ground terminal Vss.

The NMOS transistor N_TR5 is common to the source of the NMOS transistor N_TR1, the drain of the NMOS transistor N_TR3, the gate of the NMOS transistor N_TR4, and the gate of the NMOS transistor N_TR7. A drain having a gate connected thereto and commonly connected to a source of the NMOS transistor N_TR2, a gate of the NMOS transistor N_TR3, a source of the NMOS transistor N_TR6, and a gate of the NMOS transistor N_TR8. And a source connected to the ground terminal Vss, a source of the NMOS transistor N_TR2, a gate of the NMOS transistor N_TR3, a drain of the NMOS transistor N_TR6, and an NMOS transistor. It has a drain commonly connected to the gate of the jitter N_TR8.

The N-MOS transistor N_TR6 has a gate commonly connected to the gate of the driving signal input terminal Vin and the N-MOS transistor N_TR1, has a source connected to the ground terminal Vss, and an N-MOS transistor. The source of the jitter N_TR2, the gate of the NMOS transistor N_TR3, the drain of the NMOS transistor N_TR5 and the gate of the NMOS transistor N_TR8 are commonly connected.

The N-MOS transistor N_TR7 has a drain connected to the clock terminal CLK, a source connected to the driving signal output terminal Vout and the gate line GL, and an N-MOS transistor N_TR1. And a gate commonly connected to the source of the NMOS transistor N_TR3, the drain of the NMOS transistor N_TR4, and the gate of the NMOS transistor N_TR5.

The N-MOS transistor N_TR8 has a source connected to the source of the N-MOS transistor N_TR7, the drive signal output terminal Vout, and the gate line GL, and has a drain connected to the ground terminal Vss. And a gate commonly connected to the source of the NMOS transistor N_TR2, the gate of the NMOS transistor N_TR3, the drain of the NMOS transistor N_TR5, and the drain of the NMOS transistor N_TR6.

Here, the output terminal Vout represents an equivalent circuit state connected to the corresponding gate line and the driving cell of the next stage.

If the circuit shown in FIG. 4 represents the first driving cell 211-1, the gate control signal supplied from the timing controller 220 is input to the driving signal input terminal Vin, and the output terminal Vout is driven to the second driving cell. It is connected to the drive signal input terminal Vin of the cell 211-2.

If the circuit shown in Fig. 4 shows the second to n-th driving cells 211-2 to 211- (n-1), respectively, the gate supplied from the previous driving cell part to the driving signal input terminal Vin is provided. The pulse is input as the gate control signal, and the output terminal Vout is connected to the drive signal input terminal Vin of the drive cell located at the next stage.

If the circuit shown in FIG. 4 shows the n-th driving cell 211-n, the gate pulse supplied from the previous n-th driving cell 211-(n-1) to the driving signal input terminal Vin is provided. Is input as the gate control signal, and there is no output terminal Vout.

If the circuit shown in FIG. 4 shows the first auxiliary drive cell 212, the gate control signal supplied from the timing controller 220 is input to the driving signal input terminal Vin, and the source of the N-MOS transistor N_TR7 is input. And the output side located between the drain of the N-MOS transistor N_TR8 are connected to the first gate line GL1, and there is no output terminal Vout.

If the circuit shown in FIG. 4 shows the second auxiliary drive cell 213, the gate pulse supplied from the n-th driving cell 211-(n-1) is supplied to the driving signal input terminal Vin with the gate control signal. The output side, which is input as N and is located between the source of the N-MOS transistor N_TR7 and the drain of the N-MOS transistor N_TR8, is connected to the last gate line GLn, and the output terminal Vout does not exist.

Operations of the first to nth driving cells 211-1 to 211-n and the first and second auxiliary driving cells 212 and 213 having the circuit configuration described above will be described below.

First, the case in which the reset signal is input through the reset terminal Vreset will be described.

The N-MOS transistor N_TR4 is turned on by the input reset signal, thereby switching the voltage applied to the drain to ground, which causes the N-MOS transistors N_TR5 and N_TR7 having a gate connected to the drain of the N-MOS transistor N_TR3. Is turned off to reset.

Next, the high level gate control signal (or gate pulse), the high level clock signal, and the low level inverted clock signal are respectively divided into the driving signal input terminal Vin, the clock terminal CLK, and the inverted clock terminal / CLK. The case of input via the following will be described.

When the input high level gate control signal is applied to the gates of the N-MOS transistors N_TR1 and N_TR6 and the N-MOS transistors N_TR1 and N_TR6 are turned on, the high level supplied to the drain of the N-MOS transistor N_TR1. Gate control signal of the NMOS transistor N_TR7 is supplied to the gate of the NMOS transistor N_TR7, so that the NMOS transistor N_TR7 is supplied to the drain through the clock terminal CLK. The clock signal is switched to output a gate pulse to the gate line and the driving signal output terminal Vout.

At this time, the low level inversion clock signal is applied to the gate of the NMOS transistor N_TR2 through the inversion clock stage / CLK to turn off the NMOS transistor N_TR2 to thereby turn off the NMOS transistors N_TR3 and N_TR8. ) And a low signal is applied to the gate of the NMOS transistors N_TR5 and N_TR6. Accordingly, the N-MOS transistor N_TR3 is turned off so that the voltage supplied to the gate of the N-MOS transistor N_TR7 is not lost, and the N-MOS transistor N_TR8 is turned off to ground voltage. VSS is blocked from being output to the gate line GL and the driving signal output terminal Vout. Then, the low level reset signal is applied to the gate of the NMOS transistor N_TR4 connected to the reset terminal Vreset to turn off the NMOS transistor N_TR4.

Lastly, when the low level gate control signal, the low level clock signal, and the high level inversion clock signal are input through the driving signal input terminal Vin, the clock terminal CLK, and the inverting clock stage / CLK, respectively. Explain.

When the input low level gate control signal is applied to the gates of the N-MOS transistors N_TR1 and N_TR6 and the N-MOS transistors N_TR1 and N_TR6 are turned off, the low signal is applied to the gate of the N-MOS transistor N_TR7. As the NMOS transistor N_TR7 is supplied to turn off, the NMOS transistor N_TR7 outputs the low level clock signal supplied to the drain through the clock terminal CLK to the gate line and the driving signal output terminal Vout. Block the thing.

At this time, the high level inverted clock signal is applied to the gate of the NMOS transistor N_TR2 through the inverted clock stage / CLK to turn on the NMOS transistor N_TR2, thereby draining the NMOS transistor N_TR2. The high potential power supply voltage VDD applied through the high potential power terminal VDD connected to the NMOS transistor N_TR8 is supplied to the gate of the NMOS transistor N_TR8 through the NMOS transistor N_TR2 to supply the NMOS transistor N_TR8. Turn on. Accordingly, the N-MOS transistor N_TR8 switches the ground voltage VSS connected to the source and outputs a low signal to the gate line GL and the driving signal output terminal Vout. Then, the low level reset signal is applied to the gate of the NMOS transistor N_TR4 connected to the reset terminal Vreset to turn off the NMOS transistor N_TR4.

The clock signal, the inverted clock signal and the reset signal are supplied from the timing controller 220.

As described above, the present invention provides two gate pulses simultaneously to the first gate line and the last gate line among the plurality of gate lines formed in the liquid crystal display panel, thereby reducing the signal characteristics of the gate line degraded by static electricity. Compensation, thereby providing a good picture quality.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

Claims (5)

A liquid crystal display panel in which a plurality of gate lines are formed; A gate driver for sequentially supplying gate pulses to the plurality of gate lines, and simultaneously supplying two gate pulses to a first gate line and a last gate line; And Timing controller for controlling the generation of the gate pulse of the gate driver Liquid crystal display device comprising a. The method of claim 1, The gate driver, First to n-th driving cells connected to the plurality of gate lines in a one-to-one correspondence with the control of the timing controller to supply a gate pulse; A first auxiliary driving cell for supplying a gate pulse to the first gate line under control of the timing controller; And A second auxiliary drive cell driven by a gate pulse supplied from the n-th driving cell to supply a gate pulse to the last gate line; Liquid crystal display device comprising a. The method of claim 2, And the first auxiliary driving cell supplies a gate pulse to the first gate line simultaneously with the first driving cell. The method of claim 2 or 3, And the second auxiliary driving cell supplies a gate pulse to the last gate line simultaneously with the nth driving cell. Generating a gate control signal instructing supply of the gate pulse; And The gate pulses are sequentially supplied to a plurality of gate lines formed in the liquid crystal display panel according to the gate control signal, and two gate pulses are simultaneously supplied to a first gate line and a last gate line among the plurality of gate lines. step Method of driving a liquid crystal display device comprising a.

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