KR101244658B1 - Liquid Crystal Display Device - Google Patents

Abstract

The present invention provides a liquid crystal display panel including a plurality of gate lines; A plurality of gate driving cells for sequentially supplying scan pulses to the plurality of gate lines; A first auxiliary driving cell supplying a high level driving signal supplied from a timing controller to a first gate driving cell among the plurality of gate driving cells; And a second auxiliary driving cell supplied with a driving signal of a high level supplied from a last gate driving cell among the plurality of gate driving cells.

According to the present invention, since the first and second auxiliary driving cells are formed in addition to the gate driving cells, the signal characteristics of the first gate wiring and the last gate wiring can be prevented from being lowered by static electricity or the like.

LCD, Static electricity, Scan pulse, Compensation

Description

Liquid Crystal Display Device

1 is a block diagram schematically illustrating a driving unit of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is a block diagram schematically illustrating a gate driver according to an exemplary embodiment of the present invention.

FIG. 3 is a circuit diagram illustrating the structures of the first to nth gate driving cells, the first auxiliary driving cell, and the second auxiliary driving cell in FIG. 2.

Description of the Related Art

100: liquid crystal display device 110: liquid crystal display panel

120: data driver 130: gate driver

180: gate driving voltage generator 190: timing controller

131-1 to 131-n: first to nth gate driving cells

122 and 123: first and second auxiliary drive cells

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device capable of compensating for signal characteristics of a gate wiring degraded by static electricity.

Ultra-thin flat panel displays with a thickness of only a few centimeters (cm). Among them, liquid crystal displays have low operating voltages, which consume less power and can be used as portable devices. Applications range from ships to spacecraft to aircraft.

The liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field. The liquid crystal display device includes a liquid crystal panel having pixel regions arranged in a matrix and a driving circuit for driving the liquid crystal panel. Is done.

The driving circuit includes a gate driver for driving the gate lines, a data driver for driving the data lines, and a timing controller for controlling the gate driver and the data driver.

The gate driver includes a shift register to sequentially output scan pulses, and the shift register includes a plurality of stages that are connected to each other dependently.

Each of the plurality of stages receives at least one clock pulse among a plurality of clock pulses having a sequential phase difference from each other, sequentially outputs scan pulses, and sequentially applies them to the gate lines of the liquid crystal panel.

In the related art, a shift register of the gate driver is formed using a gate driver integrated circuit (IC), but recently, a shift resist is formed on a liquid crystal display panel to reduce material costs, reduce the number of processes, and shorten the process time. Gate In Panel (GIP) technology is used.

However, when using the gate in panel (GIP) technology, the first gate wiring and the last gate wiring are affected by static electricity in the manufacturing process. As a result, the signal characteristics of the scan pulses supplied to the first gate line and the last gate line are deteriorated by static electricity, which causes a problem of deteriorating image quality.

The present invention has been made to solve the above problems,

SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal display device capable of compensating for the signal characteristics of a gate wiring deteriorated by static electricity or the like by forming first and second auxiliary driving cells in addition to the gate driving cell to maintain high quality image quality.

In order to achieve the above object, the present invention provides a liquid crystal display panel including a plurality of gate lines; A plurality of gate driving cells for sequentially supplying scan pulses to the plurality of gate lines; A first auxiliary driving cell supplying a high level driving signal supplied from a timing controller to a first gate driving cell among the plurality of gate driving cells; And a second auxiliary driving cell receiving a high level driving signal supplied from a last gate driving cell among the plurality of gate driving cells.

In addition, the present invention, to achieve the above object, the step of supplying a high level drive signal from the timing controller to the first auxiliary drive cell; Supplying a high level driving signal from the first auxiliary driving cell to a gate driving cell driving a first gate wiring; And supplying a high level driving signal from the gate driving cell for driving the last gate wiring to the second auxiliary driving cell.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram schematically illustrating a driving unit of a liquid crystal display according to an exemplary embodiment of the present invention.

As can be seen in FIG. 1, in the liquid crystal display device 100 according to the exemplary embodiment of the present invention, the data lines DL1 to DLm and the gate lines GL1 to GLn cross each other, and the liquid crystal cell Clc is disposed at an intersection thereof. A liquid crystal display panel 110 including a thin film transistor (TFT) for driving, a data driver 120 for supplying data to data lines DL1 to DLm of the liquid crystal display panel 110, The gate driver 130 for supplying scan pulses to the gate lines GL1 to GLn of the liquid crystal display panel 110, and generates a gate high voltage VGH and a gate low voltage VGL to the gate driver 130. And a timing controller 190 for controlling the data driver 120 and the gate driver 130.

In the liquid crystal display panel 110, liquid crystal is injected between two glass substrates. On the lower glass substrate of the liquid crystal display panel 110, the data lines DL1 to DLm and the gate lines GL1 to GLn are orthogonal to each other. The thin film transistor TFT is formed at an intersection of the data lines DL1 to DLm and the gate lines GL1 to GLn. The thin film transistor TFT supplies the data on the data lines DL1 to DLm to the liquid crystal cell Clc in response to the scan pulse. The gate electrode of the thin film transistor TFT is connected to the gate lines GL1 to GLn, and the source electrode of the TFT is connected to the data lines DL1 to DLm. The drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell Clc and the storage capacitor Cst.

The thin film transistor TFT is turned on in response to a scan pulse supplied to the gate electrode via the gate lines GL1 to GLn. When the thin film transistor TFT is turned on, video data on the data lines DL1 to DLm is supplied to the pixel electrode of the liquid crystal cell Clc.

The data driver 120 supplies data to the data lines DL1 to DLm in response to the data driving control signal DDC supplied from the timing controller 190, and digital video data supplied from the timing controller 190. After sampling and latching the RGB, the LCD is converted into an analog data voltage capable of expressing gray scale in the liquid crystal cell Clc of the liquid crystal display panel 110 and supplied to the data lines DL1 to DLm. do.

The gate driver 130 sequentially generates scan pulses in response to the gate driving control signal GDC and the gate shift clock GSC supplied from the timing controller 190 and supplies them to the gate lines GL1 to GLn. The gate driver 130 determines the high level voltage and the low level voltage of the scan pulse in accordance with the gate high voltage VGH and the gate low voltage VGL supplied from the gate drive voltage generator 180, respectively.

In FIG. 1, the gate driver 130 is separated from the liquid crystal display panel 110, but the gate driver 130 is disposed on one side of the gate lines GL1 to GLn on the liquid crystal display panel 110. It is formed by a gate in panel (Gate In Panel, GIP) method.

When the gate driver 130 is formed on the liquid crystal display panel 110 by using a gate in panel (GIP) method, material costs and number of processes may be reduced.

The gate driving voltage generator 180 receives the high potential power voltage VDD to generate the gate high voltage VGH and the gate low voltage VGL to supply the gate driver 130 to the gate driver 130. Here, the gate driving voltage generator 180 generates a gate high voltage VGH that is equal to or greater than a threshold voltage of the thin film transistor TFT provided in each pixel of the liquid crystal display panel 110, and generates a thin film transistor TFT. A gate low voltage VGL is generated below the threshold voltage. The gate high voltage VGH and the gate low voltage VGL thus generated are used to determine the high level voltage and the low level voltage of the scan pulse generated by the gate driver 130, respectively.

The timing controller 190 supplies digital video data RGB, which is supplied from a digital video card (not shown), to the data driver 120, and also the horizontal / vertical synchronization signal H / V according to the clock signal CLK. The data driving control signal DDC and the gate driving control signal GDC are generated by using the same and supplied to the data driver 120 and the gate driver 130, respectively. The data driving control signal DDC includes a source shift clock SSC, a source start pulse SSP, a polarity control signal POL, a source output enable signal SOE, and the gate driving control signal GDC. ) Includes a gate start pulse GSP and a gate output enable signal GOE.

Hereinafter, the structure and operation of the gate driver 130 which is a feature of the present invention will be described in detail.

2 is a block diagram schematically illustrating a gate driver according to an exemplary embodiment of the present invention.

As can be seen in FIG. 2, the gate driver 130 according to the exemplary embodiment of the present invention is connected in a one-to-one correspondence with a plurality of gate lines GL1 to GLn under the control of the timing controller 190 to provide a scan pulse. First to nth gate driving cells 131-1 to 131-n for supplying, and first gate driving cells 131-1 for driving the first gate wiring GL1 under the control of the timing controller 190. ), A second auxiliary driving cell 132 for supplying a high level driving signal to the second auxiliary driving cell 132 for supplying a high level driving signal from the nth gate driving cell 131-n for driving the last gate line GLn. It comprises a drive cell 133.

The first auxiliary drive cell 132 is driven by a high level drive signal supplied from the timing controller 190, and the first gate drive cell 131-1 uses the high level clock signal input in this state as a scan pulse. Supplies).

The first gate driving cell 131-1 is driven by a scan pulse which is a high level driving signal supplied from the first auxiliary driving cell 132, and the first high frequency clock signal is input as a scan pulse. Supply to gate wiring GL1. In this case, the scan pulse supplied to the first gate line GL1 is supplied not only to the gate line GL1 but also to the second gate driving cell 131-2 and the first auxiliary driving cell 132.

The scan pulse is supplied to the second gate driving cell 131-2 to drive the second gate driving cell 131-2 as a high level driving signal, and is supplied to the first auxiliary driving cell 132 to supply the first pulse. The generation of the scan pulse of the auxiliary drive cell 132 is stopped.

The second gate driving cell 131-2 is driven by a scan pulse which is a high level driving signal supplied from the first gate driving cell 131-1, and scans a high level clock signal input in this state. As a second gate wiring GL2.

The scan pulse supplied to the second gate line GL2 is also supplied to the third gate driving cell 131-3 to drive the third gate driving cell 131-3 as a high level driving signal, and the first The first gate driving cell 131-1 is supplied to the gate driving cell 131-1 to reset the first gate driving cell 131-1.

The n-th gate driving cell 131-n is driven by a scan pulse which is a high level drive signal supplied from the n-th gate driving cell 131-(n-1), and is input in this state. Is supplied to the last gate line GLn as a scan pulse.

The scan pulse supplied to the n-th gate line GLn is also supplied to the second auxiliary drive cell 133 to drive the second auxiliary drive cell 133 as a high level drive signal, and drive the n-1 gate. Supplied to the cell 131-(n-1) to reset the n-th gate driving cell 131-(n-1).

Through this process, the third to n-th gate driving cells 131-3 to 131- (n-1) are also driven to supply the scan pulse to the gate wiring connected thereto.

The second auxiliary drive cell 133 is driven by a scan pulse which is a high level drive signal supplied from the nth gate driving cell 131-n, and the high level clock signal input in this state is used as a scan pulse. It supplies to the n gate driving cell 131-n. The scan pulse from the second auxiliary drive cell 133 is supplied to the nth gate driving cell 131-n to reset the nth gate driving cell 131-n.

FIG. 3 is a circuit diagram illustrating the structures of the first to nth gate driving cells, the first auxiliary driving cell, and the second auxiliary driving cell in FIG. 2.

As shown in FIG. 3, each of the first to nth gate driving cells 131-1 to 131-n, the first auxiliary driving cell 132, and the second auxiliary driving cell 133 may include a plurality of NMOS transistors ( N_TR1 to N_TR8).

The first N-MOS transistor N_TR1 has a drain and a gate commonly connected to the driving signal input terminal Vin, the drain of the third N-MOS transistor N_TR3, the drain of the fourth N-MOS transistor N_TR4, and the first. A source is commonly connected to the gate of the 5 N-MOS transistor N_TR5 and the gate of the seventh N-MOS transistor N_TR7.

The second N-MOS transistor N_TR2 has a drain connected to the high potential power supply voltage terminal VDD, a gate connected to the inverted clock terminal / CLK, and a third N-MOS transistor N_TR3. Has a source commonly connected to the gate of the gate, the gate of the eighth N-MOS transistor N_TR8, and the drain of the fifth N-MOS transistor N_TR5.

The third N-MOS transistor N_TR3 has a drain connected in common to the source of the first N-MOS transistor N_TR1, the drain of the fourth N-MOS transistor N_TR4, and the gate of the seventh N-MOS transistor N_TR7. A gate having a source connected to the ground terminal Vss and commonly connected to the source of the second N-MOS transistor N_TR2, the drain of the fifth N-MOS transistor N_TR5, and the gate of the eighth N-MOS transistor N_TR8. Has

The fourth NMOS transistor N_TR4 includes a source of the first NMOS transistor N_TR1, a drain of the third NMOS transistor N_TR3, a gate of the fifth NMOS transistor N_TR5, and a seventh NMOS transistor N_TR7. Has a drain connected in common to the gate, has a gate connected to the reset terminal Vreset, and has a source connected to the ground terminal Vss.

The fifth NMOS transistor N_TR5 includes a source of the first NMOS transistor N_TR1, a drain of the third NMOS transistor N_TR3, a gate of the fourth NMOS transistor N_TR4, and a seventh NMOS transistor N_TR7. The gate of the second NMOS transistor N_TR2, the gate of the third NMOS transistor N_TR3, the source of the sixth NMOS transistor N_TR6, and the eighth NMOS transistor ( It has a drain commonly connected to the gate of N_TR8, has a source connected to the ground terminal Vss, the source of the second N-MOS transistor N_TR2, the gate of the third N-MOS transistor N_TR3, and the sixth N The drain of the MOS transistor N_TR6 and the gate of the eighth N-MOS transistor N_TR8 are commonly connected.

The sixth N-MOS transistor N_TR6 has a gate commonly connected to the drive signal input terminal Vin and the gate of the first N-MOS transistor N_TR1, has a source connected to the ground terminal Vss, and a second The source of the N-MOS transistor N_TR2, the gate of the third N-MOS transistor N_TR3, the drain of the fifth N-MOS transistor N_TR5, and the drain of the eighth N-MOS transistor N_TR8 are commonly connected.

The seventh N-MOS transistor N_TR7 has a drain connected to the clock terminal CLK, has a source commonly connected to the driving signal output terminal Vout and the gate wiring GL, and has a first N-MOS transistor N_TR1. ), A drain of the third N-MOS transistor N_TR3, a drain of the fourth N-MOS transistor N_TR4, and a gate commonly connected to the gate of the fifth N-MOS transistor N_TR5.

The eighth N-MOS transistor N_TR8 has a source connected to the source of the seventh N-MOS transistor N_TR7, the drive signal output terminal Vout, and the gate wiring GL, and is connected to the ground terminal Vss. And a common connection to a source of the second N-MOS transistor N_TR2, a gate of the third N-MOS transistor N_TR3, a drain of the fifth N-MOS transistor N_TR5, and a drain of the sixth N-MOS transistor N_TR6. Has a gate.

Here, the output terminal Vout shows an equivalent circuit state connected to the corresponding gate wiring and the gate driving cell of the next stage.

If the circuit shown in FIG. 3 shows the first auxiliary drive cell 132, the gate control signal supplied from the timing controller 190 is input to the driving signal input terminal Vin, and the source of the NMOS transistor N_TR7 is input. And the output terminal Vout positioned between the drain of the N-MOS transistor N_TR8 are connected to the first gate driving cell 131-1, and the gate line GL connected to the first auxiliary driving cell 132 is does not exist.

The first gate line connected to the first gate driving cell 131-1 by forming the first auxiliary driving cell 132 not connected to the gate line GL at the front end of the first gate driving cell 131-1. The signal characteristic of the scan pulse supplied to GL1 can be prevented from being lowered by static electricity.

That is, the first auxiliary driving cell 132 is formed as a dummy in front of the first gate driving cell 131-1, so that the first gate line GL1 connected to the first gate driving cell 131-1 is dummy. It is possible to ensure the signal characteristics of the scan pulse supplied to.

The gate wiring GL may be connected to the first auxiliary driving cell 132, but even if the gate wiring GL is connected to the first auxiliary driving cell 132, the liquid crystal cell is not connected, As signal characteristics are deteriorated, it does not function very much.

If the circuit shown in FIG. 3 shows the first gate driving cell 131-1, a scan pulse supplied from the first auxiliary driving cell 132 is input to the driving signal input terminal Vin, and the output terminal Vout is input to the driving signal input terminal Vin. The driving signal input terminal Vin of the second gate driving cell 131-2 and the reset terminal Vreset of the first auxiliary driving cell 132 are connected.

If the circuit shown in Fig. 3 shows the second to n-1 gate driving cells 131-2 to 131- (n-1), respectively, the driving signal input terminal Vin is supplied from the previous gate driving cell portion. The scan pulse to be input is input as the gate control signal, and the output terminal Vout is connected to the drive signal input terminal Vin of the gate driving cell positioned at the next stage and the reset terminal Vreset of the gate driving cell positioned at the previous stage.

If the circuit shown in FIG. 3 shows the n-th gate driving cell 131-n, the driving signal input terminal Vin is supplied from the previous n-th gate driving cell 131-(n-1). The scan pulse is input as a gate control signal, and the output terminal Vout is a reset terminal of the driving signal input terminal Vin of the second auxiliary driving cell 133 and the n-1th gate driving cell 131-(n-1). Is connected to (Vreset).

If the circuit shown in FIG. 3 shows the second auxiliary drive cell 133, the scan pulse supplied from the nth gate driving cell 131-n is input to the driving signal input terminal Vin as the gate control signal. The output terminal Vout located between the source of the seventh N-MOS transistor N_TR7 and the drain of the eighth N-MOS transistor N_TR8 is connected to the reset terminal Vreset of the n-th gate driving cell 131-1, and There is no gate line GL connected to the second auxiliary driving cell 133.

By forming the second auxiliary driving cell 133 not connected to the gate line GL at the rear end of the n-th gate driving cell 131-n, the last gate wiring connected to the n-th gate driving cell 131-n ( The signal characteristic of the scan pulse supplied to GLn) can be prevented from being lowered by static electricity.

In other words, the second auxiliary driving cell 133 is formed as a dummy at the rear end of the nth gate driving cell 131-n to the last gate line GLn connected to the nth gate driving cell 131-n. Signal characteristics of the supplied scan pulse can be secured.

The gate wiring GL may also be connected to the second auxiliary driving cell 133, but even if the gate wiring GL is connected to the second auxiliary driving cell 133, the liquid crystal cell is not connected to the second auxiliary driving cell 133. As signal characteristics are deteriorated, it does not function very much.

The operations of the first to nth gate driving cells 131-1 to 131-n and the first and second auxiliary driving cells 132 and 133 having the above-described circuit configuration will be described below.

First, the case in which the reset signal is input through the reset terminal Vreset will be described.

The fourth N-MOS transistor N_TR4 is turned on by the input reset signal to switch the voltage applied to the drain to ground, whereby a third N-MOS transistor whose gate is connected to the drain of the third N-MOS transistor N_TR3. The reset is performed by turning off the N_TR5 and N_TR7.

Next, the high level gate control signal (or scan pulse), the high level clock signal, and the low level inverted clock signal are respectively divided into the driving signal input terminal Vin, the clock terminal CLK, and the inverted clock stage / CLK. The case of input via the following will be described.

When the input high level gate control signal is applied to the gates of the first and sixth NMOS transistors N_TR1 and N_TR6 to turn on the first and sixth NMOS transistors N_TR1 and N_TR6, the first NMOS The high-level gate control signal supplied to the drain of the transistor N_TR1 is supplied to the gate of the seventh NMOS transistor N_TR7 to turn on the seventh NMOS transistor N_TR7 to thereby turn on the seventh NMOS transistor N_TR7. ) Switches the high-level clock signal supplied to the drain through the clock terminal CLK to output the scan pulse to the gate wiring and the driving signal output terminal Vout.

In this case, the low level inverted clock signal is applied to the gate of the second NMOS transistor N_TR2 through the inverted clock stage / CLK to turn off the second NMOS transistor N_TR2 to thereby turn off the third and eighth signals. The low signal is applied to the gates of the N-MOS transistors N_TR3 and N_TR8 and the drains of the fifth and eighth N-MOS transistors N_TR5 and N_TR6. Accordingly, the third N-MOS transistor N_TR3 is turned off so that the voltage supplied to the gate of the seventh N-MOS transistor N_TR7 is not lost, and the eighth N-MOS transistor N_TR8 is turned off. It is turned off to block the ground voltage Vss from being output to the gate line GL and the driving signal output terminal Vout. The low level reset signal is applied to the gate of the fourth NMOS transistor N_TR4 connected to the reset terminal Vreset to turn off the fourth NMOS transistor N_TR4.

Lastly, when the low level gate control signal, the low level clock signal, and the high level inversion clock signal are input through the driving signal input terminal Vin, the clock terminal CLK, and the inverting clock stage / CLK, respectively. Explain.

When the input low-level gate control signal is applied to the gates of the first and sixth NMOS transistors N_TR1 and N_TR6 to turn off the first and sixth NMOS transistors N_TR1 and N_TR6, the seventh NMOS A low signal is supplied to the gate of the transistor N_TR7 to turn off the seventh N-MOS transistor N_TR7, so that the seventh N-MOS transistor N_TR7 is a low-level clock supplied to the drain through the clock terminal CLK. The signal is blocked from being output to the gate wiring and the driving signal output terminal Vout.

At this time, the high level inverted clock signal is applied to the gate of the second NMOS transistor N_TR2 through the inverted clock stage / CLK to turn on the second NMOS transistor N_TR2 to thereby turn on the second NMOS. The high potential power voltage VDD applied through the high potential power terminal VDD connected to the drain of the transistor N_TR2 is supplied to the gate of the eighth NMOS transistor N_TR8 through the second NMOS transistor N_TR2. The eighth N-MOS transistor N_TR8 is turned on. Accordingly, the eighth N-MOS transistor N_TR8 switches the ground voltage Vss connected to the source and outputs a low signal to the gate line GL and the driving signal output terminal Vout. The low level reset signal is applied to the gate of the fourth NMOS transistor N_TR4 connected to the reset terminal Vreset to turn off the fourth NMOS transistor N_TR4.

The clock signal, the inverted clock signal and the reset signal are supplied from the timing controller 190.

According to the present invention,

By forming auxiliary driving cells in a dummy in front of the first gate driving cell and after the last gate driving cell, they are applied to the first gate wiring connected to the first gate driving cell and the last gate wiring connected to the last gate driving cell. The signal characteristics of the scan pulses to be compensated for are lowered by static electricity and the like, thereby providing high quality images.

Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above embodiment is for the purpose of illustration and not for the purpose of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

Claims (5)

A liquid crystal display panel in which a plurality of gate lines are formed; A plurality of gate driving cells for sequentially supplying scan pulses to the plurality of gate lines; A first auxiliary driving cell supplying a high level driving signal supplied from a timing controller to a first gate driving cell of the plurality of gate driving cells; A second auxiliary driving cell configured to receive a high level driving signal supplied from a last gate driving cell among the plurality of gate driving cells; And the plurality of gate lines are connected in a one-to-one correspondence with only the plurality of gate driving cells among the plurality of gate driving cells, the first auxiliary driving cell and the second auxiliary driving cell. delete The method of claim 1, And the plurality of gate driving cells, the first auxiliary driving cell and the second auxiliary driving cell are formed on the liquid crystal display panel. delete delete

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