KR20060002204A - Lcd panel with gate driver and method for driving the same - Google Patents

Abstract

A liquid crystal panel in which a gate line is embedded is disclosed. In response to the gate line on signal input from an external timing controller, the liquid crystal panel sets the scanning order of the gate lines of the liquid crystal panel so as to sequentially scan the gate lines of the liquid crystal panel at intervals of k lines in an interleaved manner of n gate lines. The liquid crystal panel displays the source data output from an external source driver in an interleaved gate line scan order set by the gate line shift circuit. In the liquid crystal panel according to the present invention, since the common electrode is inverted for every one line, the power consumption is reduced for every N lines, and the current consumption is reduced, and the scanning is performed by the interlacing method of k line intervals, so that the effect of one line polarity is obtained, thereby reducing the power consumption and flickering at the same time. It is effective in preventing image degradation such as a phenomenon.

Polarity reversal, liquid crystal display, interlaced method

Description

LCD panel with gate driver and driving method thereof {LCD Panel with gate driver and Method for driving the same}

1A to 1C illustrate a conventional gate line driving method of various liquid crystal panel inversion methods.

2 is a graph showing power consumption according to each driving scheme.

3 is a block diagram illustrating a liquid crystal display and a peripheral circuit according to the present invention.

4 is a block diagram illustrating a timing controller according to the present invention.

5 is a diagram illustrating an address changed by the address changer of the present invention.

FIG. 6 is a diagram illustrating an N-line gate line driving using an address changed according to FIG. 5.

7 is a view showing a storage procedure of image data according to an embodiment of the present invention.

8 is a diagram showing a storage procedure of image data according to another embodiment of the present invention.

9 is a circuit diagram showing a gate line shift circuit of a conventional liquid crystal panel with a built-in gate driver.

10 is a timing diagram of each signal shown in the circuit of FIG.

11 is a circuit diagram illustrating a gate line shift circuit of a liquid crystal panel with a gate driver according to the present invention.

12 is a timing diagram of each signal shown in the circuit of FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a driving driver and a timing controller for controlling the gate line of the liquid crystal display device to be driven by a predetermined line unit, and a driving method of the liquid crystal display device.

In general, a liquid crystal device (LCD) applies a field having a controlled voltage intensity to a material having an anisotropic dielectric constant injected between two substrates, thereby controlling an amount of light transmitted through the substrate. It is a display device that obtains a signal. Such LCDs are formed by crossing a plurality of scan lines carrying a gate selection signal and a plurality of data lines carrying color data, i.e., image data, and surrounded by these scan lines and data lines, respectively. And a plurality of pixels of matrix behavior that are serially connected through a switching element.

In the method of applying image data to each pixel of the LCD device, first, when an on / off signal is sequentially applied to the gate lines, the switching elements connected to the gate lines (scan lines) are sequentially turned on / off. At the same time, an image signal to be applied to the pixel row corresponding to the gate line is converted into a gray scale voltage divided into a plurality of voltages and applied to each data line. In this case, the gate signal is sequentially applied to all the scan lines for one frame period to apply the pixel signal to all the pixel rows, thereby displaying an image of one frame.

The liquid crystal material has a problem in that its characteristics as a display device deteriorate when an electric field in the same direction is continuously applied due to its own characteristics. Therefore, it is necessary to drive by inverting the polarity of the gray scale voltage with respect to the common voltage. That is, when the polarity of the applied voltage of one pixel receives a positive polarity signal voltage, it is necessary to receive a negative polarity signal voltage in a certain frame. As a result, the polarity of the applied voltage of the specific pixel should be made to repeat the positive and negative polarities.

For this reason, the LCD inverting method is used to invert the polarity by one frame unit, the line inverting the polarity every scan of each line by the gate line, and the dot inverting by the pixel unit. There is a driving method.

On the other hand, in the liquid crystal display device using the dot inversion driving method, there is a problem that the screen shake phenomenon occurs severely when displaying the halftone screen such as the end of the window. In addition, the dot inversion driving method requires a large amplitude to drive the data line, so the power consumption is too large to be used as a liquid crystal display device such as a portable terminal.

1A is a diagram illustrating a gate line driving of a frame inversion method.

Referring to FIG. 1A, a frame inversion method of inverting polarity on a frame basis is illustrated. In the Nth frame, all gate lines are sequentially scanned by applying a common voltage of positive polarity (+) to output image data of one frame, and in the N + 1th frame, the polarity of the gate lines is reversed. A negative common voltage is applied to sequentially scan all of the gate lines. If the frame is scanned in units of 60 frames per second, the polarity inversion of the liquid crystal display is performed once every 1/60 second.

In LCD driving, power consumption is mainly generated when the polarity of the common voltage Vcom is changed. Therefore, the frame inversion driving method having a low number of inversions consumes less power than other inversion driving methods. However, since the polarity of the entire gate line is changed, the charging polarity of all the pixels is the same in one frame, so that the difference in the liquid crystal transmittance between the two frames is easily recognized, thereby causing flicker that flickers on the screen. Therefore, the frame inversion driving method is not used well.

1B is a diagram illustrating gate line driving of a line inversion method.

Referring to FIG. 1B, when scanning the N-th frame, the line is scanned by reversing the polarity of the common voltage every time one gate line is scanned. For example, the odd line scans the positive data and the even line scans the negative data. When the N + 1 th frame is scanned, the polarity of the odd and even lines is inverted again to prevent deterioration of the liquid crystal material. In addition, since the polarity of the common voltage is inverted by one line, the problem of flickering can be solved.

However, the line inversion method has a lot of power consumption because the polarity must be inverted every scan of each line. In particular, the liquid crystal display of the line inversion method is a major disadvantage when used in a portable device, such as a portable terminal, the power consumption is important. For example, if there are 480 gate lines of the liquid crystal display, power consumption is high because the polarity must be inverted in units of 1 / (60 * 480) seconds.

1C is a diagram illustrating gate line driving of an n-line inversion method.

Referring to FIG. 1C, after scanning the n gate lines and inverting the polarity, the n gate lines are scanned again, and in this manner, after all the frames are scanned, a common polarity opposite to the n th frame is obtained. Apply voltage. If the polarity is reversed after scanning with the same polarity in units of n lines, the power consumption can be reduced by more than n times compared to the inversion of the lines. That is, if the polarity is inverted in units of 3 lines, the polarity is inverted in units of 3 / (60 * 480) seconds.

However, the n-line inversion driving method has a problem in that the flicker problem occurs because the polarity is changed for each adjacent n lines.

2 is a graph showing power consumption according to each driving scheme.

Referring to FIG. 2, the polarity inversion scheme of the frame unit consumes a small current of 1.35 mA. However, the line inversion method consumes a relatively large current of 1.85mA. On the other hand, the two-line inversion driving method consumes a current of 1.60 mA, which is halfway between the line inversion and the frame inversion method. On the other hand, there is a current consumption of 1.47mA in the three-line inversion method, it can be seen that there is a large current consumption reduction compared to the line inversion when using the polarity inversion method of two or more lines. However, two or more lines of the inverted gate line driving method has a problem of flicker because several neighboring lines have the same polarity.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a gate line driving method and a liquid crystal display device that reduce power consumption and prevent flicker of a display image.

In order to achieve the object of the present invention as described above, according to the characteristics of the present invention, a liquid crystal panel with a built-in gate driver, a plurality of pixels formed in an area where a plurality of gate lines and a plurality of data lines cross, and A gate of the liquid crystal panel so as to sequentially scan the gate lines of the liquid crystal panel at predetermined k line intervals in an interleaved manner of n gate lines in response to a gate line on signal input from a timing controller external to the liquid crystal panel; And a gate line shift circuit configured to set the scan order of the lines, and the liquid crystal panel displays the source data output from an external source driver in the interleaved gate line scan order set by the gate line shift circuit.

Preferably, the liquid crystal panel is characterized in that the liquid crystal panel inverts the polarity of the gate electrode whenever scanning of the n gate lines is completed.

More preferably, the n lines are three lines, the k line intervals are two line intervals, and the gate line shift circuit scans 2k + 1 (k is an integer) three lines sequentially and then 2k Scanning three first lines sequentially is repeated, and the liquid crystal panel inverts the polarity of the gate electrode every time the three gate lines are scanned.

In one embodiment of the present invention, the gate line shift circuit is composed of a plurality of gate line switch blocks composed of six units operating in synchronization with a clock signal and an inverted clock signal, wherein each gate line switch has a corresponding gate line. The first gate line switch of the first switch block is controlled by an externally input gate line on signal, and the first gate line switch of the next switch block is controlled by the signal of the last gate line of the previous switch block. do.

Preferably, each switch block may include a first switch corresponding to a first gate line, a second switch corresponding to a second gate line, a third switch corresponding to a third gate line, and a fourth gate line. And a fourth switch, a fifth switch corresponding to the fifth gate line, and a sixth switch corresponding to the sixth gate line, wherein the first switch is the last switch of the clock signal and the gate line on signal or a previous switch block. Is turned on in response to an output signal of the second switch; is turned off in response to an output signal of the third switch, and the second switch is turned on in response to an output signal of the inverted clock signal and the fifth switch. A fourth switch is turned off in response to an output signal of the fourth switch, and the third switch is turned on in response to the inverted clock signal and an output signal of the first switch, and the fifth switch Turned off in response to an output signal of a position, wherein the fourth switch is turned on in response to an output signal of the clock signal and the second switch, turned off in response to an output signal of the sixth switch, and A fifth switch is turned on in response to the clock signal and an output signal of the third switch, is turned off in response to an output signal of the second switch, and the sixth switch is a switch of the inverted clock signal and the fourth switch; It is turned on in response to the output signal and turned off in response to the output signal of the first switch of the next switch block.

In order to fully understand the present invention, the advantages of the operability of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

3 is a block diagram illustrating a liquid crystal display and a peripheral circuit according to the present invention.

Referring to FIG. 3, the liquid crystal display 300 receives image data from an external graphic processor 350 through an RGB interface 356. The graphic processor 350 receives data from the CPU 354 and a peripheral device 352 such as a camera and generates image data corresponding to the resolution of the liquid crystal display.

The liquid crystal display 300 includes a driving driver 302 and an LCD panel 304, and the driving driver 302 includes a data line driver 306, a gate line driver 308, a timing controller 310, and a driving voltage. And a generator 312 and a gray voltage generator 314.

The LCD panel 304 is composed of two substrates (for example, a TFT substrate or a color filter substrate), and is formed by crossing a plurality of source lines and a plurality of gate lines on one substrate, and one gate line and one Pixels are formed in respective regions where the source lines intersect.

The timing controller 310 receives an R (red), G (green), and B (blue) data signal, a vertical synchronization signal Vsync as a frame discrimination signal, and a horizontal synchronization signal Hsync as a row discrimination signal from the graphic processor 350. And a digital signal for driving the gate line driver 308, the data line driver 306, and the driving voltage generator 312 by receiving the main clock signal Clk.

In addition, the timing controller 310 outputs a gate clock signal for applying a gate-on voltage to each gate line and a gate-on enable signal for enabling the output of the gate line driver 308 to the gate line driver 308. do.

In this case, the timing controller 310 may determine the scanning order of the gate line driver 308 at a predetermined number of intervals (hereinafter, referred to as 'k lines') in an existing sequential scan order. The gate clock signal is applied by changing the scanning order to sequentially scan the gate lines.

That is, after dividing into n * k gate line addresses of the timing controller 310, the gate line scanning is read out by n-level gate lines at k line intervals without sequentially transmitting neighboring lines. . That is, when there are 480 gate lines in one frame, and scanning by adjusting five gate lines at three line intervals, 1,2,3,4,5,6,7,8,9, .. Gate line scanning order of .478,479,480 is 1,4,7,10,13,2,5,8,11,14,3,6,9,12,15, ....., 477,480 Gate line It is readjusted in the scanning order and output to the gate line driver 308.

In addition, the driving voltage generator 312 receives a polarity inversion signal PICS for generating a common voltage by inverting the polarity of the electrode every time the gate line is scanned in units of n lines from the timing controller 310. That is, in response to the polarity inversion signal output from the timing controller 310, the driving voltage generator 312 applies voltages having positive polarities to the lines to be scanned, respectively, when n gate lines are scanned. When the next n lines are scanned, the polarity is reversed to apply a negative voltage to the lines being scanned.

In addition, the timing controller 310 sequentially rearranges the input image data signal by a predetermined number of data lines (hereinafter referred to as 'n') at intervals of existing predetermined lines (hereinafter referred to as 'k lines'). To the data line driver 306. The number of times that the data line driver 306 outputs the image data line to the LCD panel 304 in one frame corresponds to the number of gate lines. Therefore, if there are 480 gate lines in total, and the timing controller 310 controls the gate line driver 308 to drive five lines at the three-line intervals described above, the memory in the timing controller 310 The address of the image data stored in 316 is readjusted by five units at three line intervals, so that 1,4,7,10,13,2,5,8,11,14,3,6,9,12 In the order of .15,..., 480, the data is readjusted according to the gate line scanning order and output to the data line driver 306.

The data line driver 306, also called a source driver, is provided with a plurality of data line drivers, and serves to change image data transferred to each pixel in the LCD panel 304 to a predetermined voltage value and output one line at a time. . In more detail, the data line driver 306 stores the digital data output from the timing controller 310 in the data latch unit of the data line driver 306. In addition, in response to a signal for commanding the data to be lowered to the LCD panel 304, a voltage corresponding to each data is selected and transferred to the LCD panel 304.

Therefore, the data line driver 306 transfers the image data to the LCD panel 304 in the order of the image data output from the timing controller 310, so that the image data is output by n lines at substantially k line intervals.

The gate line driver 308, also called a scan line driver, includes a plurality of gate drivers and controls a gate so that image data applied from the data line driver 306 can be transferred to the pixel. Each pixel of the LCD panel 304 is turned on or off by a transistor serving as a switch, and the on / off of the transistor is performed by applying a constant voltage (Von, Voff) to a gate.

The gate line driver 308 receives the gate on enable signal output from the timing controller 310 and sequentially applies the gate on voltage to the gate line in the order of the input lines. Therefore, the gate lines are substantially gated on by n lines at k line intervals.

The gray voltage generator 314 generates a gray voltage equally divided according to the number of bits of the RGB data provided from the graphic processor 350 and provides the gray voltage to the data line driver 306.

The driving voltage generator 312 generates a gate-on voltage Von for turning on the gate of each pixel of the LCD panel 304 and a gate-off voltage Voff for turning off the gate. The common voltage Vcom serving as a reference for the data voltage difference of the transistor of each pixel is also generated and provided to the common electrode of each pixel.

In addition, the driving voltage generator 312 inverts the polarity of the common voltage in response to the polarity inversion control signal PICS output from the timing controller 310.

In the liquid crystal display according to the present invention having the above structure, since the polarity of the common electrode is inverted in units of n lines, power consumption may be greatly reduced as compared to the polarity inversion of lines. In addition, since scanning is performed at k line intervals, the flicker generated by the luminance difference can be reduced to the extent of line inversion.

4 is a block diagram illustrating a timing controller according to the present invention.

Referring to FIG. 4, the timing controller 310 may include an output order of image data input from a graphics processor, that is, a memory scan address generator 402 for generating an address and a line sequential generator for determining a gate-on order of a gate line driver. 404, an address change circuit 406 for rearranging the output order of the image data, a line sequence changer 408 for rearranging the line sequence of the gate driver, and a memory 316 in which the changed address is stored.

The memory scan address generator 402 generates an address for storing image data input from the graphics processor in the memory. In the memory scan address generator 402, addresses are re-arranged by n units at k line intervals through the address change unit 406 and stored in the memory 316 of the timing controller 310. Therefore, image data is stored in the memory 316 according to the changed data output order, and the data is sequentially output through the data line driver 306 by this order.

The line sequential changer 408 rearranges the gate line on sequence generated from the gate driver line sequential generator 404 by n units at k line intervals and outputs the result to the gate line driver 308.

In this case, the address change unit 406 and the line sequential change unit 408 may be internal to the timing controller 310 or may be separately generated outside the timing controller 310.

5 is a diagram illustrating an address changed by the address changer of the present invention.

The address changer 406 receives an address output from the memory scan address generator 402 and readjusts the address in an interlaced manner according to the present invention to output the changed address.

Since the conventional image data output method does not have an address change section, memory scan addresses are generated sequentially, and therefore image data is also sequentially stored in the memory.

Referring to FIG. 5, FIG. 5 is a diagram illustrating addresses realigned in units of three lines at intervals of two lines. The first address generated by the memory scan address generator 402 of FIG. 4 is generated sequentially from 1 to N. FIG. These addresses are rearranged in units of n at intervals of k lines through the address changing unit 406 of FIG. 4 and stored in the memory 316 of the timing controller 310, and the image is changed according to the changed address, that is, the changed data output order. The data is saved.

FIG. 6 is a diagram illustrating an N-line gate line driving using an address changed according to FIG. 5.

The image data of the first line 1 is output to the first data line driver, and at the same time the gate of the first line is turned on. Then, since scanning is performed at two line intervals, image data of the third line 3 is output from the line driver, and the gate line driver turns on the gate of the third line. Next, the image data of the fifth line 5 is output from the line driver, and the gate line driver turns on the gate of the fifth line. After the three lines are scanned, the polarity of the voltage applied to the common electrode of the pixel is inverted by the inversion control signal.

Then, the image data of the second line 20 is output from the data line driver, and at the same time the gate of the second line is turned on. Next, the image data of the fourth line 4 is output from the line driver, and the gate The line driver turns on the gate of the fourth line, and then the image data of the sixth line 6 is output from the line driver, and the gate line driver turns on the gate of the sixth line. After scanning, the polarity of the common voltage is inverted by the inversion control signal.

Then, data of 7 lines, 9 lines, and 11 lines are displayed in turn, and after the polarity of the common voltage is inverted, the data of 8 lines, 10 lines and 12 lines are displayed again in order, and the polarity is repeated.

In the polarity inversion method of the N line unit according to the present invention, since the polarity of the electrode is inverted every scan of the N line, the current consumption is greatly reduced compared to the line inversion (see FIG. 2). For example, when the polarity is reversed in units of three lines as shown in FIG. 6, only a small current of 1.47 mA is consumed.

In addition, since the polarity reversal method in units of N lines according to the present invention scans at intervals of k lines, there is no problem of flicker in which a screen flickers because several neighboring lines are not continuously scanned. That is, since the common electrode is inverted for every one line, the current consumption is reduced by every N lines, and scanning is performed by the interlacing method of k line intervals, so that the effect of one line polarity is obtained, thereby preventing deterioration of image quality such as flicker phenomenon.

The liquid crystal display according to the present invention may be used even when an image is directly input from a CPU, and may also be used when an image data is input through an RGB interface from a graphic source.

7 is a view showing a storage procedure of image data according to an embodiment of the present invention.

Referring to Fig. 7, the storage order of the image data output by the CPU in units of frames is shown.

3 and 7, image data generated by the CPU 354 of FIG. 3 is stored in a frame unit in a memory in the CPU 354. The data sequentially output from the CPU is 1, 3, 5, 3, 4, 6, 7, 9, 11, 8, 10, 12 ... Are stored again in the memory 316 of the liquid crystal display in the order of. The data is transferred to the data line driver in the stored order and output to the liquid crystal panel. On the other hand, the common voltage Vcom is inverted in polarity every three lines are output.

On the other hand, in the memory 316 of the liquid crystal display device, image data output from the CPU is stored in order according to the output order without changing the address, and then the reading order of the image data stored in the memory is changed by the changed address when displaying on the liquid crystal panel. It can also be changed and displayed on a liquid crystal panel.

8 is a diagram showing a storage procedure of image data according to another embodiment of the present invention.

3 and 8 illustrate a storage order of image data output one by one through a RGB interface from a graphic source without storing all the data of one frame. The data output from the graphics source is stored every six lines from the graphics source in a small memory 316 in which one block of the image of three lines in two line intervals, that is, six lines of image data can be stored. do.

That is, when 1 to 6 lines of data are output from the graphic source, they are sequentially stored according to the 1 to 6 line addresses of the memory, and then output to the liquid crystal panel according to the addresses rearranged into 3 lines of 2 line intervals. When all six lines of image data are output in this manner, the next seven to twelve lines of data are output from the graphic source and stored in the one to six line addresses of the memory. Then, they are rearranged to addresses 1, 3, 5, 2, 4, and 6 and output to the liquid crystal panel. In other words, the actual image data output at this time is the image data in the order of 7, 9, 11, 8, 10, 12 lines output from the graphic source.

Meanwhile, when the data sequentially output from the graphic processor is stored in the latch (memory) of the liquid crystal display, the data may be stored in the output order changed by the changed address. In this case, the liquid crystal panel is sequentially displayed in the order stored in the latch.

In such an RGB interface output method, the data of one frame cannot be rearranged all at once, and there is a delay of about three lines because six line image data are received and output in the rearranged order. For example, the fifth line is output fifth in the graphic source, but the third in the data line driver, so the realigned data is delayed by three lines before outputting the data. On the other hand, the polarity of the common voltage Vcom is reversed every time three lines are output.

When using this method, the image data is placed in a very small memory that can store only 6 lines of data without storing all the data of one frame, thereby reducing unnecessary memory size.

Meanwhile, among LCD panels currently on the market, there may be a kind of panel (eg, LTPS or ASG) which cannot control a gate driver. In the case of such a panel, the panel is controlled only by the source driver without the gate driver. Unlike a panel in which a gate driver exists, this type of panel cannot be scanned at intervals on the panel lines because the line scanning of the panel proceeds only in a predetermined direction, and the same method as in the above-described embodiment can be used. none.

Therefore, for the gate-embedded liquid crystal panel, a gate line shift circuit for converting sequential gate scanning to gate scanning having an interval must be incorporated in the panel itself. That is, in the conventional gate-embedded liquid crystal panel, the gate line shift circuit embedded in the panel is designed to sequentially scan the gate lines, whereas in the gate-embedded liquid crystal panel according to the present invention, the gate-line shift circuit embedded in the panel defines the gate line. It is designed to scan with an interval of.

9 is a circuit diagram illustrating a gate line shift circuit of a conventional liquid crystal panel with a built-in gate driver.

Referring to FIG. 9, a gate line shift circuit 900 of a conventional liquid crystal panel includes a plurality of switches 901 to 908 and clock signals CK and CKB for synchronizing a scan of the gate line shift circuit 900. It includes a pair of connected lines.

The clock signal CK is connected to the first switch 901, the third switch 903, the fifth switch 905, and the like, and the inverted clock signal CKB is the second switch 902 and the fourth switch 904. And the sixth switch 906 and the like, and are alternately connected to each switch. Further, when each frame is displayed on the liquid crystal panel, a gate line on signal STV for starting scanning of each gate line is output from the timing controller and input to the first switch 901.

In addition, the gate signal output from each turned-on switch is connected to the previous switch to turn off the previous switch, and also connected to the next switch to turn on the next switch.

10 is a timing diagram of each signal shown in the circuit of FIG.

In FIG. 10, the clock signal CK and the inverted clock signal CKB have inverted phases, and the gate lines are sequentially turned on every time the clock signal transitions. The signal GATE1 is a first gate line control signal output through the first switch, the signal GATE2 is a second gate line control signal output through the second switch, and the signal GATE3 is through a third switch. The third gate line control signal is output.

Referring to FIGS. 9 and 10, the operation of the conventional liquid crystal panel with a built-in gate driver is described. When the clock signal CK is high, the first switch 1001 is turned on and the first gate signal GATE1 is turned high. Transition to level 1002 is performed and data is displayed on the first gate line G1. Then, when the inverted clock signal CKB transitions to the high level (1003), the first gate signal GATE1 turns on the second switch 902 so that the second gate signal GATE2 transitions to the high level. 1004, which causes the first switch 901 to be turned off. Then, data is displayed on the second gate line G2. Then, when the clock signal CK transitions to the high level again (1005), the second gate signal GATE2 turns on the third switch 903 so that the third gate signal GATE3 transitions to the high level. 1006, which causes the second switch 902 to be turned off. Then, data is displayed on the third gate line G3.

Therefore, when the gate driver built-in liquid crystal panel shown in FIG. 9 is used, since the gate lines are sequentially turned on, the interleaved scanning method according to the present invention cannot be used.

11 is a circuit diagram illustrating a gate line shift circuit of a liquid crystal panel with a gate driver according to the present invention.

Referring to FIG. 11, the gate line shift circuit 1100 of the conventional liquid crystal panel includes a plurality of switches 1101 to 1108 and clock signals CK and CKB for synchronizing a scan of the gate line shift circuit 1100. It includes a pair of connected lines.

In this case, the clock signal CK and the inverted clock signal CKB are alternately connected to the switches in the scan order according to the interleaving method. In the embodiment of FIG. 11, since three lines are scanned at two line intervals, the clock signal CK is connected to the first switch 1101, and the inverted clock signal CKB is connected to the third switch 1103. The clock signal CK is connected to the fifth switch 1105, the inverted clock signal CKB is connected to the second switch 1102, the clock signal CK is connected to the fourth switch 1104, and the sixth switch is connected to the fourth switch 1104. The inverted clock signal CKB is connected to the switch 1106. Similarly, the clock signal and the inverted clock signal are connected to the seventh switch to the twelfth switch in the same manner. In addition, when each frame is displayed on the liquid crystal panel, a gate line on signal STV for starting scanning of each gate line is output from the timing controller and input to the first switch 1101.

In addition, the gate signal output from each switch that is turned on is connected to the switch that was turned on the previous clock to turn off the previous switch, and is connected to the switch to be turned on to the next clock to turn on the next switch.

12 is a timing diagram of each signal shown in the circuit of FIG.

In FIG. 12, the clock signal CK and the inverted clock signal CKB have inverted phases as shown in FIG. 10, and gate lines are sequentially turned on every time the clock signal transitions. In addition, each gate signal GATE1 to GATE8 is a signal output from each switch 1101 to 1108 to the gate line of the liquid crystal panel. When the gate signal is at the high level, the corresponding gate line is turned on, and the corresponding Source data is displayed on the gate line.

Referring to FIGS. 11 and 12, the operation of the liquid crystal panel with the gate driver according to the present invention will first be described. First, when the clock signal CK is high, the first switch 1101 is turned on and thus the first gate line signal GATE1. ) Becomes a high level, and data is displayed on the first gate line G1. Then, when the inverted clock signal CKB transitions to the high level, the third switch 1103 connected to the first gate signal GATE1 is turned on and the first switch 1101 is turned off. At this time, the third gate signal GATE3 becomes high and data is displayed on the third gate line G3. Then, when the clock signal CK transitions to the high level again, the fifth switch 1105 connected to the third gate signal GATE3 is turned on and the third switch 1103 is turned off. At this time, the fifth gate signal GATE5 becomes high and data is displayed on the fifth gate line G5.

Then, when the inverted clock signal CKB transitions to the high level, the second switch 1102 connected to the fifth gate signal GATE5 is turned on and the fifth switch 1105 is turned off. At this time, the second gate signal GATE2 becomes high and data is displayed on the second gate line G2. Then, when the clock signal CK transitions to the high level, the fourth switch 1104 connected to the second gate signal GATE2 is turned on and the second switch 1102 is turned off. At this time, the fourth gate signal GATE4 becomes high and data is displayed on the fourth gate line G4. Then, when the inverted clock signal CKB transitions to the high level, the sixth switch 1106 connected to the fourth gate signal GATE4 is turned on and the fourth switch 1104 is turned off. At this time, the sixth gate signal GATE6 becomes high and data is displayed on the sixth gate line G6.

Then, when the clock signal CK becomes high again, the gate lines are sequentially turned on in the same manner as described above from the seventh gate line G7 to the twelfth gate line G12.

The order in which the gate lines are scanned by the gate line shift circuit 1100 according to the present invention is indicated by a square next to the right gate line of FIG.

In this case, the polarity of the common voltage Vcom is inverted whenever three lines are output. That is, when the three gate lines of the first gate line, the third gate line, and the fifth gate line are sequentially turned on, the common voltage Vcom has a positive polarity, and the second gate line, the fourth gate line, and the third gate line. When the three gate lines of the six gate lines are sequentially turned on, the common voltage is negative. The same applies to the next gate line, and when the next frame is displayed, a common voltage having a polarity opposite to that of the previous frame is applied to prevent deterioration of the display device.

Therefore, when the gate line shifter circuit according to the exemplary embodiment of the present invention shown in FIG. 11 is used, even in the case of a liquid crystal panel with a gate driver, interleaved gate line scanning is possible.

In FIGS. 11 and 12, an interleaving method in which a common voltage having the same polarity is applied every three lines at two line intervals is disclosed, but in general, a common voltage having the same polarity is applied in predetermined n line units at predetermined k line intervals. In the case of the method, the gate line shift circuit of the liquid crystal panel may be designed and implemented so that the gate line shift circuit of the liquid crystal panel may be scanned in an interleaved order of n lines of k line intervals in a similar manner to the above-described embodiment.

Of course, at this time, the source driver of the liquid crystal panel rearranges the scan order in the same manner as in the embodiment in which the gate driver is separately provided.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. . Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

According to the liquid crystal display according to the present invention, the inversion of the common electrode for each line is changed for every N lines to reduce the current consumption, and a very small size of memory is inserted to latch the data of each line into the memory so that the k lines are spaced. Scanning is performed using the interlacing method, so that the effect of one-line polarity is obtained, thereby reducing power consumption and preventing deterioration of image quality such as flicker.

Claims (21)

In a liquid crystal panel with a built-in gate driver, A plurality of pixels formed in an area where the plurality of gate lines and the plurality of data lines cross each other; And In response to a gate line on signal input from a timing controller outside the liquid crystal panel, the gate line of the liquid crystal panel is sequentially scanned in a predetermined k-line interval in an interleaved manner by n predetermined gate lines. A gate line shift circuit for setting the scan order of the lines, And the liquid crystal panel displays the source data output from an external source driver in the interleaved gate line scan order set by the gate line shift circuit. The method of claim 1, The gate line shift circuit sequentially scans the gate lines of the liquid crystal panel by the n lines at the k line intervals, and, when the scanning of the n lines is completed, the k line intervals from neighboring lines of the scanning completed gate lines. Scans the next n lines, and when the scanning of the k * n gate line blocks is completed, the scanning of the neighboring k * n gate line blocks is repeated to complete scanning of one frame. The method of claim 1, Wherein the liquid crystal panel inverts the polarity of the gate electrode whenever the liquid crystal panel finishes scanning the n gate lines. The method of claim 3, wherein The n lines are three lines, and the interval of the k lines is an interval of two lines, The gate line shift circuit scans 2k + 1 (k is an integer) three lines sequentially and then scans 2kth lines three sequentially. Wherein the liquid crystal panel inverts the polarity of the gate electrode every time the three gate lines are scanned. The method of claim 4, wherein The gate line shift circuit includes a plurality of gate line switch blocks formed of six units operating in synchronization with a clock signal and an inverted clock signal, and each gate line switch is connected to a corresponding gate line. The first gate line switch of the first switch block is controlled by an externally input gate line on signal, and the first gate line switch of the next switch block is controlled by a signal of the last gate line of the previous switch block. Liquid crystal panel. The method of claim 5, Each of the switch blocks may include a first switch corresponding to a first gate line, a second switch corresponding to a second gate line, a third switch corresponding to a third gate line, a fourth switch corresponding to a fourth gate line, A fifth switch corresponding to the fifth gate line and a sixth switch corresponding to the sixth gate line, The first switch is turned on in response to the clock signal and the gate line on signal or the output signal of the last switch of the previous switch block, and is turned off in response to the output signal of the third switch, The second switch is turned on in response to the output signal of the inverted clock signal and the fifth switch, turned off in response to the output signal of the fourth switch, The third switch is turned on in response to the inverted clock signal and the output signal of the first switch, turned off in response to the output signal of the fifth switch, The fourth switch is turned on in response to the clock signal and the output signal of the second switch, and is turned off in response to the output signal of the sixth switch, The fifth switch is turned on in response to the clock signal and the output signal of the third switch, is turned off in response to the output signal of the second switch, And the sixth switch is turned on in response to the inverted clock signal and the output signal of the fourth switch, and is turned off in response to the output signal of the first switch of the next switch block. The method of claim 6, The gate line shift circuit may include six gate lines within each switch block in the first gate line, the third gate line, the fifth gate line, the second gate line, the fourth gate line, and the sixth gate line. A liquid crystal panel characterized by scanning in an interleaving manner of a sequence of gate lines. The method of claim 5, And the inverted clock signal is an inverted signal of the clock signal. In a gate line shift circuit that specifies a scanning order of gate lines in a liquid crystal panel having a gate driver embedded therein, And a gate line shift circuit configured to scan the gate lines of the liquid crystal panel in an overlapping block-wise fashion that implements non-contiguous blocks of lines. The method of claim 9, The gate line shift circuit, A gate of the liquid crystal panel so as to sequentially scan the gate lines of the liquid crystal panel at predetermined k line intervals in an interleaved manner of n gate lines in response to a gate line on signal input from a timing controller external to the liquid crystal panel; And a gate line shift circuit configured to set a scan order of the lines. The method of claim 10, The gate line shift circuit sequentially scans the gate lines of the liquid crystal panel by the n lines at intervals of the k lines, and when the scan of the n lines is completed, the k lines in the neighboring lines of the gate lines where the scanning is completed. Scan the next n lines at intervals, and when the scanning of the k * n gate line blocks is completed, the scanning of the neighboring k * n gate line blocks is repeated to complete scanning of one frame. The method of claim 11, The n lines are three lines, and the interval of the k lines is an interval of two lines, And the gate line shift circuit is configured to repeat scanning three 2k + 1 (k is an integer) lines in sequence and three scanning the 2k lines in sequence. The method of claim 12, The gate line shift circuit includes a plurality of gate line switch blocks formed of six units operating in synchronization with a clock signal and an inverted clock signal, and each gate line switch is connected to a corresponding gate line. The first gate line switch of the first switch block is controlled by an externally input gate line on signal, and the first gate line switch of the next switch block is configured to be controlled by the signal of the last gate line of the previous switch block. A gate line shift circuit. The method of claim 13, Each of the switch blocks may include a first switch corresponding to a first gate line, a second switch corresponding to a second gate line, a third switch corresponding to a third gate line, a fourth switch corresponding to a fourth gate line, A fifth switch corresponding to the fifth gate line and a sixth switch corresponding to the sixth gate line, The first switch is turned on in response to the clock signal and the gate line on signal or the output signal of the last switch of the previous switch block, and is turned off in response to the output signal of the third switch, The second switch is turned on in response to the output signal of the inverted clock signal and the fifth switch, turned off in response to the output signal of the fourth switch, The third switch is turned on in response to the inverted clock signal and the output signal of the first switch, turned off in response to the output signal of the fifth switch, The fourth switch is turned on in response to the clock signal and the output signal of the second switch, and is turned off in response to the output signal of the sixth switch, The fifth switch is turned on in response to the clock signal and the output signal of the third switch, is turned off in response to the output signal of the second switch, And the sixth switch is turned on in response to the inverted clock signal and the output signal of the fourth switch, and is turned off in response to the output signal of the first switch of the next switch block. The method of claim 14, The gate line shift circuit may include six gate lines within each switch block in the first gate line, the third gate line, the fifth gate line, the second gate line, the fourth gate line, and the sixth gate line. And the gate line shift circuit is configured to scan in an interleaved manner of the order of the gate lines. The method of claim 13, And the inverted clock signal is an inverted signal of the clock signal. A plurality of pixels formed in an area where the plurality of gate lines and the plurality of data lines cross each other, and A gate of the liquid crystal panel so as to sequentially scan the gate lines of the liquid crystal panel at predetermined k line intervals in an interleaved manner of n gate lines in response to a gate line on signal input from a timing controller external to the liquid crystal panel; A liquid crystal panel including a gate line shift circuit for setting a scan order of lines; Receives image data from a graphic source, rearranges the scanning order of the image data in predetermined n line units at predetermined k line intervals, and sequentially scans in predetermined n gate line units at the predetermined k line intervals. A timing controller configured to output a gate line on signal to generate an inversion control signal applied in the n line periods; A source driver which selects a gray voltage to be applied to each pixel of the liquid crystal panel according to the image data input from the timing controller and outputs the gray voltage to the liquid crystal panel; And A voltage generator for generating and outputting a gray voltage required for the source driver, and inverting a polarity of a common voltage applied to each pixel of the liquid crystal panel in response to the inversion control signal, And the liquid crystal panel displays the source data output from the source driver in the order of the interleaved gate line scan set in the gate line shift circuit. The liquid crystal display device of claim 17, wherein And an address changer for repeatedly rearranging memory addresses in the n-th unit at the k-line intervals. The method of claim 17, The gate line shift circuit sequentially scans the gate lines of the liquid crystal panel by the n line intervals at the k line intervals, and when the scanning of the n lines is completed, the k lines in the neighboring lines of the gate lines where the scanning is completed. Scan the next n lines at intervals, and when the scanning of the k * n gate line blocks is completed, scanning of the neighboring k * n gate line blocks is repeated to complete scanning of one frame. The method of claim 17, And wherein the inversion control signal is inverted in polarity whenever scanning of the n gate lines of the liquid crystal panel is completed. The method of claim 17, The gate line shift circuit includes a plurality of gate line switch blocks formed of six units operating in synchronization with a clock signal and an inverted clock signal, and each gate line switch is connected to a corresponding gate line. The first gate line switch of the first switch block is controlled by the externally input gate line on signal, the first gate line switch of the next switch block is controlled by the signal of the last gate line of the previous switch block, Each switch block may include a first switch corresponding to a first gate line, a second switch corresponding to a second gate line, a third switch corresponding to a third gate line, and a fourth switch corresponding to a fourth gate line. A fifth switch corresponding to the fifth gate line and a sixth switch corresponding to the sixth gate line, The first switch is turned on in response to the clock signal and the gate line on signal or the output signal of the last switch of the previous switch block, and is turned off in response to the output signal of the third switch, The second switch is turned on in response to the output signal of the inverted clock signal and the fifth switch, turned off in response to the output signal of the fourth switch, The third switch is turned on in response to the inverted clock signal and the output signal of the first switch, turned off in response to the output signal of the fifth switch, The fourth switch is turned on in response to the clock signal and the output signal of the second switch, and is turned off in response to the output signal of the sixth switch, The fifth switch is turned on in response to the clock signal and the output signal of the third switch, is turned off in response to the output signal of the second switch, And the sixth switch is turned on in response to the inverted clock signal and the output signal of the fourth switch, and is turned off in response to the output signal of the first switch of the next switch block.

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