TWI417858B - Driving method and apparatus for driving tft-lcd - Google Patents

Description

Driving method and device for thin film transistor liquid crystal display

The present invention relates to a driving method of a thin film transistor liquid crystal display, and more particularly to dividing a panel into a plurality of regions and generating a specific scanning sequence for the regions.

The liquid crystal display uses an electric field applied to the liquid crystal material to change its rotation angle to control the color and brightness of the pixel.

Each pixel of the liquid crystal display panel has a pixel transistor, and the gate of the pixel transistor is connected to the gate line controlled by the gate driving integrated circuit; the source is integrated with the source driving body. The data lines controlled by the circuit are connected; and the drain is connected to the pixels. Each of the above pixels has a common electrode to apply a common voltage. The gate drive integrated circuit applies a voltage to the gate line in a certain order to activate the entire column of pixel transistors on the gate line; the order in which the gate line applies voltage is the scan order of the panel. The source drives the integrated circuit to apply a voltage to the data line; the drain of the activated pixel transistor is based on the voltage supplied to the source by the data line, and reacts a liquid crystal material biased to the pixel to control the output color of the pixel. With brightness.

The voltage difference experienced by the liquid crystal material is the voltage of the pixel transistor, the voltage supplied to the pixel electrode, and the common voltage of the common electrode, and the difference between the two voltages. The electric field induced by the voltage difference drives the angle at which the liquid crystal molecules rotate to determine the intensity of the backlight source passing through the pixel. Since the liquid crystal molecules maintain a fixed angle for a long time, passivation occurs, so the molecule must be periodically inverted to extend the life of the liquid crystal panel. The reverse operation can be achieved by using the difference between the positive and negative voltage differences.

As the industry progresses, the size of the panel increases, the resolution increases, and the explicit image evolves from a plane to a solid. At the same time, it is necessary to increase the number of gate lines and increase the frame rate from 60 Hz to 120 Hz.

For the above reasons, the turn-on time of the gate line becomes shorter. If the scanning mode of the panel is still scanned by the first gate line above the panel to the last gate line below the panel, the connection time of the gate line is too short, and the liquid crystal material is too late to react. , produces ghosting phenomenon.

In order to solve this problem, a large voltage can be used to drive the gate line under the panel, in an attempt to speed up the reaction speed of the liquid crystal. However, the gate connection time of the area below the panel is too short, and this method still cannot effectively solve the problem.

Recently, the industry has used a dual scan to divide the picture into upper and lower parts and scan at the same time, which can increase the reaction time of the liquid crystal material by a factor of two. This method can be combined with the liquid crystal inversion technique to make the adjacent gate lines or adjacent pixels have opposite liquid crystal polarities (ie, the positive and negative voltage differences applied to the liquid crystal material) in one picture time.

The dual scanning of the cooperative liquid crystal inversion technique divides the picture into upper and lower parts, and generally scans the same direction from the first gate of the two parts to the last gate at the same time. However, this method will cause uneven brightness and streaks at the junction between the upper and lower parts.

Therefore, an effective method is needed to solve the problem of uneven brightness of the above various panels.

The invention provides a liquid crystal scanning system and method, which is characterized in that a signal generated by two sets of digital logic circuits is received by a gate driving integrated circuit to generate a scan which is not in accordance with the spatial arrangement of the gate lines. This method can keep the panel brightness uniform while increasing the number of gate lines and increasing the frame rate.

The two sets of signals are respectively operated by a signal generated by a gate signal generating module 120 and a gate clock signal generating module 120.

Based on the above objective, the present invention provides a driving device for a liquid crystal display, comprising: a plurality of gate driving integrated circuits, each corresponding to a plurality of regions of the liquid crystal display; and a gate clock signal generating module, an output gate clock The signal is applied to the complex gate driving integrated circuit to scan the complex region in a non-sequential manner, wherein the gate clock signal generating module comprises a gate line designated pulse generating module and a partial clock signal selecting module. The gate line designation pulse generation module outputs a first signal to the segment clock signal selection module to specify a gate line to be scanned. The branch clock signal selection module receives the first signal output by the gate line designation pulse generation module, generates a second signal to the complex gate drive integrated circuit, and scans the designated scan gate in a non-sequential manner line.

A further object of the present invention is to provide a scanning method for a liquid crystal display, comprising: defining a picture as a complex area; each of the plurality of areas is defined as a plurality of parts; in the plurality of areas, each of the plurality of areas Corresponding gate driving integrated circuit is configured to determine a gate line scanning sequence of the plurality of regions; wherein each of the plurality of regions scans only one gate line at a time, and after scanning a region for a first specific number of times, Jump to another area, but the first specific number of times must be less than or equal to the number of parts; after each area is scanned for the first specific number of times, the scanning process is repeated, and the gate line is scanned in space The aiming sequence is not sequential. Each of them scans only one gate line at a time, and after scanning a second specific number of times, jumps to another part, but the second specific number of times must be less than or equal to the number of all gate lines in the part; each part After scanning the second specific number of times, the scanning process is repeated.

The invention cuts the liquid crystal display panel into a plurality of regions, and proposes a special sequential scanning method, in which the different regions of the panel are scanned in a specific order, the scanning timing of the panel is dispersed to the entire screen, and the response of the liquid crystal is dispersed. The brightness distribution of the panel is more uniform and the ghost phenomenon is improved. The scanning method also considers the inversion period of the liquid crystal molecules to delay the degradation effect of the liquid crystal molecules, so that it can also lengthen the service life of the panel. Features of the present invention will be apparent from the following description.

Various changes and modifications of the embodiments are obvious to those skilled in the art in the scope of the present invention. Specific examples are for illustrative purposes only and are not enumerated.

The present invention relates to a liquid crystal scanning system and method. In order to achieve the above functions and purposes, various signal waveforms and circuit system diagrams will be provided in the following pages, and the scanning mode will be described.

In one embodiment, referring to FIG. 1, the liquid crystal scanning system of the present invention comprises: a special application integrated circuit 100, a gate clock signal generating module 120, a gate signal pulse delay module 130, and a source. The pole drive integrated circuit 201, the at least one gate drive integrated circuit 202, and a liquid crystal display panel (not shown). The gate clock signal generating module includes a gate line generating pulse generating module 121 (GD impulse generate moudule) and a partial clock signal selecting module 122 (CLK1/2 select moudule). The special application integrated circuit includes: a low voltage differential signal receiver 111 (LVDS receiver), an over data processor 112 (OD/data processor), a column buffer 113 (line buffer), and a data resetter 114 ( Data Re-mapping, an Oscillator (OSC) and a Timing Controller 116, the operation of which will be set forth below.

In one embodiment, the special application integrated circuit receives a low voltage differential signal (LVDS) and a fundamental frequency (CLK). The signal receiver 111 receives the low voltage differential signal, and then outputs the signal to the overfeed data processor 112. The column buffer 113 and the data resetter 114 output a source data signal (S Data). After receiving the low voltage differential signal, the receiver connection 111 also outputs a source data write signal (Data Enable, DE) to the time controller 116. The time controller 116 receives the source data write signal (DE), the fundamental frequency (CLK), and the output signal of the oscillator 116 (OSC) to generate a liquid crystal inversion signal (POL), the gate integrated circuit main trigger clock. Signal (CLKm) and source integrated circuit main trigger clock signal (CLKH), gate split control signal (Up/down of GD), start operation signal (GD SEL), and gate signal pulse (GSP).

The source driving integrated circuit receives the source data signal (S Data), the liquid crystal inversion signal (POL), and the source integrated circuit main trigger clock signal (CLKH) to control the data line.

According to the invention, the panel scan line is divided into a plurality of regions, and each of the plurality of gate drive integrated circuits is correspondingly controlled to respectively control the gate opening state of the pixel transistor, and the gate pulse signal pulse is additionally used in each region (GSP1/ 2 GD) signal to open different segments corresponding to each region, such as the upper half or lower half of each region. Therefore, the present invention utilizes the gate clock signal generation module 120 to receive the gate trigger circuit main trigger clock signal (CLKm), the start operation signal (GD SEL), and the gate division control signal (Up/down of GD). Scan the signal sequentially. The gate line specifies the gate line designation signal (GDS) generated by the pulse generation module 121, which will specify the gate line to be scanned. The time controller 116 refers to the gate segment signal pulse (GSP1/2 GD) signal, the output gate segment control signal (Up/down of GD) to the segment clock signal selection module 122, and the segment clock signal selection module. 122 receiving a gate line designation signal (GDS) and a gate division control signal (Up/down of GD), generating a gate segmentation clock signal (CLK1/2 GD) recognizable by the gate drive integrated circuit 202, Specify the division and gate lines of the scan area.

Based on the above features, the gate clock signal generating module 120 receives the gate integrated circuit main trigger clock signal (CLKm), the gate split control signal (Up/down of GD), and the start operation signal (GD SEL). After the gate pulse designation module 121 and the segment clock signal selection module 122 are operated, a gate segment clock signal (CLK1/2 GD) is generated; the gate signal pulse delay module 130 receives the gate collector product. The main circuit main trigger clock signal (CLKm) and the gate signal pulse (GSP) are processed to generate a gate sub-signal pulse (GSP1/2 GD). The gate drive integrated circuit 202 receives the gate divided clock signal (CLK1/2 GD) and the gate divided signal pulse (GSP1/2 GD) to generate a special scan sequence. The liquid crystal scanning method provided by the present invention uses the liquid crystal scanning system of the above embodiment. The scanning method is as follows.

The gate line of the liquid crystal panel of the present invention is diced into a singular or plural area, each of which has a separate gate drive integrated circuit 202 to determine the gate line scan order of the area.

In a preferred embodiment, the gate line of the liquid crystal panel is cut into three regions, as shown in FIG. In these three regions, the scanning sequence of the gate lines is controlled by the gate clock signal generating module 120 and the gate signal pulse delay module 130. It should be noted that although the examples of the present invention are three regions, the number of the intervals may be arbitrarily changed without departing from the spirit of the present invention.

As shown in FIG. 3, in the gate clock signal generation module 120, the gate line designation pulse generation module 121 receives the gate trigger circuit main trigger clock signal (CLKm) and the start operation signal (GD SEL), and performs an operation. Thereafter, a gate line designation signal (GDS) is generated, which is a first gate line designation signal (GDS1), a second gate line designation signal (GDS2), and a third gate line designation signal (GDS3), respectively. The type is shown in Figure 4. The sub-clock signal selection module 122 receives the three gate line designation signals (GDS) and the corresponding gate sub-section control signal (Up/down of GD), that is, the first gate sub-section control signal. (Up/down of GD1), second gate control signal (Up/down of GD2) and third gate control signal (Up/down of GD3), the waveform of which is shown in Figure 4. After the operation, a gate divided clock signal (CLK1/2 GD) is generated. The first gate upper clock signal (CLK1/GD1), the first gate lower clock signal (CLK2/GD1), the second gate upper clock signal (CLK1/GD2), and the second gate lower clock signal ( CLK2/GD2), the third gate upper clock signal (CLK1/GD3) and the third gate lower clock signal (CLK2/GD3), the waveform of which is shown in Figure 4. The sub-portion and the gate line of the scan area are explicitly specified by the above-mentioned gate-segment clock signals (CLK1/2 GD), and a non-sequential scan procedure is generated.

As shown in FIG. 5, the gate signal pulse delay module 130 includes a plurality of, for example, five delays. The first delay 501 extends the square wave of the main trigger clock signal (CLKm) of the six gate integrated circuits, the second delay 502 extends the main trigger clock signal of the gate integrated circuit (CLKm), and the third wave The delay 503 extends the six gate integrated circuit main trigger clock signal (CLKm) square wave, the fourth delay 504 extends a gate integrated circuit main trigger clock signal (CLKm) square wave, and the fifth delay 505 The six-gate integrated circuit main trigger clock signal (CLKm) square wave is extended. The module 130 receives the main trigger clock signal (CLKm) and the gate signal pulse (GSP) of the gate integrated circuit, and after the operation, generates a gate split signal pulse (GSP1/2 GD), which is respectively the first gate Very upper signal pulse (GSP1/GD1), first gate lower signal pulse (GSP2/GD1), second gate upper signal pulse (GSP1/GD2), second gate lower signal pulse (GSP2/GD2), The three-gate upper signal pulse (GSP1/GD3) and the third gate lower signal pulse (GSP2/GD3) have a waveform as shown in Fig. 6.

The gate drive integrated circuit receives the gate segment clock signal (CLK1/2 GD) and the gate segment signal pulse (GSP1/2 GD) to generate a specific scan sequence. While the gate driving integrated circuit 202 controls the gate line scanning, the source driving integrated circuit 201 receives the source liquid crystal inversion signal (POL) to determine the polarity of the liquid crystal located on the entire gate line. For the following embodiments, the voltage of the pixel transistor is provided at the pixel electrode, and the difference between the two voltages is positive with respect to the common voltage of the common electrode, and is represented by “+”; the difference between the two voltages is When the value is negative, it is represented by "-".

In one embodiment, the panel has, for example but not limited to, 1080 gate lines. As shown in FIG. 2, the panel is cut into three zones, and the first gate integrated circuit (GD1) controls the scanning order of the first gate line (G1) to the 360th gate line (G360). The 360 gate lines are defined as a first region (Zone 1); the second gate integrated circuit (GD2) controls a scanning order of the 361th gate line (G361) to the 720th gate line (G720). The 360 gate lines are defined as a second region (Zone 2); the third gate integrated circuit (GD3) controls the scanning order of the 721th gate line (G721) to the 1080th gate line (G1080). This 360 gate line is defined as the third zone (Zone 3). Each of the four gate lines is defined as a set, and the first 45 groups of each zone are defined as the upper half of the zone; that is, the first gate integrated circuit 2021 is managed. The first group (S1/GD2) to the 45th group (S45/GD1) and the second gate integrated circuit 2022 are managed by the first group (S1/GD2) to the 45th group (S45/GD2) and the third group. The first group (S1/GD3) to the 45th group (S45/GD3) managed by the gate integrated circuit 2023. And 45 groups after each zone are defined as the lower half of the zone; that is, the 46th group (S46/GD1) to the 90th group (S90/GD1) managed by the first gate integrated circuit 2021. The 46th group (S46/GD3) managed by the 46th group (S46/GD2) to the 90th group (S90/GD2) and the third gate integrated circuit 2023 managed by the second gate integrated circuit 2022 To the 90th group (S90/GD3).

In an embodiment, the specific scanning sequence is called 1 line inversion, and the scanning sequence is as shown in Table 1. The rules are as follows (the priority order of this rule is (1), (2) , (3), (4), (5)):

(1) Principle between area and area: Scan in the order of the first area (Zone 1), the second area (Zone 2) and the third area (Zone 3), scanning only one gate line at a time. After scanning an area once, skip to the next area. After scanning three times, that is, after scanning from the first area (Zone 1) to the third area (Zone 3), returning to the first area (Zone 1), repeating the scanning sequence until the entire panel is scanned (1080 lines) ) The gate line.

(2) Principles between the department and the department: first scan the upper half twice, then scan the lower half twice, and scan only one gate line at a time. After scanning four times, that is, after scanning from the upper half to the lower half, return to the upper half and repeat the scanning sequence until the entire area is scanned.

(3) The principle between group and group: The first half of the group (Set) scans the group with the smallest number (that is, starting from the first group), and only scans one gate line at a time. After scanning the complete set (Set), the number of groups is smaller than the group size (ie, scanning from the first group to the 45th group) until the entire upper half is scanned. The lower half of the set (Set) first scans the largest number of groups (ie starting from the 90th group), scanning only one gate line at a time. After scanning the complete set (Set), the number of groups is larger to the smaller number of groups (ie, scanning from the 90th group to the 46th group) until the entire upper half is scanned.

(4) Principles within the group: Since there are 4 gate lines in each group, for the convenience of explanation, the number of curves with the largest number of curves to G1, Gm+1, G m+2 and G are respectively defined. m+3, only one gate line is scanned at a time. The upper half of the set has the scan order of first scanning Gm, then Gm+1, then G m+2, and finally G m+3. Taking the first group (S1/GD1) of the first zone (Zone 1) as an example, the scanning sequence is first scanning G1, then G2, then G3, and finally G4. The lower half of the set has a scan order of first scanning Gm+2, then Gm+3, then Gm, and finally Gm+1. Taking the 90th group (S90/GD1) of the first zone (Zone 1) as an example, the scanning sequence is first scanning G359, then G360, then G357, and finally G358.

(5) Liquid crystal polarity reversal rule: only one gate line is scanned at a time, and the polarity of the liquid crystal is inverted once every three times.

In another embodiment, the specific scanning sequence is called 2 line inversion, and the scanning sequence is as shown in Table 2. The rules are as follows (the priority order of this rule is (1), ( 2), (3), (4), (5)):

(1) Principle between area and area: Scan in the order of the first area (Zone 1), the second area (Zone 2) and the third area (Zone 3), scanning only one gate line at a time. After scanning an area once, skip to the next area. After scanning three times, that is, after scanning from the first area (Zone 1) to the third area (Zone 3), returning to the first area (Zone 1), repeating the scanning sequence until the entire panel is scanned (1080 lines) ) The gate line.

(2) Principles between the department and the department: first scan the upper half twice, then scan the lower half twice, and scan only one gate line at a time. After scanning four times, that is, after scanning from the upper half to the lower half, return to the upper half and repeat the scanning sequence until the entire area is scanned.

(3) The principle between group and group: The first half of the group (Set) scans the group with the smallest number (that is, starting from the first group), and only scans one gate line at a time. After scanning the complete set (Set), the number of groups is smaller than the group size (ie, scanning from the first group to the 45th group) until the entire upper half is scanned. The lower half of the set (Set) first scans the largest number of groups (ie starting from the 90th group), scanning only one gate line at a time. After scanning the complete set (Set), the number of groups is larger to the smaller number of groups (ie, scanning from the 90th group to the 46th group) until the entire upper half is scanned.

(4) Principles within the group: Since there are 4 gate lines in each group, for the convenience of explanation, the definition from the small number of lines to the large number of lines is Gm, Gm+1, G m+2 and G m+3, only one gate line is scanned at a time. The upper half of the set has the scan order of first scanning Gm, then Gm+2, then G m+1, and finally G m+3. Taking the first group (S1/GD1) of the first zone (Zone 1) as an example, the scanning sequence is first scanning G1, then G3, then G2, and finally G4. The lower half of the set has a scanning order of first scanning Gm+1, then Gm+3, then Gm, and finally Gm+2. Taking the 90th group (S90/GD1) of the first zone (Zone 1) as an example, the scanning sequence is first scanning G358, then G360, then G357, and finally G359.

(5) Liquid crystal polarity reversal rule: only one gate line is scanned at a time, and the polarity of the liquid crystal is inverted once every three times.

In another embodiment, the specific scanning sequence is called 1+2 line inversion, and the scanning sequence is as shown in Table 3. The rules are as follows (the priority of this rule is ( 1), (2), (3), (4), (5)):

(1) Principle between area and area: Scan in the order of the first area (Zone 1), the second area (Zone 2) and the third area (Zone 3), scanning only one gate line at a time. After scanning an area once, skip to the next area. After scanning three times, that is, after scanning from the first area (Zone 1) to the third area (Zone 3), returning to the first area (Zone 1), repeating the scanning sequence until the entire panel is scanned (1080 lines) ) The gate line.

(2) Principles between the department and the department: first scan the upper half twice, then scan the lower half twice, and scan only one gate line at a time. After scanning four times, that is, after scanning from the upper half to the lower half, return to the upper half and repeat the scanning sequence until the entire area is scanned.

(3) The principle between group and group: The first half of the group (Set) scans the group with the smallest number (that is, starting from the first group), and only scans one gate line at a time. After scanning the complete set (Set), the number of groups is smaller than the group size (ie, scanning from the first group to the 45th group) until the entire upper half is scanned. The lower half of the set (Set) first scans the largest number of groups (ie starting from the 90th group), scanning only one gate line at a time. After scanning the complete set (Set), the number of groups is larger to the smaller number of groups (ie, scanning from the 90th group to the 46th group) until the entire upper half is scanned.

(4) Principles within the group: Since there are 4 gate lines in each group, for the convenience of explanation, the definition from the small number of lines to the large number of lines is Gm, Gm+1, G m+2 and G m+3, only one gate line is scanned at a time. In the upper half of the set, the scan sequence is first scan Gm, then Gm+1, then G m+3, and finally G m+2. Taking the first group (S1/GD1) of the first zone (Zone 1) as an example, the scanning sequence is first scanning G1, then G2, then G4, and finally G3. The lower half of the set has a scan order of first scanning Gm+3, then Gm+2, then Gm, and finally Gm+1. Taking the 90th group (S90/GD1) of the first zone (Zone 1) as an example, the scanning sequence is first scanning G360, then G359, then G357, and finally G358.

(5) Liquid crystal polarity reversal rule: only one gate line is scanned at a time, and the polarity of the liquid crystal is inverted once every three times.

Since the gate clock signal generating module 120, the gate signal pulse delay module 130 and the gate driving integrated circuit are all digital logic circuits, in addition to the three scanning sequences exemplified in the embodiment, in the present invention Under the idea of dispersing the scan timing to the entire screen, there are still many other different partitions, divisions, grouping methods and scan order designs, which will not be repeated here.

Many variations can be made by those skilled in the art in light of the concept and spirit of the invention. The above embodiments and specific examples are for illustrative purposes only and are not intended to be exhaustive.

100‧‧‧Special application integrated circuit

111‧‧‧Low-voltage differential signal receiver

112‧‧‧Overactive data processor

113‧‧‧ column buffer

114‧‧‧Data Resetter

115‧‧‧ oscillator

116‧‧‧Time controller

120‧‧‧ gate clock signal generation module

121‧‧‧gate line specified pulse generation module

122‧‧‧ Division Clock Signal Selection Module

130‧‧‧gate signal pulse delay module

200‧‧‧LCD panel

201‧‧‧Source Drive Integrated Circuit

202‧‧‧Gate drive integrated circuit

2021‧‧‧First gate drive integrated circuit

2022‧‧‧Second gate drive integrated circuit

2023‧‧‧3rd gate drive integrated circuit

501‧‧‧First retarder

502‧‧‧second retarder

503‧‧‧3rd retarder

504‧‧‧4th retarder

505‧‧‧5th retarder

Figure 1 is a schematic diagram of the driving circuit system of the present invention

Figure 2 is a schematic view of the driving method of the present invention for cutting a panel in three regions

Figure 3 is a schematic diagram of the circuit of the gate clock signal generation module.

Figure 4 is the waveform diagram of the relevant signal processed by the gate clock signal generation module.

Figure 5 is a schematic diagram of the circuit of the gate signal pulse delay module.

Figure 6 is the waveform diagram of the relevant signal processed by the gate signal pulse delay module.

200. . . LCD panel

201. . . Source drive integrated circuit

2021. . . First gate drive integrated circuit

2022. . . Second gate driving integrated circuit

2023. . . Third gate drive integrated circuit

Claims (5)

A scanning method for a liquid crystal display, comprising: defining a picture as a plurality of regions; each of the plurality of regions is defined as a plurality of portions; wherein each of the plurality of regions is configured with a corresponding gate driver An integrated circuit for determining a gate line scanning sequence of the plurality of regions; wherein each of the plurality of regions scans only one gate line at a time, and after scanning a region for a first specific number of times, jumping to another region, but The first specific number of times must be less than or equal to the number of parts; after each area is scanned for the first specific number of times, the scanning process is repeated, and the scan order of the gate lines in the spatial arrangement is not sequential. The scanning method of the liquid crystal display according to claim 1, wherein each part scans only one gate line at a time, and after scanning a second specific number of times, jumps to another part, but the special part The second specific number must be less than or equal to the number of all gate lines in the part; after each part is scanned for the second specific number of times, the scanning process is repeated. The scanning method of the liquid crystal display according to claim 1, wherein the polarity of the liquid crystal is inverted once per scan for a specific number of gate lines. The scanning method of the liquid crystal display according to claim 1, wherein each of the plurality of regions is scanned, and the polarity of the liquid crystal is inverted once. The scanning method of the liquid crystal display according to claim 1, wherein each of the plurality of portions is scanned, and the polarity of the liquid crystal is inverted once.