KR20070098335A - Method for fabricating the same of semiconductor device - Google Patents

Method for fabricating the same of semiconductor device Download PDF

Info

Publication number
KR20070098335A
KR20070098335A KR1020060029855A KR20060029855A KR20070098335A KR 20070098335 A KR20070098335 A KR 20070098335A KR 1020060029855 A KR1020060029855 A KR 1020060029855A KR 20060029855 A KR20060029855 A KR 20060029855A KR 20070098335 A KR20070098335 A KR 20070098335A
Authority
KR
South Korea
Prior art keywords
hard mask
oxide film
semiconductor device
metal hard
metal
Prior art date
Application number
KR1020060029855A
Other languages
Korean (ko)
Inventor
조준희
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020060029855A priority Critical patent/KR20070098335A/en
Publication of KR20070098335A publication Critical patent/KR20070098335A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method for manufacturing a semiconductor device is provided to improve the operation reliability of the semiconductor device by reducing an amount of a noise which is generated between adjacent lines. A metal line(22) is formed on a semiconductor substrate. A multilayer interlayer dielectric(23), which includes a low-dielectric oxide film, is formed on the metal layer. A metal hard mask is formed on the interlayer dielectric. A photo-sensitive pattern is formed on the metal hard mask. The metal hard mask is etched by using the photo-sensitive pattern as an etching mask. The photo-sensitive pattern is removed from the semiconductor substrate. The interlayer dielectric is etched by using the metal hard mask as the etching mask and forms a contact hole formed by etching the interlayer dielectric.

Description

반도체 소자의 제조방법{METHOD FOR FABRICATING THE SAME OF SEMICONDUCTOR DEVICE}Manufacturing method of semiconductor device {METHOD FOR FABRICATING THE SAME OF SEMICONDUCTOR DEVICE}

도 1은 종래 기술에 따른 반도체 소자를 설명하기 위한 TEM사진,1 is a TEM photograph for explaining a semiconductor device according to the prior art,

도 2a 내지 도 2e는 본 발명의 바람직한 제1실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정 단면도,2A through 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention;

도 3a 내지 도 3e는 본 발명의 바람직한 제2실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정 단면도,3A to 3E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention;

도 4는 본 발명의 바람직한 실시예에 따른 반도체 소자를 설명하기 위한 TEM사진.4 is a TEM photograph for explaining a semiconductor device according to a preferred embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

21 : 반도체 기판 22 : 메탈배선21 semiconductor substrate 22 metal wiring

23 : 층간절연막 24 : 메탈하드마스크23: interlayer insulating film 24: metal hard mask

25 : 감광막패턴 26 : 콘택홀25 photosensitive film pattern 26 contact hole

27a : 메탈콘택플러그27a: Metal Contact Plug

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 반도체 소자의 메탈배선 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing metal wiring of a semiconductor device.

현재 반도체 소자의 메탈(Metal)배선간의 층간절연막물질(Inter Metal Dielectric;IMD Material)로 평탄화 특성이 우수하고 유전상수(K-VALUE)가 낮은 산화막을 사용하고 있다. 그러나, 반도체 소자가 고집적화 됨에 따라 소자의 기생캐패시터(Capacitor)저하 및 스피드(Speed)향상을 위하여 종래의 산화막보다 유전상수(K-value)가 더 낮은 저유전(low-K)물질이 제안되고 있다.Currently, an oxide film having excellent planarization characteristics and a low dielectric constant (K-VALUE) is used as an inter metal dielectric (IMD material) between metal interconnections of semiconductor devices. However, as semiconductor devices have been highly integrated, low-K materials having a lower dielectric constant (K-value) than conventional oxide films have been proposed to reduce parasitic capacitors and improve speed of devices. .

메탈배선을 형성하기 위해서는 메탈배선 상부에 라이너산화막, 저유전산화막과 캡핑산화막을 순차로 적층된 층간절연막을 형성하고 캡핑산화막 상에 감광막패턴을 형성한 후, 감광막패턴으로 층간절연막을 형성하여 콘택홀을 형성한 후, 콘택홀을 매립하는 메탈콘택플러그를 형성하여 상부와 하부 메탈배선을 연결하는 공정을 실시한다.In order to form a metal wiring, an interlayer insulating film in which a liner oxide film, a low dielectric oxide film, and a capping oxide film are sequentially stacked on the metal wiring is formed, a photosensitive film pattern is formed on the capping oxide film, and an interlayer insulating film is formed using the photosensitive film pattern to form a contact hole. After forming the metal contact plug to fill the contact hole is performed to connect the upper and lower metal wiring.

위와 같이, 층간절연막 형성시 스피드 및 기생캐패시터문제 해결을 위해 저유전산화막을 사용한다. 이때, 저유전산화막은 일반적인 산화막보다 카본(Carbon)이 더 많이 함유되어 있다.As described above, a low dielectric oxide film is used to solve the problem of speed and parasitic capacitor when forming an interlayer insulating film. At this time, the low dielectric oxide film contains more carbon than the general oxide film.

그러나, 콘택홀 형성 후 감광막패턴 제거를 위한 산소스트립공정에서 카본이 함유된 저유전산화막이 손실되어 박막이 어택받는 문제점이 있다.However, the low dielectric oxide film containing carbon is lost in the oxygen strip process for removing the photoresist pattern after forming the contact hole, thereby causing the thin film to be attacked.

도 1은 종래 기술에 따른 반도체 소자를 설명하기 위한 TEM사진이다.1 is a TEM photograph for explaining a semiconductor device according to the prior art.

도 1에 도시된 바와 같이, 메탈배선(11) 상부에 콘택홀(13)이 형성된 저유전산화막(12)이 어택(Attack)받아 보잉(Bowing)이 형성된 것을 알 수 있다.As shown in FIG. 1, it can be seen that the low dielectric oxide film 12 having the contact hole 13 formed on the metal wiring 11 is attacked to form a bowing.

본 발명은 상기한 종래 기술의 문제점을 해결하기 위해 제안된 것으로, 저유전산화막을 포함하는 층간절연막이 어택받아 보잉이 형성되는 것을 방지하기 위한 반도체 소자의 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a method of manufacturing a semiconductor device for preventing the formation of a bowing due to an interlayer insulating film including a low dielectric oxide film attacked.

본 발명은 반도체 기판 상부에 메탈배선을 형성하는 단계, 상기 메탈배선 상에 저유전산화막을 포함하는 다층의 층간절연막을 형성하는 단계, 상기 층간절연막 상에 메탈하드마스크를 사용하는 단계, 상기 메탈하드마스크 상에 감광막패턴을 형성하는 단계, 상기 감광막패턴을 식각마스크로 하여 상기 메탈하드마스크를 식각하는 단계, 상기 감광막패턴을 제거하는 단계, 상기 메탈하드마스크를 식각마스크로 상기 층간절연막을 식각하여 콘택홀을 형성하는 단계를 포함한다.The present invention includes forming a metal wiring on the semiconductor substrate, forming a multi-layered insulating film including a low dielectric oxide film on the metal wiring, using a metal hard mask on the interlayer insulating film, the metal hard Forming a photoresist pattern on a mask, etching the metal hard mask using the photoresist pattern as an etch mask, removing the photoresist pattern, and etching the interlayer insulating layer using the metal hard mask as an etch mask. Forming a hole.

이하, 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

실시예Example 1 One

도 2a 내지 도 2e는 본 발명의 바람직한 제1실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정 단면도이다.2A to 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

도 2a에 도시된 바와 같이, 반도체 기판(21) 상부에 메탈배선(22)을 형성한다. 여기서, 반도체 기판(21)은 소자분리막과 웰(Well)을 포함한다. 또한, 반도체 기판(21)과 메탈배선(22) 사이에는 게이트패턴, 비트라인패턴과 스토리지노드가 형성된다.As shown in FIG. 2A, the metal wiring 22 is formed on the semiconductor substrate 21. Here, the semiconductor substrate 21 includes an isolation layer and a well. In addition, a gate pattern, a bit line pattern, and a storage node are formed between the semiconductor substrate 21 and the metal wiring 22.

이어서, 메탈배선(22) 상에 라이너산화막(Liner Oxide, 23a), 저유전산화막(low-K Oxide, 23b)과 캡핑산화막(Capping Oxide, 23c)이 순차로 적층된 메탈배선간의 절연을 위한 층간절연막(Inter Metal Dielectirc;IMD, 23)을 형성한다.Subsequently, an interlayer for insulation between a metal line in which a liner oxide (23a), a low-K oxide (23b), and a capping oxide (23c) are sequentially stacked on the metal line 22 is formed. An insulating film Inter Metal Dielectirc (IMD) 23 is formed.

특히, 저유전산화막(23b)은 코팅타입(Coating Type) 또는 화학기상증착법(Chemical Vapor Deposition;CVD)으로 형성하되, Si-O-C-H의 화합물로 구성된 산화막으로 형성한다. 상기 저유전산화막(23b)은 기존 산화막에 비해 카본(Carbon)과 수분이 더 많이 포함되어 있으며, 반도체 소자의 스피드와 기생캐패시터 문제의 개선을 위한 충분한 두께 즉, 5000Å∼7000Å으로 형성한다. In particular, the low dielectric oxide film 23b is formed by a coating type or chemical vapor deposition (CVD), but is formed by an oxide film composed of a compound of Si-O-C-H. The low dielectric oxide film 23b contains more carbon and moisture than the conventional oxide film, and is formed to have a sufficient thickness, that is, 5000 Å to 7000 을 to improve the speed and parasitic capacitor problem of the semiconductor device.

그리고, 라이너산화막(23a)은 저유전산화막(23b)과 하부 메탈배선(22) 사이에 저유전산화막(23b)의 수분으로 인해 메탈배선(22)이 손상되는 것을 방지하기 위해 형성하되, 100Å∼1000Å의 두께로 형성한다. The liner oxide film 23a is formed between the low dielectric oxide film 23b and the lower metal wiring 22 to prevent damage to the metal wiring 22 due to moisture in the low dielectric oxide film 23b. It is formed to a thickness of 1000Å.

그리고, 캡핑산화막(23c)은 상부 하드마스크에 의해 저유전산화막(23b)이 손상되거나 물성이 변화되는 것을 방지하면서 상부 하드마스크와 저유전산화막(23b)이 반응하는 것을 방지하기 위해 형성하되, 3000Å∼5000Å의 두께로 형성한다.In addition, the capping oxide film 23c is formed to prevent the upper hard mask and the low dielectric oxide film 23b from reacting while preventing the low dielectric oxide film 23b from being damaged or changing physical properties by the upper hard mask. It is formed to a thickness of ˜5000 mm.

따라서, 층간절연막(23)의 총 두께는 8100Å∼13000Å으로 형성할 수 있다.Therefore, the total thickness of the interlayer insulating film 23 can be formed to be 8100 kPa to 13000 kPa.

이어서, 층간절연막(23) 상에 메탈하드마스크(24)를 형성한다. 여기서, 메탈하드마스크(24)는 텅스텐(Ｗ) 또는 알루미늄(Al)으로 형성한다. 바람직하게는 텅스텐으로 형성한다.Subsequently, a metal hard mask 24 is formed on the interlayer insulating film 23. Here, the metal hard mask 24 is made of tungsten or aluminum (Al). It is preferably formed of tungsten.

이어서, 메탈하드마스크(24) 상에 감광막을 형성하고, 노광 및 현상으로 콘택홀 예정지역을 오픈시키는 감광막패턴(25)을 형성한다.Subsequently, a photoresist film is formed on the metal hard mask 24, and a photoresist pattern 25 is formed to open a contact hole region by exposure and development.

도 2b에 도시된 바와 같이, 감광막패턴(25)을 식각마스크로 메탈하드마스크(24)를 식각한다. 여기서, 텅스텐으로 형성된 메탈하드마스크(24)는 SF5와 N2의 혼합가스를 이용하여 식각하되, SF6는 1sccm∼sccm, N2는 1sccm∼100sccm의 유량으로 플로우 하여 실시한다.As shown in FIG. 2B, the metal hard mask 24 is etched using the photoresist pattern 25 as an etch mask. Here, the metal hard mask 24 formed of tungsten is etched using a mixed gas of SF 5 and N 2 , but SF 6 flows at a flow rate of 1 sccm to sccm and N 2 to 1 sccm to 100 sccm.

이어서, 감광막패턴(25)을 산소스트립공정으로 제거한다. 이때, 층간절연막(23)은 식각되지 않고, 최상부층에 캡핑산화막(23c)이 형성되어 저유전산화막(23b)의 노출을 방지하고 있으므로 저유전산화막(23b)의 손상을 방지할 수 있다.Subsequently, the photosensitive film pattern 25 is removed by an oxygen strip process. At this time, since the interlayer insulating film 23 is not etched and the capping oxide film 23c is formed on the uppermost layer to prevent the low dielectric oxide film 23b from being exposed, damage to the low dielectric oxide film 23b can be prevented.

도 2c에 도시된 바와 같이, 메탈하드마스크(24)를 식각마스크로 층간절연막(23)을 식각하여 콘택홀(26)을 형성한다. 여기서, 층간절연막(23)은 1스텝으로 식각하고, 특히 저유전산화막(23b)의 식각시 N2와 O2의 혼합가스로 실시하되, N2를 1sccm∼1000sccm, O2를 1sccm∼1000sccm의 유량으로 플로우하여 실시한다.As illustrated in FIG. 2C, the interlayer insulating layer 23 is etched using the metal hard mask 24 as an etch mask to form the contact hole 26. Here, the interlayer insulating film 23 is etched in a first step and, in particular, synthesis was carried out with a mixed gas at the time of etching of low-k oxide layer (23b) N 2 and O 2, of the the N 2 1sccm~1000sccm, O 2 1sccm~1000sccm Flow by flow.

도 2d에 도시된 바와 같이, 콘택홀(26)을 채울때까지 메탈하드마스크(24) 상에 도전물질(27)을 형성한다. 여기서, 도전물질(27)은 메탈하드마스크(24)와 동일 한 물질로 형성하되, 바람직하게는 텅스텐(Ｗ)으로 형성한다.As shown in FIG. 2D, the conductive material 27 is formed on the metal hard mask 24 until the contact hole 26 is filled. Here, the conductive material 27 is formed of the same material as the metal hard mask 24, preferably formed of tungsten (Ｗ).

도 2e에 도시된 바와 같이, 층간절연막(23)의 표면이 드러날때까지 도전물질(27)을 전면식각하여 메탈콘택플러그(27a)를 형성한다.As shown in FIG. 2E, the conductive material 27 is etched entirely until the surface of the interlayer insulating layer 23 is exposed to form the metal contact plug 27a.

도전물질(27)을 전면식각하는 시점에서 도전물질(27)에 의해 층간절연막(23)의 측벽이 모두 채워져 있기 때문에 전면식각으로 인한 층간절연막(23)의 손실이 없다.Since the sidewalls of the interlayer insulating film 23 are completely filled by the conductive material 27 at the time of the entire surface etching of the conductive material 27, there is no loss of the interlayer insulating film 23 due to the entire surface etching.

상기 도 2d에서 도전물질(27)을 메탈하드마스크(24)와 동일한 물질로 형성함으로써 도전물질(27) 전면식각시 메탈하드마스크(24)를 같이 제거할 수 있다. 즉, 메탈하드마스크(24)의 제거공정을 따로 실시하지 않아서 저유전산화막(23b)의 손상 방지와 공정마진을 확보할 수 있다.In FIG. 2D, the conductive material 27 may be formed of the same material as the metal hard mask 24 so that the metal hard mask 24 may be removed together with the entire surface of the conductive material 27. That is, since the removal process of the metal hard mask 24 is not performed separately, it is possible to prevent damage to the low dielectric film 23b and to secure a process margin.

실시예Example 2 2

도 3a 내지 도 3e는 본 발명의 바람직한 제2실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정 단면도이다.3A to 3E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

도 3a에 도시된 바와 같이, 반도체 기판(31) 상부에 메탈배선(32)을 형성한다. 여기서, 반도체 기판(31)은 소자분리막과 웰(Well)을 포함한다. 또한, 반도체 기판(31)과 메탈배선(32) 사이에는 게이트패턴, 비트라인패턴과 스토리지노드가 형성된다.As shown in FIG. 3A, a metal wiring 32 is formed on the semiconductor substrate 31. Here, the semiconductor substrate 31 includes an isolation layer and a well. In addition, a gate pattern, a bit line pattern, and a storage node are formed between the semiconductor substrate 31 and the metal wiring 32.

이어서, 메탈배선(32) 상에 라이너산화막(Liner Oxide, 33a), 저유전산화막(low-K Oxide, 33b)과 캡핑산화막(Capping Oxide, 33c)가 순차로 적층된 메탈배선간의 절연을 위한 층간절연막(Inter Metal Dielectirc;IMD, 33)을 형성한다.Subsequently, an interlayer for insulation between a metal line in which a liner oxide layer 33a, a low-K oxide layer 33b, and a capping oxide layer 33c are sequentially stacked on the metal line 32 is formed. An insulating film Inter Metal Dielectirc (IMD) 33 is formed.

특히, 저유전산화막(33b)은 코팅타입(Coating Type) 또는 화학기상증착법(Chemical Vapor Deposition;CVD)으로 형성하되, Si-O-C-H의 화합물로 구성된 산화막으로 형성한다. 상기 저유전산화막(33b)은 기존 산화막에 비해 카본(Carbon)과 수분이 더 많이 포함되어 있으며, 반도체 소자의 스피드와 기생캐패시터 문제의 개선을 위한 충분한 두께 즉, 5000Å∼7000Å으로 형성한다. In particular, the low dielectric oxide film 33b is formed by a coating type or chemical vapor deposition (CVD), but is formed by an oxide film composed of a compound of Si-O-C-H. The low dielectric oxide film 33b contains more carbon and moisture than the conventional oxide film, and is formed to have a sufficient thickness, that is, 5000 Å to 7000 을 to improve the speed and parasitic capacitor problem of the semiconductor device.

그리고, 라이너산화막(33a)은 저유전산화막(33b)과 하부 메탈배선(32) 사이에 저유전산화막(33b)의 수분으로 인해 메탈배선(32)이 손상되는 것을 방지하기 위해 형성하되, 100Å∼1000Å의 두께로 형성한다. The liner oxide film 33a is formed between the low dielectric oxide film 33b and the lower metal wiring 32 to prevent damage to the metal wiring 32 due to moisture in the low dielectric oxide film 33b. It is formed to a thickness of 1000Å.

그리고, 캡핑산화막(33c)은 상부 하드마스크에 의해 저유전산화막(33b)이 손상되거나 물성이 변화되는 것을 방지하면서 상부 하드마스크와 저유전산화막(33b)이 반응하는 것을 방지하기 위해 형성하되, 3000Å∼5000Å의 두께로 형성한다.In addition, the capping oxide film 33c is formed to prevent the upper hard mask and the low dielectric oxide film 33b from reacting while preventing the low dielectric oxide film 33b from being damaged or changing physical properties by the upper hard mask. It is formed to a thickness of ˜5000 mm.

따라서, 층간절연막(33)의 총 두께는 8100Å∼13000Å으로 형성할 수 있다.Therefore, the total thickness of the interlayer insulating film 33 can be formed to be 8100 kPa to 13000 kPa.

이어서, 층간절연막(33) 상에 메탈하드마스크(34)를 형성한다. 여기서, 메탈하드마스크(34)는 텅스텐(Ｗ) 또는 알루미늄(Al)으로 형성한다. 바람직하게는 텅스텐으로 형성한다.Subsequently, a metal hard mask 34 is formed on the interlayer insulating film 33. Here, the metal hard mask 34 is formed of tungsten or aluminum (Al). It is preferably formed of tungsten.

이어서, 메탈하드마스크(34) 상에 감광막을 형성하고, 노광 및 현상으로 콘택홀 예정지역을 오픈시키는 감광막패턴(35)을 형성한다.Subsequently, a photoresist film is formed on the metal hard mask 34, and a photoresist pattern 35 is formed to open a contact hole region by exposure and development.

도 3b에 도시된 바와 같이, 감광막패턴(35)을 식각마스크로 메탈하드마스크(34)를 식각한다. 여기서, 텅스텐으로 형성된 메탈하드마스크(34)는 SF5와 N2의 혼합가스를 이용하여 식각하되, SF6는 1sccm∼sccm, N2는 1sccm∼100sccm의 유량으로 플로우 하여 실시한다.As shown in FIG. 3B, the metal hard mask 34 is etched using the photoresist pattern 35 as an etch mask. Here, the metal hard mask 34 formed of tungsten is etched using a mixed gas of SF 5 and N 2 , but SF 6 flows at a flow rate of 1 sccm to sccm and N 2 to 1 sccm to 100 sccm.

이어서, 감광막패턴(35)을 산소스트립공정으로 제거한다. 이때, 층간절연막(33)은 식각되지 않고, 최상부층에 캡핑산화막(33c)이 형성되어 저유전산화막(33b)의 노출을 방지함으로써 저유전산화막(33b)의 손상을 방지할 수 있다.Next, the photosensitive film pattern 35 is removed by an oxygen strip process. At this time, the interlayer insulating film 33 is not etched, and the capping oxide film 33c is formed on the uppermost layer to prevent the low dielectric oxide film 33b from being exposed, thereby preventing damage to the low dielectric film 33b.

도 3c에 도시된 바와 같이, 메탈하드마스크(34)를 식각마스크로 층간절연막(33)을 식각하여 콘택홀(36)을 형성한다. 여기서, 층간절연막(33)은 1스텝으로 식각하고, 특히 저유전산화막(33b)의 식각시 N2와 O2의 혼합가스로 실시하되, N2를 1sccm∼1000sccm, O2를 1sccm∼1000sccm의 유량으로 플로우하여 실시한다.As shown in FIG. 3C, the interlayer insulating layer 33 is etched using the metal hard mask 34 as an etch mask to form the contact hole 36. Here, the interlayer insulating film 33 is etched in a first step, and in particular synthesis was carried out with a mixed gas of the low during the etching of the dielectric oxide film (33b) N 2 and O 2, of the the N 2 1sccm~1000sccm, O 2 1sccm~1000sccm Flow by flow.

이어서, 메탈하드마스크(34)를 SF5와 N2의 혼합가스를 이용한 스트립공정으로 제거하되, SF6는 1sccm∼sccm, N2는 1sccm∼100sccm의 유량으로 플로우 하여 실시한다. Subsequently, the metal hard mask 34 is removed by a strip process using a mixed gas of SF 5 and N 2 , but SF 6 is flowed at a flow rate of 1 sccm to sccm, and N 2 is 1 sccm to 100 sccm.

메탈하드마스크(34)의 제거공정은 산소가스를 포함하지 않는 혼합가스로 식각을 실시한다. 즉, 카본(Carbon)이 종래의 산화막보다 더 많이 함유된 저유전산화막(33b)이 산소가스로 인해 손상받는 것을 방지함으로써, 저유전산화막(33b)의 손실없이 메탈하드마스크(34)만 제거가 가능하다.The metal hard mask 34 is removed by etching with a mixed gas containing no oxygen gas. That is, the low dielectric oxide film 33b containing more carbon than the conventional oxide film is prevented from being damaged by oxygen gas, thereby removing only the metal hard mask 34 without losing the low dielectric oxide film 33b. It is possible.

도 3d에 도시된 바와 같이, 콘택홀(36)을 채울때까지 층간절연막(33) 상에 도전물질(37)을 형성한다.As shown in FIG. 3D, the conductive material 37 is formed on the interlayer insulating layer 33 until the contact hole 36 is filled.

도 3e에 도시된 바와 같이, 층간절연막(33)의 표면이 드러날때까지 도전물질(37)을 전면식각하여 메탈콘택플러그(37a)를 형성한다.As shown in FIG. 3E, the conductive material 37 is etched entirely until the surface of the interlayer insulating layer 33 is exposed to form a metal contact plug 37a.

도전물질(37)을 전면식각하는 시점에서 도전물질(37)에 의해 층간절연막(33)의 측벽이 모두 채워져 있기 때문에 전면식각으로 인한 층간절연막(33)의 손실이 없다.Since the sidewalls of the interlayer insulating film 33 are filled by the conductive material 37 at the time of the entire etching of the conductive material 37, there is no loss of the interlayer insulating film 33 due to the entire surface etching.

도 4는 본 발명의 바람직한 실시예에 따른 반도체 소자를 설명하기 위한 TEM사진이다. 이해를 돕기 위해 도면부호는 도 2a 내지 도 2e와 동일한 부호를 사용하였다.4 is a TEM photograph for explaining a semiconductor device according to a preferred embodiment of the present invention. For the sake of clarity, the same reference numerals are used to refer to FIGS. 2A to 2E.

도 4에 도시된 바와 같이, 메탈배선(22) 상에 형성된 콘택홀(26)을 제공하는 층간절연막(23)에 손상으로 인한 보잉(Bowing)이 존재하지 않는다.As shown in FIG. 4, no bowing due to damage is present in the interlayer insulating layer 23 that provides the contact hole 26 formed on the metal line 22.

상술한 본 발명은, 라이너산화막, 저유전산화막과 캡핑산화막이 순차로 적층된 층간절연막을 식각하기 위한 메탈하드마스크를 형성하고 감광막패턴으로 메탈하드마스크를 식각한 후 감광막패턴을 스트립함으로써 감광막패턴의 스트립시 산소가스로 인한 저유전산화막의 손상을 방지할 수 있는 장점이 있다.According to the present invention, a metal hard mask for etching an interlayer insulating film in which a liner oxide film, a low dielectric oxide film, and a capping oxide film are sequentially stacked is formed, the metal hard mask is etched with the photosensitive film pattern, and then the photosensitive film pattern is stripped to form a metal hard mask. When stripping, there is an advantage of preventing damage to the low-k dielectric layer due to oxygen gas.

또한, 메탈하드마스크 제거시 산소가스를 포함하지 않는 혼합가스를 사용함으로써 산소가스로 인한 저유전산화막의 손상을 방지할 수 있는 장점이 있다. 또한, 메탈하드마스크는 메탈콘택플러그형성을 위한 도전물질의 전면식각시 동시에 제거가 가능하므로 공정 마진 확보와 저유전산화막의 손상을 방지할 수 있는 장점이 있다.In addition, by using a mixed gas containing no oxygen gas when removing the metal hard mask, there is an advantage that can prevent damage to the low-k dielectric layer due to oxygen gas. In addition, since the metal hard mask can be removed at the same time during the entire surface etching of the conductive material for forming the metal contact plug, there is an advantage of securing a process margin and preventing damage to the low dielectric layer.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으 나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 본 발명에 의한 반도체 소자의 제조방법은 층간절연막의 보잉을 방지하여 콘택저항, 플러그간 펀치특성열화 및 배선간 노이즈증가 문제를 개선함으로써 소자특성 개선 및 소자의 신뢰성을 확보할 수 있는 효과가 있다.The manufacturing method of the semiconductor device according to the present invention described above has the effect of preventing the bowing of the interlayer insulating film, thereby improving the contact resistance, the deterioration of the punch characteristics between the plugs, and the noise increase between the wires, thereby improving device characteristics and securing device reliability. have.

Claims (11)

반도체 기판 상부에 메탈배선을 형성하는 단계;Forming a metal wiring on the semiconductor substrate; 상기 메탈배선 상에 저유전산화막을 포함하는 다층의 층간절연막을 형성하는 단계;Forming a multilayer interlayer insulating film including a low dielectric oxide film on the metal wiring; 상기 층간절연막 상에 메탈하드마스크를 사용하는 단계;Using a metal hard mask on the interlayer insulating film; 상기 메탈하드마스크 상에 감광막패턴을 형성하는 단계;Forming a photoresist pattern on the metal hard mask; 상기 감광막패턴을 식각마스크로 하여 상기 메탈하드마스크를 식각하는 단계;Etching the metal hard mask by using the photoresist pattern as an etching mask; 상기 감광막패턴을 제거하는 단계; 및Removing the photoresist pattern; And 상기 메탈하드마스크를 식각마스크로 상기 층간절연막을 식각하여 콘택홀을 형성하는 단계Forming a contact hole by etching the interlayer insulating layer using the metal hard mask as an etch mask 를 포함하는 반도체 소자의 제조방법.Method of manufacturing a semiconductor device comprising a. 제1항에 있어서,The method of claim 1, 상기 콘택홀을 형성한 후,After forming the contact hole, 상기 콘택홀을 채울때까지 도전물질을 형성하는 단계; 및Forming a conductive material until the contact hole is filled; And 상기 층간절연막 상부가 드러날때까지 상기 도전물질 및 메탈하드마스크를 전면식각하여 메탈콘택플러그를 형성하는 단계Forming a metal contact plug by completely etching the conductive material and the metal hard mask until the upper portion of the interlayer insulating layer is exposed. 를 더 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.Method of manufacturing a semiconductor device further comprising. 제1항에 있어서,The method of claim 1, 상기 콘택홀을 형성한 후,After forming the contact hole, 상기 메탈하드마스크를 제거하는 단계;Removing the metal hard mask; 상기 콘택홀을 채울때까지 도전물질을 형성하는 단계; 및Forming a conductive material until the contact hole is filled; And 상기 층간절연막 상부가 드러날때까지 상기 도전물질을 전면식각하여 메탈콘택플러그를 형성하는 단계Forming a metal contact plug by etching the entire conductive material until the upper portion of the interlayer insulating layer is exposed; 를 더 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.Method of manufacturing a semiconductor device further comprising. 제1항 내지 제3항 중 어느 한 항에 있어서,The method according to any one of claims 1 to 3, 상기 메탈하드마스크와 도전물질은 동일한 물질로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.The metal hard mask and the conductive material are formed of the same material. 제4항에 있어서,The method of claim 4, wherein 상기 메탈하드마스크는 텅스텐(Ｗ) 또는 알루미늄(Al)으로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.The metal hard mask is a method of manufacturing a semiconductor device, characterized in that formed by tungsten (Ｗ) or aluminum (Al). 제3항에 있어서,The method of claim 3, 상기 메탈하드마스크를 식각하는 단계는,Etching the metal hard mask, SF5와 N2의 혼합가스를 이용하여 식각하되, SF6는 1sccm∼sccm, N2는 1sccm∼100sccm의 유량으로 플로우 하여 실시하는 것을 특징으로 하는 반도체 소자의 제조방법.Etching using a mixed gas of SF 5 and N 2 , SF 6 is carried out by flowing at a flow rate of 1sccm ~ sccm, N 2 1sccm ~ 100sccm. 제3항에 있어서,The method of claim 3, 상기 메탈하드마스크를 제거하는 단계는,Removing the metal hard mask, SF5와 N2의 혼합가스를 이용한 스트립공정을 실시하되, SF6는 1sccm∼sccm, N2는 1sccm∼100sccm의 유량으로 플로우 하여 실시하는 것을 특징으로 하는 반도체 소자의 제조방법.A strip process using a mixed gas of SF 5 and N 2 , wherein SF 6 flows at a flow rate of 1 sccm to sccm, and N 2 flows at a flow rate of 1 sccm to 100 sccm. 제1항에 있어서,The method of claim 1, 상기 저유전산화막은 코팅타입(Coating Type) 또는 화학기상증착법(Chemical Vapor Deposition;CVD)으로 형성하되, Si-O-C-H의 화합물로 구성된 산화막으로 형 성하는 것을 특징으로 하는 반도체 소자의 제조방법.The low dielectric oxide film is formed by a coating type (Coating Type) or Chemical Vapor Deposition (CVD), the method of manufacturing a semiconductor device, characterized in that formed as an oxide film composed of a compound of Si-O-C-H. 제8항에 있어서,The method of claim 8, 상기 저유전산화막은 5000Å∼7000Å의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.The low dielectric oxide film is a semiconductor device manufacturing method, characterized in that formed in a thickness of 5000 ~ 7000Å. 제1항 또는 제8항에 있어서,The method according to claim 1 or 8, 상기 저유전산화막을 식각하는 단계는,Etching the low dielectric oxide film, N2와 O2의 혼합가스로 실시하되, N2를 1sccm∼1000sccm, O2를 1sccm∼1000sccm의 유량으로 플로우하여 실시하는 것을 특징으로 하는 반도체 소자의 제조방법.The synthesis was carried out with a mixed gas of N 2 and O 2, The method of producing a semiconductor device characterized in that the N 2 conduct 1sccm~1000sccm, O 2 to flow at a flow rate of 1sccm~1000sccm. 제1항에 있어서,The method of claim 1, 상기 다층의 층간절연막은,The multilayer interlayer insulating film, 라이너산화막, 저유전산화막과 캡핑산화막이 순차로 적층된 구조로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.A liner oxide film, a low dielectric oxide film and a capping oxide film are formed in a stacked structure of a semiconductor device manufacturing method characterized in that.
KR1020060029855A 2006-03-31 2006-03-31 Method for fabricating the same of semiconductor device KR20070098335A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020060029855A KR20070098335A (en) 2006-03-31 2006-03-31 Method for fabricating the same of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020060029855A KR20070098335A (en) 2006-03-31 2006-03-31 Method for fabricating the same of semiconductor device

Publications (1)

Publication Number Publication Date
KR20070098335A true KR20070098335A (en) 2007-10-05

Family

ID=38804412

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020060029855A KR20070098335A (en) 2006-03-31 2006-03-31 Method for fabricating the same of semiconductor device

Country Status (1)

Country Link
KR (1) KR20070098335A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10074707B2 (en) 2015-11-03 2018-09-11 Samsung Display Co. Ltd. Thin film transistor array for organic light-emitting display

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10074707B2 (en) 2015-11-03 2018-09-11 Samsung Display Co. Ltd. Thin film transistor array for organic light-emitting display

Similar Documents

Publication Publication Date Title
KR100568425B1 (en) Method of manufacturing bit line in a flash device
US6879042B2 (en) Semiconductor device and method and apparatus for manufacturing the same
US7772112B2 (en) Method of manufacturing a semiconductor device
KR100772681B1 (en) Method for manufacturing storage node contact hole in semiconductor device
KR20080030292A (en) Method of forming metal line of semiconductor devices
KR100831981B1 (en) Method for forming contact plug in semiconductor device
JP5178025B2 (en) Manufacturing method of semiconductor memory device
KR20070098335A (en) Method for fabricating the same of semiconductor device
KR100778869B1 (en) Method for forming contact of semiconductor device
JP2003197775A (en) Method for manufacturing semiconductor element
KR100591179B1 (en) Metal line formation method of semiconductor device
TWI512894B (en) Metal interconnect structure and process thereof
US20230154853A1 (en) Semiconductor structure and semiconductor device
KR100784074B1 (en) Method of manufacturing bit line in a semiconductor device
US8053369B2 (en) Process for forming opening portion in interlayer insulation film on metallic layer of semiconductor device
KR100832018B1 (en) Semiconductor device and method for manufacturing the same
KR100780614B1 (en) Method for fabricating semiconductor device
KR20070066460A (en) Method for forming storage node hole in semiconductor device
KR100643567B1 (en) Method for fabricating of Landing Plug Contact
US20070210406A1 (en) Semiconductor device and method of manufacturing the same
KR100792372B1 (en) Method for fabricating semiconductor device
KR100762877B1 (en) Method for forming contact plug of semiconductor device
KR20080060310A (en) Method for forming plug in semiconductor device
KR20070002839A (en) Method for manufacturing semiconductor device
KR20050023982A (en) Method of forming metal contact

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination