KR20070089544A - Non planar anti fuse - Google Patents

Abstract

A non-planar anti-fuse is provided to prevent the degradation of a peripheral circuit by making a gate insulating layer easily broken in a low level voltage using a recess of a three-dimensional structure under a gate electrode. A non-planar anti-fuse includes a silicon substrate(21), a recess, a gate insulating layer, and a gate electrode. The recess(100) is formed on the substrate. The recess has a depth. The gate insulating layer(23) is formed on the substrate including the recess. The gate electrode(24) is formed on the gate insulating layer. The recess is formed like an etch bar type structure. The recess and the gate electrodes are arranged across each other. The recess is capable of being formed like a plurality of etch bar type structures.

Description

NON PLANAR ANTI FUSE}

1A is a plan view showing an antifuse of a MOS structure according to the prior art;

1B is a cross-sectional view taken along line AA ′ of FIG. 1A;

1C is a cross-sectional view taken along the line BB ′ of FIG. 1A;

2A is a plan view of an antifuse according to a first embodiment of the present invention;

FIG. 2B is a cross sectional view of the antifuse taken along line CC ′ in FIG. 2A;

FIG. 2C is a cross-sectional view of the antifuse taken along the line D-D 'of FIG. 2A;

3A is a plan view of an antifuse according to a second embodiment of the present invention;

3B is a cross-sectional view of the anti-fuse along the line E-E 'of FIG. 3A,

3C is a cross-sectional view taken along the line FF 'of FIG. 3A.

* Explanation of symbols for the main parts of the drawings

21, 31: silicon substrate 22, 32: P-type well

23, 33: gate insulating film 24, 34: gate electrode

25, 35: N-type source / drain junction 25a, 35a: junction contact

26, 36: device isolation layer 27, 37: P-type pickup layer

27a, 37a: P type pickup layer contact

100, 200: recess

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to non-planar anti-fuse.

In general, an anti-fuse structure applies a voltage to upper and lower electrodes of a Miller capacitor (ie, a MOS structure), and carriers formed in the active region cause injection into the gate oxide layer. Insulation breakdown is obtained.

The presence of the junction is to reduce the conduction conditions of the antifuse by concentrating the electric field on the gate oxide film near the junction.

1A is a plan view illustrating an antifuse of a MOS structure according to the prior art, FIG. 1B is a cross-sectional view taken along the line AA ′ of FIG. 1A, and FIG. 1C is a cross-sectional view taken along the line B-B ′ of FIG. 1A.

The P type well 12 is formed in the silicon substrate 11, the gate insulating film 13 is formed on the P type well 12, and the gate electrode is formed on the gate insulating film 13 by a conductive layer such as polysilicon. (14) is formed.

An N-type source / drain junction 15 is formed in the P-type well 12 between the gate electrodes 14, and is formed by the device isolation film 16 in the silicon substrate 11 except for the P-type well 12. A separate P-type pickup layer 17 is formed. Then, a junction contact 15a is formed on the N-type source / drain junction 15, and a pickup layer contact 17a is formed on the P-type pickup layer 17.

The antifuse structure of FIGS. 1A to 1C destroys the gate insulating film to increase the leakage current between the gate electrode and the channel and the gate electrode and the source / drain junction, thereby recording data.

However, prior art antifuse structures require very high levels of electric field concentration ('E') for fuse conduction (i.e. to destroy the gate insulating film), which is connected to the antifuse drive. There is a problem that deteriorates the characteristics of the product by causing degradation and destruction of the circuit. In particular, since the active region under the gate insulating layer has a planar structure, a higher electric field is required, and a relatively large voltage must be applied for fuse conduction.

The present invention has been proposed to solve the above problems of the prior art, and an object of the present invention is to provide an antifuse of a semiconductor device capable of preventing a deterioration and destruction of a peripheral circuit by allowing a fuse to be conducted even at a low voltage.

Antifuse of the semiconductor device of the present invention for achieving the above object is a silicon substrate; A recess of a predetermined depth formed in the silicon substrate; A gate insulating film formed on the silicon substrate including the recess; And a gate electrode on the gate insulating layer, wherein the recess is in the form of a transverse etch bar that intersects the gate electrode, and the recess is a quadrangle having a size that does not deviate from the gate electrode. Characterized in that the etching wedge form.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

Embodiments of the present invention described below form a non-planar anti fuse structure by modifying the structure of the active region under the gate electrode so that an electric field is artificially concentrated in the structure itself so that the gate insulating film is formed even at a low voltage. Break to achieve fuse conduction.

FIG. 2A is a plan view of the antifuse according to the first embodiment of the present invention, FIG. 2B is a cross-sectional view of the antifuse taken along line C-C 'of FIG. 2A, and FIG. 2C is taken along the line D-D' of FIG. 2A. A cross section of the antifuse.

2A to 2C, a P type well 22 is formed in the silicon substrate 21, a gate insulating film 23 is formed on the P type well 22, and a poly is formed on the gate insulating film 23. The gate electrode 24 is formed of a conductive layer such as silicon.

An N-type source / drain junction 25 is formed in the P-type well 22 between the gate electrodes 24, and is formed by the device isolation layer 26 in the silicon substrate 21 except for the P-type well 22. A separate P-type pick-up layer 27 is formed. A junction contact 25a is formed on the N-type source / drain junction 25, and a pickup layer contact 27a is formed on the P-type pickup layer 27.

In the first embodiment, the recess 100 is formed by etching the silicon substrate 21 having the P-type well 22 formed under the portion through which the gate electrode 24 passes to a predetermined depth. At this time, a plurality of recesses 100 are formed to cross the gate electrode 24 (three in FIG. 2A), and the three recesses 100 are spaced apart from each other at predetermined intervals.

The shape of the recess 100 as described above is called a transversely etched bar type. That is, since the silicon substrate 21 is etched in the transversely direction to form a bar shape, the silicon substrate 21 is referred to as a cross etch bar shape. As shown in FIG. 2A, the recess 100 is a gate electrode. It is formed in the direction which intersects with (24). In addition, both ends of the recess 100 have a size outside the gate electrode 24, whereby a self-aligning method may be applied when the gate electrode 24 is formed.

Referring to the method of forming the recess 100, assuming that the device isolation layer 22 is formed by a shallow trench isolation (STI) process, the pad layer used during the trench etching for forming the device isolation layer 22 ( In general, the recess 100 is formed at the same time as the trench etching using the stacked structure in the order of the pad oxide film and the pad nitride film. That is, the recess 100 is formed by trench etching to form a three-dimensional structure.

As described above, the first embodiment forms a plurality of recesses 100 having a predetermined depth in a direction crossing the gate electrode 24, so that the gate insulating film 23 is formed at the corner of the recess 100. It is thinly formed. That is, the thickness of the gate insulating film formed at the edge of the recess 100 may be defined by the protruding portion (substantially the surface of the silicon substrate) between the recess 100, the sidewalls and the bottom of the recess 100. It is formed thinner than thickness. As such, the thickness of the gate insulating film becomes non-uniform because, for example, when the gate insulating film is formed through dry oxidation, the oxidation proceeds more rapidly at the angled portions such as the protruding edges than the flat surface.

As such, when the gate insulating layer 23 is thinly formed at the edge of the recess 100, the electric field is more concentrated than the other portions at the edge of the recess 100 by the thin gate insulating layer 23. In addition, as the etched surface is increased by the sidewall of the recess 100, an inversion layer increases, thereby increasing the amount of carriers to be injected into the gate insulating layer 23.

As a result, the electric field is concentrated on the thinner gate insulating layer 23 and the amount of carrier increases as the etching surface increases, so that the first embodiment can easily conduct the fuse even at a lower voltage than the planar structure. have.

As in the first embodiment, when the recess 100 is formed as a cross etch bar, a self-aligning method may be applied when forming the gate electrode.

3A is a plan view of an antifuse according to a second embodiment of the present invention, FIG. 3B is a cross-sectional view of the antifuse taken along line E-E 'of FIG. 3A, and FIG. 3C is taken along the line F-F' of FIG. 3A. It is a cross section. 3A shows only the gate electrode 34 and the recess 200.

3A to 3C, a P-type well 32 is formed in the silicon substrate 31, a gate insulating film 33 is formed on the P-type well 32, and a poly is formed on the gate insulating film 33. The gate electrode 34 is formed of a conductive layer such as silicon.

An N-type source / drain junction 35 is formed in the P-type well 32 between the gate electrodes 34, and is formed by the device isolation film 36 in the silicon substrate 31 except for the P-type well 32. A P-type pickup layer 37 is formed to be separated. The junction contact 35a is formed on the N-type source / drain junction 35, and the pickup layer contact 37a is formed on the P-type pickup layer 37.

In the second embodiment, the recess 200 is formed by etching the silicon substrate 31 having the P-type well 32 formed under the portion through which the gate electrode 34 passes to a predetermined depth. In this case, a plurality of recesses 200 are formed under the gate electrode 24 (three in FIG. 3A), and the three recesses 200 are recessed structures having a rectangular wedge shape spaced apart from each other at predetermined intervals. to be. Thus, the recess 200 of the second embodiment also has a three-dimensional structure.

The shape of the recess 200 as described above is called a rectangular etched wedge type. That is, since the silicon substrate 31 is etched to form a wedge shape, the silicon substrate 31 is formed as a wedge shape, and the recess 200 is formed under the gate electrode 34, as shown in FIG. 3A. The gate electrode 34 is formed to have a size that does not deviate from the shortening of the gate electrode 34. That is, the recess 200 having a rectangular shape is formed to have a size not to deviate from the width of the gate electrode 34 at a predetermined interval below the long axis direction of the gate electrode 34. Therefore, the recesses 200 do not contact each other between the adjacent gate electrodes 34, and thus have a structure different from that of the first embodiment.

Referring to the method of forming the recess 200, assuming that the device isolation layer 32 is formed by a shallow trench isolation (STI) process, the pad layer used during the trench etching for forming the device isolation layer 32 ( In general, the recess 200 is formed in a rectangular shape at the same time as the trench barrier using an etching barrier.

As described above, the second embodiment forms a plurality of recesses 200 having a predetermined depth in the shape of a rectangle under the gate electrode 34, so that the gate insulating layer 33 is formed at the corner of the recess 200. It is thinly formed. That is, the thickness of the gate insulating film formed at the edge of the recess 200 may be defined by the protruding portion (substantially the surface of the silicon substrate) between the recess 200, the sidewall and the bottom of the recess 200. It is formed thinner than thickness. As such, the thickness of the gate insulating film becomes non-uniform because, for example, when the gate insulating film is formed through dry oxidation, the oxidation proceeds more rapidly at the angled portions such as the protruding edges than the flat surface.

As such, when the gate insulating layer 33 is thinly formed at the edge of the recess 200, the electric field is more concentrated by the thin gate insulating layer 33 than at other corners of the recess 200. In addition, as the etched surface is increased by the sidewall of the recess 200, an inversion layer increases, thereby increasing the amount of carrier to be injected into the gate insulating layer 33.

As a result, the electric field is concentrated on the thinner gate insulating film 33 and the amount of carrier increases as the etching surface increases, so that the second embodiment can easily conduct the fuse even at a lower voltage than the planar structure. have.

Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention, a recess having a three-dimensional structure is formed under the gate electrode so that the gate insulating film is easily broken even at a low voltage, thereby weakening the conduction condition of the antifuse, thereby preventing degradation of the peripheral circuit. .

In addition, even when applied to a non-planar type DRAM that requires the deformation of the device isolation layer there is an effect that can be manufactured without additional layers and costs.

Claims (7)

Silicon substrate; A recess of a predetermined depth formed in the silicon substrate; A gate insulating film formed on the silicon substrate including the recess; A gate electrode on the gate insulating layer Anti-fuse of the semiconductor device comprising a. The method of claim 1, The recess is The anti-fuse of the semiconductor device, characterized in that the cross-shaped etching bar intersecting the gate electrode. The method of claim 2, The recess is An anti-fuse of a semiconductor device, characterized in that in the form of a plurality of cross-etched bar arranged at a predetermined interval. The method of claim 3, Both ends of the recess have a size outside the gate electrode. The method of claim 1, The recess is The anti-fuse of the semiconductor device, characterized in that the rectangular etching wedge shape having a size that does not deviate from the gate electrode. The method of claim 5, The recess is An anti-fuse of a semiconductor device characterized in that the form of a plurality of rectangular etching wedges arranged at a predetermined interval. The method according to any one of claims 1 to 6, The gate insulating film, The thickness of the recess formed in the corner portion of the anti-fuse of the semiconductor device, characterized in that thinner than the thickness formed in the portion except the recess.

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