KR20070088054A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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KR20070088054A
KR20070088054A KR1020060018187A KR20060018187A KR20070088054A KR 20070088054 A KR20070088054 A KR 20070088054A KR 1020060018187 A KR1020060018187 A KR 1020060018187A KR 20060018187 A KR20060018187 A KR 20060018187A KR 20070088054 A KR20070088054 A KR 20070088054A
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South Korea
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gate insulating
active region
sides
pmos transistor
region
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KR1020060018187A
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Korean (ko)
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신민정
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주식회사 하이닉스반도체
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Priority to KR1020060018187A priority Critical patent/KR20070088054A/en
Publication of KR20070088054A publication Critical patent/KR20070088054A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

Abstract

A method for manufacturing a semiconductor device is provided to prevent concentration of electric field by rounding both sides of an active region of a vertical structure. A semiconductor substrate including a PMOS transistor region, an NMOS transistor region, and an isolation layer(24) for defining an active region(21) is provided. A first gate insulating layer(25) is formed on the semiconductor substrate including the isolation layer. A mask pattern is formed on the first gate insulating layer to expose an isolation layer part and both side parts of the active region along to a width direction in the PMOS transistor region on the first gate insulating layer. The exposed part of the first gate insulating layer is removed. Both sides of the active region of the exposed PMOS transistor region are rounded. A second gate insulating layer(27) is formed selectively on the rounded both sides of the active region and the isolation layer part contacting the rounded both sides of the active region. The mask pattern is removed. A gate conductive layer(28) is formed on the first and the second gate insulating layers. The gate conductive layer and the gate insulating layer are etched.

Description

반도체 소자의 제조방법{METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE}Manufacturing method of semiconductor device {METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE}

도 1은 종래기술의 문제점을 설명하기 위한 반도체 소자의 단면도.1 is a cross-sectional view of a semiconductor device for explaining the problems of the prior art.

도 2a 내지 도 2d는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정별 단면도.2A to 2D are cross-sectional views illustrating processes for manufacturing a semiconductor device in accordance with an embodiment of the present invention.

도 3a 내지 도 3c는 본 발명의 효과를 설명하기 위한 도면. 3A to 3C are views for explaining the effects of the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

21 : 액티브영역 22 : 측벽산화막21 active region 22 sidewall oxide film

23 : 라이너질화막 24 : 소자분리막23: liner nitride film 24: device isolation film

25 : 제1게이트절연막 26 : 마스크패턴25: first gate insulating film 26: mask pattern

27 : 제2게이트절연막 28 : 게이트도전막27: second gate insulating film 28: gate conductive film

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히, 엔모스(NMOS) 트랜지스터의 특성을 유지하면서 피모스(PMOS) 트랜지스터의 HEIP(Hot Electron Induced Punchthrough) 현상을 개선할 수 있는 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device capable of improving the Hot Electron Induced Punchthrough (PHI) phenomenon of a PMOS transistor while maintaining the characteristics of an NMOS transistor. It is about.

최근 반도체 소자의 고집적화 추세에 따라 우수한 소자 특성을 얻기 위한 다양한 공정 기술들이 적용 및 개발되고 있으며, 그 한 예로서, 소자분리막의 측면을 수직으로 형성하는 방법이 제안되었다.Recently, various process technologies for obtaining excellent device characteristics have been applied and developed according to the trend of high integration of semiconductor devices. As an example, a method of vertically forming side surfaces of a device isolation layer has been proposed.

그러나, 도 1에 도시된 바와 같이, 수직으로 형성된 소자분리막(14)으로 인해 그와 접한 액티브영역(11)의 양끝단 모서리부분(A)이 뾰족하게 형성되고, 이 모서리 부분에 트랜지스터의 동작시 발생하는 전기장이 집중되어 HEIP 현상이 심화된다는 문제점이 발생된다.However, as shown in FIG. 1, the edges A of both ends of the active region 11 which are in contact with each other are sharply formed due to the vertically formed device isolation layer 14. The problem occurs that the generated electric field is concentrated and the HEIP phenomenon is intensified.

상기 HEIP 현상은 피모스 트랜지스터에서의 원치 않는 채널 인버전(inversion) 현상에 기인한 것으로, 문턱전압(Threshold Voltage : Vt)을 국부적으로 감소시키고, 턴-오프(turn-off) 시의 누설전류를 증가시켜 전력 소모를 증가시킬 뿐만 아니라, 동작 속도를 저하시키며, 항복 전압을 감소시키는 등의 문제를 일으킨다. 이러한 HEIP 현상이 심한 경우, 트랜지스터의 원치 않는 턴-온(turn-on) 현상이 유발될 수도 있다.The HEIP phenomenon is due to an unwanted channel inversion phenomenon in the PMOS transistor, which locally reduces a threshold voltage (Vt) and reduces leakage current at turn-off. Not only does this increase power consumption, but it also causes problems such as slowing down operation and reducing breakdown voltage. If this HEIP phenomenon is severe, unwanted turn-on of the transistor may occur.

미설명된 도면부호 12는 측벽산화막을, 13은 라이너질화막을, 15는 게이트절연막을, 그리고, 16은 게이트도전막을 각각 나타낸다.Unexplained reference numeral 12 denotes a sidewall oxide film, 13 a liner nitride film, 15 a gate insulating film, and 16 a gate conductive film.

한편, 이러한 HEIP 현상은 소자분리막과 접한 액티브영역 부분 전체를 라운딩함으로써 개선시킬 수 있다. 그러나, 이 경우에는 액티브영역의 면적이 손실되어 소자의 리플레쉬 특성을 저하시키며, 트랜지스터의 열화현상을 야기하게 된다. 그러므로, 소자분리막과 접한 액티브영역 부분 전체를 라운딩시키는 방법을 적용하기에는 해결해야 할 과제가 많이 있으므로 실용성에 문제가 있다.On the other hand, such a HEIP phenomenon can be improved by rounding the entire active region in contact with the device isolation layer. In this case, however, the area of the active region is lost, which degrades the refresh characteristics of the device and causes the transistor to deteriorate. Therefore, there are many problems to be solved in order to apply the method of rounding the entire portion of the active region in contact with the device isolation film.

따라서, 본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출된 것으로서, 엔모스 트랜지스터의 특성을 유지하면서 소자분리막의 측면각도가 수직에 가까워짐에 따라 유발되는 피모스 트랜지스터에서의 HEIP 현상을 효과적으로 개선할 수 있는 반도체 소자의 제조방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and effectively improves the HEIP phenomenon in the PMOS transistor caused by the side angle of the device isolation layer becoming vertical while maintaining the characteristics of the NMOS transistor. It is an object of the present invention to provide a method for manufacturing a semiconductor device.

상기의 목적을 달성하기 위하여, 본 발명은, 피모스 트랜지스터 형성지역 및 엔모스 트랜지스터 형성지역을 가지며 액티브영역을 한정하는 소자분리막이 구비된 반도체 기판을 제공하는 단계; 소자분리막을 포함한 반도체 기판 상에 제1게이트절연막을 형성하는 단계; 제1게이트절연막 상에 피모스 트랜지스터 형성지역에서의 폭 방향에 따른 소자분리막 부분과 그에 접한 액티브영역 양측부를 노출시키는 마스크패턴을 형성하는 단계; 노출된 제1게이트절연막 부분을 제거하는 단계; 제1게이트절연막이 제거되어 노출된 피모스 트랜지스터 형성지역의 액티브영역 양측부를 라운딩시키는 단계; 액티브영역의 라운딩된 양측부 및 그와 접한 소자분리막 부분 상에 선택적으로 제2게이트절연막을 형성하는 단계; 마스크패턴을 제거하는 단계; 제1 및 제2게이트절연막 상에 게이트도전막을 형성하는 단계; 및 게이트도전막과 게이트절연막을 식각하는 단계;를 포함하는 반도체 소자의 제조방법을 제공한다. In order to achieve the above object, the present invention provides a semiconductor substrate having a PMOS transistor forming region and the NMOS transistor forming region and provided with a device isolation film defining an active region; Forming a first gate insulating film on the semiconductor substrate including the device isolation film; Forming a mask pattern on the first gate insulating layer to expose portions of the device isolation layer in the width direction in the PMOS transistor forming region and both sides of the active region in contact with the device isolation layer; Removing the exposed portion of the first gate insulating film; Rounding both sides of the active region of the PMOS transistor forming region exposed by removing the first gate insulating layer; Selectively forming a second gate insulating film on rounded both sides of the active region and a portion of the device isolation film in contact with the rounded portion of the active region; Removing the mask pattern; Forming a gate conductive film on the first and second gate insulating films; And etching the gate conductive layer and the gate insulating layer.

여기서, 상기 노출된 제1게이트절연막 부분은 건식 또는 습식식각 공정을 통해 제거하며, 상기 노출된 피모스 트랜지스터 형성지역의 액티브영역 양측부는 건식 또는 습식식각 공정을 통해 라운딩시킨다.Here, the exposed first gate insulating layer is removed through a dry or wet etching process, and both sides of the active region of the exposed PMOS transistor formation region are rounded by a dry or wet etching process.

(실시예)(Example)

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2d는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정별 단면도이다.2A through 2D are cross-sectional views illustrating processes of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

도 2a를 참조하면, 피모스 트랜지스터 형성지역과 엔모스 트랜지스터 형성지역을 가지는 반도체 기판에 공지의 STI 공정에 따라 트렌치를 형성한다. 이어서, 측벽 산화공정을 수행하여 상기 트렌치의 표면에 측벽산화막(22)을 형성한 후, 상기 측벽산화막(22)을 포함한 반도체 기판 전면 상에 균일한 두께로 라이너질화막(23)을 형성한다.Referring to FIG. 2A, trenches are formed in a semiconductor substrate having a PMOS transistor forming region and an NMOS transistor forming region according to a known STI process. Subsequently, the sidewall oxide layer 22 is formed on the surface of the trench by performing sidewall oxidation, and then the liner nitride layer 23 is formed on the entire surface of the semiconductor substrate including the sidewall oxide layer 22.

그다음, 상기 라이너질화막(23)을 포함한 트렌치를 완전히 매립하도록 절연막을 증착한 후, 이를 CMP(Chemical Mechanical Polishing)하여, 액티브영역(21)을 한정하는 트렌치형의 소자분리막(24)을 형성한다.Next, an insulating film is deposited to completely fill the trench including the liner nitride film 23, and then, by chemical mechanical polishing (CMP), a trench type device isolation film 24 defining the active region 21 is formed.

다음으로, 상기 소자분리막(24)과 액티브영역(21) 상에 산화공정을 통해 제1게이트절연막(25)을 형성한다. 그리고 나서, 상기 제1게이트절연막(25) 상에 피모스 트랜지스터 형성지역에서의 폭 방향에 따른 소자분리막과 그에 접한 액티브영역 양측부를 선택적으로 노출시키는 마스크패턴(26)을 형성해 준다.Next, a first gate insulating layer 25 is formed on the device isolation layer 24 and the active region 21 through an oxidation process. Then, a mask pattern 26 is formed on the first gate insulating layer 25 to selectively expose the device isolation layer along the width direction in the PMOS transistor formation region and both sides of the active region in contact with the device isolation layer.

도 2b를 참조하면, 상기 마스크패턴(26)에 의해 노출된 제1게이트절연막 부분을 습식 또는 건식 식각공정으로 제거한다. 그런다음, 상기 제1게이트절연막(25)이 제거되어 노출된 피모스 트랜지스터 형성지역의 액티브영역 양측부를 라운딩시 킨다. 여기서, 상기 노출된 액티브영역 양측부의 라운딩 공정은 건식 또는 습식식각 공정으로 수행한다.Referring to FIG. 2B, the portion of the first gate insulating layer exposed by the mask pattern 26 is removed by a wet or dry etching process. Thereafter, the first gate insulating layer 25 is removed to round both sides of the active region of the exposed PMOS transistor formation region. The rounding process on both sides of the exposed active region may be performed by a dry or wet etching process.

도면부호 B는 상기 식각공정에 의해 라운딩된 피모스 트랜지스터 형성지역의 액티브영역 양측부를 나타내며, 도시되지는 않았지만, 엔모스 트랜지스터 형성지역의 액티브영역 양측부는 라운딩되지 않았다.Reference numeral B denotes both sides of the active region of the PMOS transistor forming region rounded by the etching process, and although not shown, both sides of the active region of the NMOS transistor forming region are not rounded.

도 2c를 참조하면, 소자분리막(24)과 접한 측면이 라운딩된 피모스 트랜지스터 형성지역의 액티브영역 및 그와 접한 소자분리막 부분 상에 추가로 산화공정을 수행하여 선택적으로 제2게이트절연막(27)을 형성한다. 여기서, 상기 산화공정은 마스크패턴(26)이 제거되지 않은 상태에서 진행된다.Referring to FIG. 2C, the second gate insulating layer 27 is selectively oxidized by further performing an oxidation process on the active region of the PMOS transistor forming region where the side contact with the device isolation layer 24 is rounded and the part of the device isolation layer contacting with the device isolation layer 24. To form. Here, the oxidation process is performed in a state where the mask pattern 26 is not removed.

도 2d를 참조하면, 공지의 공정에 따라 마스크패턴을 제거하고, 이어서, 제1게이트절연막(25) 및 제2게이트절연막(27) 상에 게이트도전막(28)을 형성한다. Referring to FIG. 2D, the mask pattern is removed according to a known process, and then a gate conductive film 28 is formed on the first gate insulating film 25 and the second gate insulating film 27.

이후, 도시하지는 않았으나, 공지된 일련의 후속 공정들을 차례로 수행하여 본 발명에 따른 반도체 소자를 완성한다.Then, although not shown, the semiconductor device according to the present invention is completed by sequentially performing a series of subsequent known processes.

본 발명에 따르면, 소자분리막을 수직으로 형성함으로써 고집적 소자의 제조를 가능하게 함과 동시에 피모스 트랜지스터 형성지역의 액티브영역 양측부를 선택적으로 라운딩시킴으로써 HEIP현상이 심화되는 것을 방지할 수 있다. 아울러, 모서리 부분에 전기장이 집중되는 것을 방지하여 문턱전압을 감소시킬 수 있다. According to the present invention, it is possible to manufacture the highly integrated device by forming the device isolation layer vertically, and to prevent the HEIP phenomenon from deepening by selectively rounding both sides of the active region of the PMOS transistor formation region. In addition, it is possible to reduce the threshold voltage by preventing the electric field is concentrated in the corner portion.

도 3a는 피모스 트랜지스터의 액티브영역 양측부를 라운딩시켰을 때의 문턱전압 변화를 나타낸 그래프이고, 도 3b는 라운딩시키지 않았을 때의 문턱전압 변화를 나타낸 그래프로서, 도시된 바와 같이, 라운딩 공정을 수행한 본 발명의 경우 라운딩 공정을 수행하지 않은 경우에 비해 문턱전압 증가 현상이 대략 24% 정도 개선되었음을 알 수 있다. FIG. 3A is a graph illustrating a change in threshold voltage when the both sides of the active region of the PMOS transistor are rounded, and FIG. 3B is a graph illustrating a change in threshold voltage when the PMOS transistor is not rounded, as shown in FIG. In the case of the present invention, it can be seen that the threshold voltage increase phenomenon is improved by about 24% compared with the case where the rounding process is not performed.

도 3c는 웨이퍼 내의 균일도 분포를 나타내는 도면으로서, 도시된 바와 같이, 라운딩 공정을 수행한 경우(A)가 상기 라운딩 공정을 수행하지 않은 경우(B)에 비해 웨이퍼 내의 균일도가 대략 78% 정도 개선되었음을 알 수 있다.FIG. 3C illustrates a uniform distribution in the wafer. As shown in FIG. 3C, the uniformity in the wafer is improved by about 78% compared to the case where the rounding process (A) is not performed (B). Able to know.

이상, 여기에서는 본 발명을 특정 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다.As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the scope of the following claims is not limited to the scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

이상에서와 같이, 본 발명은 고집적 소자를 제조하기 위해 수직으로 형성된 액티브영역의 양측부를 라운딩시킴으로써 전기장이 집중되는 것을 막을 수 있으며, 따라서, 소자분리막의 측면각도가 수직에 가까워짐에 따라 피모스 트랜지스터에서 유발되는 HEIP 현상이 심화되는 것을 방지할 수 있다. As described above, the present invention can prevent the electric field from being concentrated by rounding both sides of the active region formed vertically to manufacture the highly integrated device, and thus, as the side angle of the device isolation layer approaches the vertical, The induced HEIP phenomenon can be prevented from deepening.

또한, 이 방법을 마스크패턴을 이용하여 피모스 트랜지스터 형성지역의 액티브영역 양측부에만 선택적으로 적용함으로써 소자의 리플레쉬 특성 저하와 트랜지스터의 열화현상을 방지할 수 있다. 즉, 소자분리막과 접한 액티브영역 부분 전체가 아닌, 폭 방향에 따른 피모스 트랜지스터 형성지역에서의 액티브영역 양측부만을 라운딩시킴으로써, 피모스 트랜지스터에서 발생하는 HEIP 현상을 효과적으로 개선함과 동시에 엔모스 트랜지스터의 특성을 그대로 유지할 수 있다.In addition, by selectively applying this method only to both sides of the active region in the PMOS transistor formation region using a mask pattern, it is possible to prevent degradation of the refresh characteristics of the device and deterioration of the transistor. That is, by rounding only the both sides of the active region in the PMOS transistor formation region along the width direction instead of the entire active region portion in contact with the device isolation film, the HEIP phenomenon occurring in the PMOS transistor can be effectively improved and the NMOS transistor Characteristics can be kept as it is.

Claims (3)

피모스 트랜지스터 형성지역 및 엔모스 트랜지스터 형성지역을 가지며, 액티브영역을 한정하는 소자분리막이 구비된 반도체 기판을 제공하는 단계;Providing a semiconductor substrate having a PMOS transistor forming region and an NMOS transistor forming region, the semiconductor substrate having an isolation layer defining an active region; 상기 소자분리막을 포함한 반도체 기판 상에 제1게이트절연막을 형성하는 단계;Forming a first gate insulating film on the semiconductor substrate including the device isolation film; 상기 제1게이트절연막 상에 피모스 트랜지스터 형성지역에서의 폭 방향에 따른 소자분리막 부분과 그에 접한 액티브영역 양측부를 노출시키는 마스크패턴을 형성하는 단계;Forming a mask pattern on the first gate insulating layer to expose portions of the device isolation layer in the width direction of the PMOS transistor forming region and both sides of the active region in contact with the device isolation layer; 상기 노출된 제1게이트절연막 부분을 제거하는 단계;Removing the exposed portion of the first gate insulating film; 상기 제1게이트절연막이 제거되어 노출된 피모스 트랜지스터 형성지역의 액티브영역 양측부를 라운딩시키는 단계;Rounding both sides of an active region of the PMOS transistor forming region exposed by removing the first gate insulating layer; 상기 액티브영역의 라운딩된 양측부 및 그와 접한 소자분리막 부분 상에 선택적으로 제2게이트절연막을 형성하는 단계;Selectively forming a second gate insulating film on rounded both sides of the active region and a portion of the device isolation film in contact with the rounded portion of the active region; 상기 마스크패턴을 제거하는 단계;Removing the mask pattern; 상기 제1 및 제2게이트절연막 상에 게이트도전막을 형성하는 단계; 및Forming a gate conductive film on the first and second gate insulating films; And 상기 게이트도전막과 게이트절연막을 식각하는 단계;를 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.Etching the gate conductive film and the gate insulating film. 제 1 항에 있어서, 상기 노출된 제1게이트절연막 부분을 제거하는 단계는 건 식 또는 습식식각으로 수행하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein removing the exposed portion of the first gate insulating layer is performed by dry or wet etching. 제 1 항에 있어서, 상기 노출된 액티브영역의 끝단을 라운딩시키는 단계는 건식 또는 습식식각으로 수행하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the rounding of the exposed end of the active region is performed by dry or wet etching.
KR1020060018187A 2006-02-24 2006-02-24 Method of manufacturing semiconductor device KR20070088054A (en)

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