KR20070088007A - Driving circuit and liquid crystal display including the same - Google Patents

Abstract

A driving circuit and an LCD(Liquid Crystal Display) device including the same are provided to display superior images on the LCD device by maintaining constant read and write directions in a memory. A driving circuit includes an interface unit(710), a memory(750), an address counter(730), and first and second controllers(720,760). The interface unit inputs and outputs a signal. The memory performs read and write operations based on a control signal. The address counter determines read and write directions of the memory. The first controller controls the write direction of the address counter into both directions. The second controller controls the read direction of the address counter into both directions. The read and write directions are the same.

Description

A driving circuit and a liquid crystal display including the same {DRIVING CIRCUIT AND LIQUID CRYSTAL DISPLAY INCLUDING THE SAME}

1 is a plan view illustrating a liquid crystal panel assembly according to an embodiment of the present invention.

2 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is an equivalent circuit diagram illustrating one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

4 is a block diagram showing a portion of a driving circuit of a liquid crystal display according to an embodiment of the present invention.

5A and 5B show the recording and reading directions of the liquid crystal display according to an embodiment of the present invention.

<Description of Drawing>

3: liquid crystal layer 110, 210: substrate

100: lower panel 191: pixel electrode

200: upper display panel 220: light blocking member

270: common electrode 300: liquid crystal panel assembly

400: gate driver 500: data driver

The present invention relates to a driving circuit and a liquid crystal display including the same.

The liquid crystal display is one of the most widely used flat panel display devices, and includes two display panels on which an electric field generating electrode such as a pixel electrode and a common electrode are formed, and a liquid crystal layer interposed therebetween. The liquid crystal display generates an electric field in the liquid crystal layer by applying a voltage to the field generating electrode, thereby determining an orientation of liquid crystal molecules in the liquid crystal layer and controlling the polarization of incident light to display an image.

The liquid crystal display also includes a switching element connected to each pixel electrode and a plurality of signal lines such as a gate line and a data line for controlling the switching element and applying a voltage to the pixel electrode. The gate line generates a gate signal generated by the gate driving circuit, the data line transfers the data voltage generated by the data driving circuit, and the switching element transfers the data voltage to the pixel electrode according to the gate signal.

The liquid crystal display device is mounted on a portable device such as a mobile phone to represent various images. Previously, the liquid crystal display mounted in a mobile phone could perform its function even with a still image. However, recently, as the functions of mobile phones are diversified, liquid crystal displays are used for display screens or video playback of cameras. In this case, higher image quality is required than the liquid crystal display mounted in the existing mobile phone.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a driving circuit capable of increasing the degree of completeness of an image and a liquid crystal display including the same.

According to an aspect of the present invention, there is provided a driving circuit including an interface unit for receiving and outputting a signal, a memory for reading and writing based on a control signal, and an address counter for determining a writing and reading direction of the memory ( address counter), a first control unit for controlling the writing direction of the address counter in both directions, and a second control unit for controlling the determination direction of the address counter in both directions, wherein the writing direction and the reading direction are the same.

The apparatus may further include a write latch unit configured to store an output signal of the first controller and transmit the output signal to the memory.

The apparatus may further include a read latch unit configured to store an output signal of the memory and transmit the output signal to the interface unit.

According to another aspect of the present invention, a liquid crystal display includes a display panel unit including a plurality of pixels connected to a gate line and a data line, a memory for writing and reading according to a control signal, image data input from the memory, and input from the outside. A signal controller for outputting a plurality of output control signals based on the input control signal, a gate driver generating a gate signal according to the output control signal, and applying the gate signal to the gate line, and generating a data signal according to the output control signal And a data driver for applying to the data line, wherein the write and read directions of the memory coincide with each other.

A first control unit for controlling the recording direction in both directions, and a second control unit for controlling the reading direction in both directions.

The gate driver may be integrated in the display panel.

The gray voltage generator may further include a gray voltage generator.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

First, a liquid crystal display according to an exemplary embodiment of the present invention will be described with reference to FIGS. 1 to 3.

1 is a schematic diagram of a liquid crystal display according to an embodiment of the present invention, FIG. 2 is a block diagram of a liquid crystal display according to an embodiment of the present invention, and FIG. 3 is a liquid crystal display according to an embodiment of the present invention. An equivalent circuit diagram for one pixel of the device.

Referring to FIG. 1, the liquid crystal display according to the present exemplary embodiment is mounted on the display panel 300, the flexible printed circuit film (FPC) 650 attached to the display panel 300, and the display panel 300. Integrated chip 700.

The display panel 300 may include a display area DA and a peripheral area PA in which an image is displayed, and a light blocking layer (not shown) for blocking light may be provided in the peripheral area PA. A flexible printed circuit film 650 may be attached to the peripheral area to transmit a signal from the outside to the integrated chip 700.

The flexible printed circuit film 650 is attached near one side of the display panel 300. One end of the flexible printed circuit film 650 is provided with an input unit 660, and a signal is transmitted to the display panel 300 from the outside through the input unit 660.

As shown in FIG. 2, the liquid crystal display according to the exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a pair of gate driver 400 and a data driver 500 connected thereto. The gray voltage generator 800 connected to the data driver 500 and a signal controller 600 for controlling the gray voltage generator 800 are included.

The liquid crystal panel assembly 300 may include a plurality of signal lines G ₁ -G _{n and} D ₁ -D _m and a plurality of pixels PX connected to the plurality of signal lines G ₁ -G _{n and} D ₁ -D _m , which are arranged in a substantially matrix form. Include.

Most of the pixel PX and the plurality of signal lines G ₁ -G _{n and} D ₁ -D _m are positioned in the display area DA, and the gate driver 400 is positioned in the peripheral area PA. The peripheral area PA of the side where the gate driver 400 is located has a larger width.

In contrast, in the structure shown in FIG. 3, the liquid crystal panel assembly 300 includes lower and upper panels 100 and 200 facing each other and a liquid crystal layer 3 interposed therebetween.

The signal line includes a plurality of gate lines G ₁ -G _n transmitting a gate signal (also referred to as a “scan signal”) and a plurality of data lines D ₁ -D _m transmitting a data signal. The gate lines G ₁ -G _n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

The display signal lines G ₁ -G _n and D ₁ -D _m are generally wide at the point where they are connected to the flexible printed circuit film 650 to form pads (not shown), and are flexible with the display panel 300. The printed circuit film 650 is attached with an anisotropic conductive film (not shown) for electrical connection of these pads.

Each pixel PX includes a switching element Q connected to a signal line, a liquid crystal capacitor Clc, and a storage capacitor Cst connected thereto. Holding capacitor Cst can be omitted as needed.

The switching element Q is a three-terminal element of a thin film transistor or the like provided in the lower panel 100, the control terminal of which is connected to the gate line G _i , and the input terminal of which is connected to the data line D _j . The output terminal is connected to the liquid crystal capacitor Clc and the storage capacitor Cst.

The liquid crystal capacitor Clc has two terminals, the pixel electrode 191 of the lower panel 100 and the common electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 191 and 270 is a dielectric material. It functions as a sieve. The pixel electrode 191 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives the common voltage Vcom. Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, at least one of the two electrodes 191 and 270 may be formed in a linear or bar shape.

The storage capacitor Cst, which serves as an auxiliary part of the liquid crystal capacitor Clc, is formed by overlapping a separate signal line (not shown) and the pixel electrode 191 provided on the lower panel 100 with an insulator interposed therebetween. A predetermined voltage such as the common voltage Vcom is applied to the separate signal line. However, the storage capacitor Cst may be formed such that the pixel electrode 191 overlaps the front gate line directly above the insulator.

On the other hand, in order to implement color display, each pixel PX uniquely displays one of the primary colors (spatial division) or each pixel PX alternately displays the primary colors over time (time division). The desired color is recognized by the spatial and temporal sum of these primary colors. Examples of the primary colors include three primary colors such as red, green, and blue. FIG. 3 illustrates that each pixel PX includes a color filter 230 representing one of the primary colors in an area of the upper panel 200 corresponding to the pixel electrode 191 as an example of spatial division. Unlike in FIG. 3, the color filter 230 may be formed above or below the pixel electrode 191 of the lower panel 100.

At least one polarizer (not shown) for polarizing light is attached to an outer surface of the liquid crystal panel assembly 300.

A gate driver 400, a gate line (G ₁ -G _n) and is connected to the gate turn-on voltage (Von), and a gate signal consisting of a combination of a gate-off voltage (Voff), a gate line (G ₁ of the liquid crystal panel assembly 300 -G _n ). The gate driver 400 includes a plurality of stages substantially arranged in a row as a shift register, and together with the signal lines G ₁ -G _n , D ₁ -D _m , and the thin film transistor switching element Q. In the same process, the liquid crystal panel assembly 300 may be formed and integrated, and connected to the integrated chip 700 through the signal line SL1.

The integrated chip 700 includes a gray voltage generator 700, a data driver 500, and a signal controller 600 illustrated in FIG. 2. The integrated chip 700 may include a wiring provided in the peripheral area PA of the display panel 300 to receive and process a signal received from an external signal through signal lines provided in the connection part 660 and the flexible printed circuit film 650. These are controlled by supplying the display panel 300 through the control panel.

The gray voltage generator 800 generates two sets of gray voltages (or reference gray voltage sets) related to the transmittance of the pixel PX. One of the two sets has a positive value for the common voltage Vcom and the other set has a negative value.

The data driver 500 is connected to the data lines D ₁ -D _m of the liquid crystal panel assembly 300 and selects a gray voltage from the gray voltage generator 800 and uses the data line D ₁ as a data signal. -D _m ). However, when the gray voltage generator 800 provides only a predetermined number of reference gray voltages instead of providing all of the voltages for all grays, the data driver 500 divides the reference gray voltages to divide the gray voltages for all grays. Generate and select the data signal from it.

The signal controller 600 controls the gate driver 400, the data driver 500, and the like.

Next, the operation of the liquid crystal display will be described in detail.

The signal controller 600 receives input image signals R, G, and B and an input control signal for controlling the display thereof from an external graphic controller (not shown). Examples of the input control signal include a vertical sync signal Vsync, a horizontal sync signal Hsync, a main clock MCLK, and a data enable signal DE.

The signal controller 600 properly processes the input image signals R, G, and B according to operating conditions of the liquid crystal panel assembly 300 based on the input image signals R, G, and B and the input control signal, and controls the gate. After generating the signal CONT1 and the data control signal CONT2, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signal DAT are transmitted to the data driver 500. Export to).

The gate control signal CONT1 defines a duration of the gate clock signal CPV and the gate on voltage Von that control the output period of the scan start signal STV and the gate on voltage Von indicating the start of the scan. The output enable signal OE may be further included.

The data control signal CONT2 is a load for applying a data signal to the horizontal synchronization start signal STH and the data lines D ₁ -D _m indicating the start of image data transmission for the pixels PX in one row [bundling]. Signal LOAD and data clock signal HCLK. The data control signal CONT2 is also an inverted signal that inverts the voltage polarity of the data signal relative to the common voltage Vcom (hereinafter referred to as " polarity of the data signal " by reducing the " voltage polarity of the data signal for the common voltage &quot;) RVS) may be further included.

According to the data control signal CONT2 from the signal controller 600, the data driver 500 receives the digital image signal DAT for the pixels PX in one row (bundling), and each digital image signal DAT. By converting the digital image signal DAT into an analog data signal by selecting a gray scale voltage corresponding to), it is applied to the corresponding data lines D ₁ -D _m .

The gate driver 400 applies the gate-on voltage Von to the gate lines G ₁ -G _n in response to the gate control signal CONT1 from the signal controller 600, thereby applying the gate lines G ₁ -G _n . Turn on the switching element (Q) connected to. Then, the data signal applied to the data lines D ₁ -D _m is applied to the pixel PX through the switching element Q turned on.

The difference between the voltage of the data signal applied to the pixel PX and the common voltage Vcom is shown as the charging voltage of the liquid crystal capacitor Clc, that is, the pixel voltage. The arrangement of the liquid crystal molecules varies depending on the magnitude of the pixel voltage, thereby changing the polarization of light passing through the liquid crystal layer 3. The change in polarization is represented by a change in transmittance of light by a polarizer attached to the display panel assembly 300.

This process is repeated in units of one horizontal period (also referred to as "1H" and equal to one period of the horizontal sync signal Hsync and the data enable signal DE), thereby all the gate lines G ₁ -G _n. ), The gate-on voltage Von is sequentially applied to the data signal to all the pixels PX, thereby displaying an image of one frame.

When one frame ends, the state of the inversion signal RVS applied to the data driver 500 is controlled so that the next frame starts and the polarity of the data signal applied to each pixel PX is opposite to the polarity of the previous frame. "Invert frame"). In this case, the polarity of the data signal flowing through one data line is changed (eg, row inversion and point inversion) or the polarity of the data signal applied to one pixel row is different depending on the characteristics of the inversion signal RVS within one frame. (E.g. column inversion, point inversion).

Then, the integrated chip 700 according to an embodiment of the present invention will be described in more detail with reference to FIG. 4.

4 is a block diagram illustrating some driving circuits of an integrated chip 700 of a liquid crystal display according to an exemplary embodiment of the present invention, and FIGS. 5A and 5B illustrate driving of a liquid crystal display according to an exemplary embodiment of the present invention. It is a figure explaining a form.

Referring to FIG. 4, the driving circuit of the liquid crystal display according to the present invention may include an interface unit 710, first and second controllers 720 and 760, first and second latch units 741 and 742, and a memory device. 750).

The interface unit 710 receives an image data signal DAT and an operation control signal CS of the memory 750 from the outside and inputs the same into the driving circuit, and transmits a signal transmitted from the driving circuit to the integrated chip 700. The other part is output to the data driver 500, the signal controller 600, the gray voltage generator 800, and the like. The memory 750 operation control signal CS may be applied by a micro processing unit (MPU), and for example, a write enable signal (write enable, WE), a read enable signal (read enable, RE), and an address counter signal ( AC).

The first control unit 720 receives various signals from the interface unit 710 and controls the write direction of the memory in both directions. That is, it controls whether the image data signal DAT or the like is recorded from the upper left of the screen to the lower right direction or from the lower right of the screen to the upper left direction.

The second control unit 760 receives various signals from the interface unit 710 to control the read direction of the memory in both directions. That is, it controls whether the image data signal DAT or the like is read from the upper left of the screen to the lower right direction or from the lower right of the screen to the upper left direction.

The first and second controllers 720 and 760 control the write and read directions of the memory 730 to always match. That is, as shown in FIG. 5A, when the write operation (solid line) of the memory 730 advances from the bottom right of the display area DA to the upper left direction, the read operation (dotted line) of the memory 730 is also displayed in the display area DA. Proceed in the upper left direction from the lower right. In addition, as shown in FIG. 5B, when the writing operation (solid line) of the memory 730 proceeds from the upper left to the lower right of the display area DA, the reading operation (dotted line) of the memory 730 is also performed in the display area DA. It progresses from the upper left to the lower right.

The address counter 730 receives the output signals of the first and second controllers 720 and 760 to determine the reading and writing directions of the memory 750.

The memory 750 performs a read operation according to the output signal of the address counter 730 and the output signal of the first control unit 720, and performs a write operation according to the output signal of the address counter 730 to interface unit 710. Output to the outside of driving circuit through. As described above, since the first and second controllers 720 and 760 control the read and write directions in both directions, respectively, the memory 750 may perform both read and write operations in both upper and lower left and lower right directions. have. In this case, as shown in Figs. 5A and 5B, the progress directions of the read and write operations are always the same.

The first latch unit 741 stores the output signal of the first control unit 720 and transfers the output signal to the memory 750, and the second latch unit 742 stores the output signal of the memory 750 and then the interface unit. Forward to 710.

In this manner, not only the recording direction but also the reading direction can be selected as one of the bidirectional directions of the display area DA, that is, the upper left lower right and the lower right upper left, so that the recording and reading directions can always be constantly adjusted. Then, the quality of the image may be improved in a liquid crystal display device in which reading and writing of the memory is performed in real time, such as a moving image or a camera image.

According to the present invention, the reading and writing directions of the memory can be adjusted constantly, so that the image of the liquid crystal display device in which recording and reading is performed in real time can be excellently represented.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (7)

Interface unit for receiving and outputting signals Memory for reading and writing based on control signals, An address counter for determining a writing and reading direction of the memory, A first controller for controlling the writing direction of the address counter in both directions; and A second control unit controlling the determination direction of the address counter in both directions Including, The driving direction and the reading direction are the same. In claim 1, And a write latch unit which stores the output signal of the first controller and transfers the output signal to the memory. In claim 1, And a read latch unit configured to store an output signal of the memory and transmit the stored output signal to the interface unit. A display panel unit including a plurality of pixels connected to the gate line and the data line; Memory for recording and reading in accordance with control signals, A signal controller configured to emit a plurality of output control signals based on the image data input from the memory and an input control signal input from the outside; A gate driver for generating a gate signal according to the output control signal and applying the gate signal to the gate line; A data driver for generating a data signal according to the output control signal and applying the data signal to the data line Including, And write directions of the memory coincide with each other. In claim 4, A first controller for controlling the recording direction in both directions, and A second control unit controlling the reading direction in both directions Further comprising a liquid crystal display device. In claim 4, And the gate driver is integrated in the display panel. In claim 4, And a gray voltage generator which generates a gray voltage.

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