KR20070084317A - Trench capacitor with hybrid surface orientation substrate - Google Patents

Abstract

Methods of forming a deep trench capacitor memory device and logic devices on a single chip with hybrid surface orientation. The methods allow for fabrication of a system-on-chip (SoC) with enhanced performance including n-type complementary metal oxide semiconductor (CMOS) device SOI arrays and logic transistors on (100) surface orientation silicon, and p-type CMOS logic transistors on (110) surface orientation silicon. In addition, the method fabricates a silicon substrate trench capacitor within a hybrid surface orientation SOI and bulk substrate. Cost-savings is realized in that the array mask open and patterning for silicon epitaxial growth is accomplished in the same step and with the same mask.

Description

TRENCH CAPACITOR WITH HYBRID SURFACE ORIENTATION SUBSTRATE}

The present invention relates generally to semiconductor device fabrication, and more particularly, to a method of forming a semiconductor device on a hybrid surface orientation and a structure so formed.

Semiconductor device manufacturers are constantly working to improve the performance of semiconductor devices. One challenge facing the semiconductor industry today is the implementation of memory and logic devices on a single chip while maintaining process simplicity and transistor performance. These devices are called "System-On-Chips" because the electronics for a complete product are contained on a single chip. One approach currently employed to improve the performance of SoCs is to fabricate different types of logic devices on silicon substrates with optimal surface orientation. As used herein, "surface orientation" refers to the crystal structure or periodic arrangement of silicon atoms on the wafer surface. Specifically, nFETs can be optimized by being created on silicon with a surface orientation of (100), while pFETs can be optimized by being created on silicon with a surface orientation of (110). In addition, memory elements and n-type field effect transistors (nFETs) can typically be optimized when generated on a silicon-on-insulator (SOI) substrate, but p-type field effect transistors ( pFETs are typically optimized when created on bulk silicon.

In addition to the aforementioned challenges, additional challenges exist when manufacturing the hybrid orientation logic device and memory device (eg, silicon deep trench capacitors used in Dynamic Random Access Memory (DRAM)) together. Specifically, in deep trench capacitor memory devices, manufacturing costs are needed because different masks are needed to open the deep trenches for the capacitors and to pattern them for silicon epitaxial growth for pFET logic devices. Is added. In addition, memory devices may also have optimal substrate requirements. For example, memory devices, like nFETs, are typically optimized when created on an SOI substrate.

In view of the foregoing, it is difficult to manufacture memory elements and different types of logic elements while maintaining performance. Thus, in the related art, there is a need for an improved method of fabricating memory and logic elements on a single chip with hybrid surface orientation.

The present invention includes a method of forming deep trench capacitor memory elements and logic elements on a single chip with hybrid surface orientation. The method includes a logic transistor and an n-type Complementary Metal Oxide Semiconductor (CMOS) device SOI array on (100) surface-oriented silicon, and a p-type CMOS logic transistor on (110) surface-oriented silicon. The system-on-chip (SoC) can be manufactured with improved performance. The method also fabricates silicon substrate trench capacitors in hybrid surface oriented SOI and bulk substrates. Cost savings are realized because array mask opening and silicon epitaxial growth patterning are achieved at the same stage and with the same mask.

A first aspect of the present invention is directed to a method of forming deep trench capacitor memory elements and logic elements on a single chip having a hybrid surface orientation, which method comprises a bulk silicon substrate having a first surface orientation and a different agent thereon. Providing a silicon-on-insulator (SOI) region having two surface orientations; Using a hard mask to form first and second openings through the SOI region to the bulk silicon substrate; Forming a spacer in each opening; Forming epitaxially grown silicon capped with a dielectric in the second opening; Opening a deep trench through the first opening and into the bulk silicon substrate; Forming a deep trench capacitor in the deep trench; Forming a shallow trench isolation (STI), and forming a logic element.

A second aspect includes a method of providing a substrate for forming deep trench capacitor memory elements and logic elements on a single chip having a hybrid surface orientation, which method differs from a bulk silicon substrate having a first surface orientation above and different from above. Providing a silicon-on-insulator (SOI) region having a second surface orientation; Using a single hard mask, a first opening through the SOI region to be used to fabricate a deep trench capacitor, and the SOI region to fabricate a first type of logic device on the first surface orientation. Passing through to form a second opening into the bulk silicon substrate.

A third aspect of the invention relates to an electronic structure, which structure is a bulk silicon substrate having a first surface orientation, a silicon-on-insulator (SOI) having a different second surface orientation thereon, and the SOI region vertically And an electronic device partially located within and partially within the bulk silicon substrate.

The foregoing and other features of the present invention will become apparent from the following more detailed description of embodiments of the invention.

DETAILED DESCRIPTION Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, and these drawings denote like reference numerals for like elements.

1 is a diagram illustrating an electronic structure formed according to an embodiment of the present invention.

2 through 10 illustrate the steps of one embodiment of a method of forming the electronic structure of FIG. 1.

Referring to the accompanying drawings, FIG. 1 is a system-on-with deep trench capacitor memory elements and logic elements on a single chip having a hybrid surface orientation, made according to one embodiment of the method according to the present invention. The chip electronic structure 10 is shown. This structure 10 is a bulk silicon based substrate 12 having a first surface orientation, such as (110), and a silicon-on-insulator (SOI) having a different second surface orientation, such as (100), above. Region 14 is included. The SOI region 14 includes a silicon layer 16 on buried silicon dioxide (BOX) 18. The nFET array 30 is separated by a shallow trench isolation (STI) 34 from the first type of logic element 32 (eg, nFET) 14 on a portion of the SOI region 14. Located on another part of the. Thus, the nFET array 30 and the first logic element 32 are both placed on the second surface orientation of the SOI 12, such as (100). The first type of logic element (nFET) 32 is separated from another type of logic element 40, such as a pFET, by another STI 44. A second type of logic element 40 is located on the epitaxial silicon region 42 extending through the SOI region 14 to the bulk silicon substrate 12. The epitaxial silicon region 42 has a first surface orientation, such as 110, of the bulk silicon substrate 12.

The structure 10 also includes gain memory cells, non-planar MOSFET transistors, FINFETs, bipolar transistor devices, static random access memory (SRAM) cells, flash memory, passive electronic devices (e.g., resistors, capacitors, fuses, Diodes and electrostatic protection devices), and other devices such as latchup protection devices, but include electronic devices 50 to be described herein as deep trench capacitors. As a trench capacitor, the electronic device 50 includes a doped buried plate 52 and a node dielectric 54 surrounding the trench region 56, typically filled with doped polysilicon. Trench capacitor 50 is partially located in SOI region 14 vertically and electrically separated from SOI region 14 by STI 34. The trench capacitor 50 also includes a top 60 adjacent the SOI region 14 and a bottom 62 positioned (optionally) wider than the top 60. Bottom 62 is positioned under buried silicon dioxide 18 in SOI region 14. The buried plate 52 surrounds the lower portion 62.

2 to 9, an embodiment of forming the structure 10 will now be described. 2 provides a bulk silicon substrate 12 having a first surface orientation, such as (110), with a silicon-on-insulator (SOI) region 14 having a different second surface orientation, such as (100), on top. A number of steps are shown, including the first step of providing.

FIG. 2 also shows a first opening 80 and a second opening 82 through the SOI region 14 to the bulk silicon substrate 12 using a hard mask 84, i.e., a pattern, a dry etching method. The steps are shown. The first opening 80 will be used to form the deep trench capacitor 18 (FIG. 1). The second opening 82 will be used to finally form the epitaxial silicon region 42 (FIG. 1) on which the logic element 40 (FIG. 1) is finally formed. Thus, using a single hard mask 84, a first opening 80 through the SOI region 14 and a first surface orientation, such as over (110), to be used to fabricate the deep trench capacitor 50. A second opening 82 is formed through the SOI region 14 to the bulk silicon substrate 12 for fabricating the logic element 40. Hard mask 84 may include, for example, silicon nitride or any other conventional hard mask material. Further, as shown, the width W1 of the first opening 80 is not as wide as the width W2 of the second opening 82, that is, W2> W1.

3 and 4A show a step of forming a spacer 86 (FIG. 4A) in each opening as a next step. Spacer 86 (FIG. 4A) may be formed in any known or later developed manner, such as thin conformal deposition, such as low pressure chemical vapor deposition (LPCVD) followed by anisotropic etching. have. Spacer 86 (FIG. 4A) may comprise, for example, silicon nitride or any other conventional spacer material. In one embodiment, the thickness of the spacer 86 is less than one third of the diameter of the first opening 80 W1 (FIG. 2).

4A and 4B and FIGS. 5A-5E illustrate two other embodiments for forming epitaxially grown silicon that is capped with a dielectric in the second opening 82. Referring to the first embodiment shown in Figs. 4A and 4B, the first step shown in Fig. 4A is to epitaxially grow silicon 88 in each of the openings 80 and 82 to form the epitaxial silicon 88. To have this first surface orientation, such as (110). Then, as also shown in FIG. 4A, a dielectric cap 90 is formed over the epitaxial silicon 88 in each of the openings 80 and 82, and then planarized by chemical mechanical polishing (CMP). This step may for example planarize the epitaxial silicon 88 (e.g., by wet chemical etching or dry etching of sulfur hexafluoride (SF ₆ ), etc.) in each opening 80, 82 to form a recess. And depositing dielectric 90 (eg, by LPCVD) and then planarizing it again. In one embodiment, dielectric cap 90 may comprise silicon dioxide. However, this is not essential. Finally, as shown in FIG. 4B, in the first opening 80, a dielectric is formed using a block mask 89 made of, for example, silicon carbide (SiC), silicon nitride (Si ₃ N ₄ ), or another organic mask material. The cap 90 is removed to the epitaxial silicon 88.

The second embodiment for forming epitaxially grown silicon capped with a dielectric in the second opening 82 first substantially fills the first opening 80 and shows the second opening (as shown in FIG. 5A). Depositing the first dielectric 92 uniformly to partially fill 82. This occurs when the width W1 of the first opening 80 is smaller than the width W2 of the second opening 82, that is, when W2> W1. In one embodiment, the first dielectric 92 is silicon dioxide. However, other conformal dielectrics may also be used. Next, as shown in FIG. 5B, the first dielectric 92 is removed from the second opening 82. As shown in FIG. 5C, the next step is to epitaxially grow silicon 94 in the second opening 82 such that the epitaxial helicon 94 has a first surface orientation, such as 110. . Next, as shown in FIG. 5D, a second dielectric cap 96 is formed over the epitaxial silicon 94 in the second opening 82. The second dielectric may comprise silicon nitride. However, this is not essential. Finally, as shown in FIG. 5E, the first dielectric 92 is removed from the first opening 80.

Next, as shown in FIG. 6, the deep trench 100 is opened through the first opening 80 to the inside of the bulk silicon substrate 12. Using the embodiment of FIGS. 4A and 4B, this step passes through the epitaxial silicon 88 (FIG. 4B) remaining in the first opening 80 after removal of the dielectric 90 (FIG. 4A). 100). Block mask 89 (FIG. 4B) may be removed, or may remain in place, as shown in FIG. 6, wherein a highly selective anisotropic dry etch method (e. G., For patterning deep trench 100) is employed. , Dry etching feed gas containing silicon tetrachloride (SiCl ₄ ), HBR, and chlorine (Cl).

FIG. 7 shows the bulk silicon substrate 12 and below the SOI region 14, i.e., buried silicon dioxide, in order to increase the storage capacitance of the capacitor 50 (FIG. 1), for example using isotropic silicon etching. 18) An optional step of extending deep trench 100 down is shown. This step may also include forming the buried plate 52 in the extended deep trench 100 to improve the trench capacity. The buried plate 52 may be formed by diffusion of an arsenic (As) -containing gas or by wet stripping following thin film deposition and diffusion containing As. Spacer 86 protects the SOI region 14 during the process and may then be removed from the first opening 80.

8 and 9 illustrate forming the deep trench capacitor 50 in the deep trench 100 (FIG. 7). This step may include first depositing a node dielectric 54 in the first opening 80 and the deep trench 100 (FIG. 7), as shown in FIG. 8. In addition, as shown in FIG. 8, the second step is a CMP method followed by LPCVD, in which the first opening 80 and the deep trench 100 (FIG. 7) are doped with a node polysilicon 110 such as As. Filling with polysilicon doped with. The third step is to remove the doped node silicon 110 in the first opening 80, for example up to approximately the top surface of the buried silicon dioxide 18, as shown in FIG. 9, which is not necessary. . The removal method is preferably a dry etching method such as SF ₆ and a feed gas. Subsequently, the node dielectric 54 is formed on the first opening 80 over the buried silicon dioxide 18 of the SOI region 14 by using a wet or dry isotropic etching method such as hydrofluoric acid (HF) and ethylene glycol. ) From the side wall. As an option for this step, sidewall nitride films (not shown) may be formed on the sidewalls of the first opening 80 to provide an interface, diffusion, and recrystallization barrier. This nitride film can be formed very thin, for example, about 10 GPa. Next, as shown in FIG. 9, the first opening 80 is filled with polysilicon 112, such as intrinsic or As doped polysilicon, and then planarized using LPCVD.

Referring to FIG. 10, a final step of the method may include forming recesses in polysilicon 94 and 112 to be hibernating with silicon 16 in SOI region 14, and a hard mask ( 84) (FIG. 9) and dielectric cap 96 (FIG. 9), and performing conventional processes to prepare additional structures, including depositing and stripping channel nitride. The next step is to form STIs 34, 44 (FIG. 1) and 120 using photolithography and dry etching, followed by logic elements (e.g., nFETs 32 and pFETs 40 in FIG. 1), If necessary, an additional memory element (eg, nFET array 30 of FIG. 1) is formed. Because different surface orientations are exposed, different structures can be located on different exposure orientations. As shown in FIG. 1, the NMOS array 30 and the nFET 32 are located on the (100) surface orientation of the SOI region 14, and the pFET 40 is positioned 110 of the epitaxial silicon region 42. Located on the surface orientation. While specific surface orientations and structures are shown, it is understood that other configurations may be possible. For example, the SOI region 14 may have a (110) surface orientation, and the substrate 12 may have a (100) surface orientation such that the epitaxial silicon region 42 has a (100) surface orientation. In this case, a logic NMOS is built on the bulk epitaxial silicon region 42 and the PMOS is built on the (110) surface oriented SOI region 14. In another example, other configurations including SOI and bulk of different semiconductor materials, such as III-V compounds, and other combinations of crystal orientations including (111) can also be used.

Although the invention has been described with respect to specific embodiments described above, many alternatives, modifications, and variations will be apparent to those skilled in the art. Accordingly, embodiments of the invention are illustrative only and not restrictive. Various changes can be made without departing from the spirit and scope of the invention as defined in the following claims.

The present invention is useful in the field of semiconductor devices, and more particularly in methods of manufacturing memory devices.

Claims (9)

In a method of forming a deep trench capacitor memory element and logic elements 32, 40 on a single chip having a hybrid surface orientation, Providing a bulk silicon substrate 12 having a first surface orientation and a silicon-on-insulator (SOI) region 14 having a different second surface orientation thereon; Using a hard mask (84) to form first and second openings (80, 82) through the SOI region (14) and into the bulk silicon substrate (12); Forming a spacer (86) in each opening (80, 82); Forming epitaxially grown silicon capped with a dielectric in the second opening (82); Opening a deep trench through the first opening (80) and into the bulk silicon substrate (12); Forming a deep trench capacitor in the deep trench; Forming shallow trench isolation (STI) 33, 34; Forming logic elements 32, 40 And forming a deep trench capacitor memory element and logic elements on a single chip having a hybrid surface orientation. The method of claim 1, wherein the first surface orientation is (110) and the second surface orientation is (100). 3. The method of claim 1, wherein forming the first and second openings (80, 82) comprises patterning and etching using a single mask. 4. The method of claim 3, wherein forming epitaxially grown silicon capped with the dielectric comprises: Epitaxially growing silicon in each opening to epitaxially grow the silicon such that the epitaxial silicon has the first surface orientation; Forming a dielectric cap (90) over the epitaxial silicon in each opening; Removing the dielectric cap 90 to the epitaxial silicon in the first opening 80. It comprises, forming method. The method of claim 4, wherein the forming of the dielectric cap 90 comprises: Planarizing the epitaxial silicon and forming a recess in each opening, depositing the dielectric, and then planarizing the dielectric. 4. The method of claim 1, wherein the first opening 80 is smaller than the second opening 92, and the forming of the dielectric capped epitaxially grown silicon comprises: Uniformly depositing a first dielectric to substantially fill the first opening (80) and partially fill the second opening (82); Removing the first dielectric from the second opening (82); Epitaxially growing silicon in the second opening (82) to epitaxially grow the silicon such that the epitaxial silicon has the first surface orientation; Forming a second dielectric cap (96) over the epitaxial silicon in the second opening (82); Removing the first dielectric from the first opening 80 It comprises, forming method. The method according to any one of claims 1 to 3, Extending the deep trench within the bulk silicon region and below the SOI region (14); Forming a buried plate 52 in the extended deep trench Further comprising, forming method. The method of any one of claims 1 to 3, wherein forming the trench capacitor, Depositing a node dielectric in said first opening (80) and in said deep trench; A first filling step of filling the first opening (80) and the deep trench with doped node polysilicon; Forming a recess in the doped node polysilicon in the first opening (80); Removing the node dielectric from the sidewall of the first opening (80) over the buried oxide of the SOI region (14); A second filling step of filling the first opening 80 with polysilicon to planarize It comprises, forming method. 9. The method of claim 8, further comprising forming sidewall nitride films on sidewalls of the first openings (80) prior to the second filling step.

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