CN101752227B - Manufacturing method of shallow groove isolation structure for MOS capacitance - Google Patents
Manufacturing method of shallow groove isolation structure for MOS capacitance Download PDFInfo
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- CN101752227B CN101752227B CN2009100553738A CN200910055373A CN101752227B CN 101752227 B CN101752227 B CN 101752227B CN 2009100553738 A CN2009100553738 A CN 2009100553738A CN 200910055373 A CN200910055373 A CN 200910055373A CN 101752227 B CN101752227 B CN 101752227B
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- mos capacitance
- isolation structure
- shallow groove
- groove isolation
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Abstract
The invention provides a manufacturing method of a shallow groove isolation structure for MOS capacitance, which comprises: forming a first shallow groove in a semiconductor substrate; growing insulation medium on the semiconductor substrate and in the first shallow groove; grinding the surface of the insulation medium to make the surface of the first shallow groove planar, and removing the insulation medium on the semiconductor substrate; forming a second shallow groove in the first shallow groove, wherein the second shallow groove is positioned on the MOS capacitance area of the semiconductor substrate; growing pad oxide layers on the side wall and the bottom of the second shallow groove; and growing polysilicon layers on the pad oxide layers. The shallow groove provided by the invention is used as the substrate of the MOS capacitance, effectively increasing the surface area of the MOS capacitance, thus greatly improving the storage capacity of the MOS capacitance.
Description
Technical field
The invention belongs to a kind of semiconductor technology, relate in particular to a kind of manufacture method that is used for the fleet plough groove isolation structure of mos capacitance.
Background technology
In integrated circuit flourish today, element downsizing and the integrated trend that is inevitable also are the important topics of all circles' develop actively.When component size is dwindled gradually, integrated level (Integration) improves gradually, and interelement isolation structure also must dwindle, so element separation technical difficulty degree also increases gradually.Element separation helps the application region oxidizing process, and (Local Oxidation, the field oxide that LOCOS) forms (Field Oxide) because field oxide is subject to beak (Birds Beak) characteristic of its profile, dwindles its size and have any problem in fact.In view of this; Existing other element separation methods continue to be developed; Wherein with shallow trench isolation from (Shallow Trench Isolation STI) is widely used most, especially is applied in the ic manufacturing process of time half micron (Sub-half Micron).
The manufacturing that shallow trench isolation leaves; The general silicon nitride that uses defines precipitous groove as hard mask with anisotropy (anisotropy) etching method (dry etching) on the semiconductor-based end, again groove is filled up oxide afterwards; Form oxide plug; With as the element fleet plough groove isolation structure, the element below 0.13 micron for example in the cmos device, all adopt shallow trench isolation to leave (STI) technology and form by the isolation between nmos pass transistor and the PMOS transistor.
Please refer to Fig. 1, Fig. 1 is the flow chart that the prior art fleet plough groove isolation structure is made, and in the manufacturing process of fleet plough groove isolation structure, prior art comprises the steps: step 111: on semiconductor-based bottom material, form said shallow trench; Step 112: carry out the annealing in process first time; Step 113: in said shallow trench sidewall and bottom grow liners oxide layer; Step 114: in said shallow trench, insert dielectric; Step 115: carry out the annealing in process second time; Step 116: said dielectric surface ground make the shallow trench flattening surface; Step 117: on the said semiconductor-based bottom material of said dielectric both sides, precipitate sacrificial oxide layer, on this shallow ditch groove structure, make mos capacitance afterwards.Because this shallow ditch groove structure is planar substrates, the surface area of the mos capacitance of making above that can't increase, the stored charge of the mos capacitance of making indifferent.
Summary of the invention
In order to solve the above not strong problem of mentioning of mos capacitance storage capacity of on common fleet plough groove isolation structure, making, the present invention provides a kind of manufacture method that can effectively improve the fleet plough groove isolation structure of mos capacitance storage capacity.
In order to achieve the above object, the present invention proposes a kind of manufacture method that is used for the fleet plough groove isolation structure of mos capacitance, comprising: in the semiconductor-based end, form first shallow trench; On the said semiconductor-based end with said first shallow trench in the dielectric of growing; Grind on surface to said dielectric, makes the said first shallow trench flattening surface, and remove the suprabasil said dielectric of said semiconductor; In said first shallow trench, form second shallow trench; In said second shallow trench sidewall and bottom grow liners oxide layer; Growing polycrystalline silicon layer on said second cushion oxide layer.
Optional, adopt the dry etching method on the said semiconductor-based end, to form first shallow trench among the said step S1.
Optional, adopt the dry etching method in said first shallow trench, to form second shallow trench among the said step S4.
Optional, said dielectric is a silica.
Optional, use the chemical meteorological precipitation method said cushion oxide layer of growing.
Optional, the material of said cushion oxide layer is silica or silicon dioxide.
Optional, the depth bounds of said shallow trench is 0.1 micron to 1 micron.
Optional, the depth bounds of said deep trench is 5 microns to 15 microns.
The beneficial effect of manufacture method that the present invention is used for the fleet plough groove isolation structure of mos capacitance is: the present invention forms shallow trench in the mos capacitance zone, has increased the surface area of mos capacitance, thereby has made the storage capacity of mos capacitance be greatly enhanced.
Description of drawings
Fig. 1 is the flow chart that the prior art fleet plough groove isolation structure is made;
Fig. 2 is the flow chart of embodiment of the manufacture method of the present invention's fleet plough groove isolation structure of being used for mos capacitance;
Fig. 3 is the fleet plough groove isolation structure sketch map that the present invention is used for mos capacitance.
Embodiment
The manufacture method that the present invention is used for the fleet plough groove isolation structure of mos capacitance below in conjunction with accompanying drawing and embodiment is done further to specify.
At first please refer to Fig. 2, Fig. 2 is the flow chart of first embodiment of the invention, on scheming, can see; First embodiment comprises the steps: step 11: in the semiconductor-based end, form first shallow trench; Said semiconductor-based bottom material is a silicon, and the general shape of said shallow trench can form shallow trench isolation and leave with reference to figure 3; The general silicon nitride that uses defines precipitous groove as hard mask with anisotropy (anisotropy) etching method (dry etching) on the semiconductor-based end; After forming first shallow trench; Also will be in said shallow trench sidewall and bottom grow liners oxide layer; The purpose of grow liners oxide layer is for fear of corner effect (CornerEffect), if the corner of shallow trench is too sharp, in follow-up manufacture process; When for example utilizing ion to inject the formation source electrode with drain electrode; This one edge corner will stored charge, causes abnormal threshold current (Subthreshold Current) in the transistor channels and causes neck knot effect (Kink Effect), makes that transistor can't normal operation; Step 12: the dielectric of on the said semiconductor-based end and in said first shallow trench, growing, said dielectric is a silica, generally is to utilize chemical gaseous phase deposition (CVD) in said shallow trench, to insert dielectric; Grown and carried out annealing in process behind the dielectric; Annealing temperature is between 1000 ℃ to 1200 ℃, and annealing reaches two purposes herein; The one, form dry etching method that the shallow trench process uses to damage that backing material caused in order to eliminate; The 2nd, in order to make the dielectric densification, testing result has afterwards also given proof, with doing detailed argumentation in the back; Step 13: grind on the surface to said dielectric, makes the said first shallow trench flattening surface, and remove the suprabasil said dielectric of said semiconductor; Can on the said semiconductor-based bottom material of said dielectric both sides, precipitate sacrificial oxide layer afterwards, silicon dioxide for example, this is in follow-up ion implantation process, substrate surface to be battered down; Protected substrate surface; After ion injected, the sacrificial oxide layer that is battered down can be removed through the method for wet etching; Step 14: in said first shallow trench, form second shallow trench; In the subsequent technique; Be to be the substrate fabrication mos capacitance with said second shallow trench; In other words, remove the dielectric in mos capacitance zone at the semiconductor-based end exactly, first shallow trench that is about to the suprabasil mos capacitance of said semiconductor zone becomes second shallow trench; Step 15: in said second shallow trench sidewall and bottom grow liners oxide layer, the purpose of grow liners oxide layer is for fear of corner effect; Step 16: growing polycrystalline silicon layer on said second cushion oxide layer, because mos capacitance is the mos capacitance that contains fleet plough groove isolation structure, so the surface area of mos capacitance obtained increase, thereby makes the storage capacity of mos capacitance be greatly enhanced.
Fig. 3 is the fleet plough groove isolation structure sketch map that the present invention is used for mos capacitance; On scheming, can see; Inserted dielectric 21 in first shallow trench in the substrate 22, the grow liners oxide layer 25 also in said shallow trench sidewall and bottom, the purpose of grow liners oxide layer 25 is for fear of corner effect; Said dielectric 21 is a silica; Generally be to utilize chemical gaseous phase deposition (CVD) in said shallow trench, to insert dielectric, this is the raceway groove insulation usefulness for other circuit, and other circuit regions and mos capacitance zone are formed at first shallow trench simultaneously; Afterwards the dielectric in first shallow trench in mos capacitance zone is all removed, formed second shallow trench.Second shallow trench bottom and sidewall are grown successively has cushion oxide layer 24 and polysilicon layer 23, forms shallow trench in the mos capacitance zone, has increased the surface area of mos capacitance, has therefore improved the storage capacity of mos capacitance.
Though the present invention discloses as above with preferred embodiment, so it is not in order to limit the present invention.Have common knowledge the knowledgeable in the technical field under the present invention, do not breaking away from the spirit and scope of the present invention, when doing various changes and retouching.Therefore, protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (6)
1. be used for the manufacture method of the fleet plough groove isolation structure of mos capacitance, comprise:
S1: in the semiconductor-based end, form first shallow trench;
S2: the dielectric of on the said semiconductor-based end and in said first shallow trench, growing;
S3: grind on the surface to said dielectric, makes the said first shallow trench flattening surface, and remove the suprabasil said dielectric of said semiconductor;
S4: in said first shallow trench, forming second shallow trench, is the substrate fabrication mos capacitance with second groove;
S5: in said second shallow trench sidewall and bottom grow liners oxide layer;
S6: growing polycrystalline silicon layer on said second cushion oxide layer.
2. according to the manufacture method of the said fleet plough groove isolation structure of claim 1, it is characterized in that adopting among the said step S1 dry etching method on the said semiconductor-based end, to form first shallow trench.
3. according to the manufacture method of the said fleet plough groove isolation structure of claim 1, it is characterized in that adopting among the said step S4 dry etching method in said first shallow trench, to form second shallow trench.
4. according to the manufacture method of the said fleet plough groove isolation structure of claim 1, it is characterized in that said dielectric is a silica.
5. according to the manufacture method of the said fleet plough groove isolation structure of claim 1, it is characterized in that using the chemical gaseous phase deposition method said cushion oxide layer of growing.
6. according to the manufacture method of the said fleet plough groove isolation structure of claim 1, the material that it is characterized in that said cushion oxide layer is silica or silicon dioxide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100553738A CN101752227B (en) | 2009-07-24 | 2009-07-24 | Manufacturing method of shallow groove isolation structure for MOS capacitance |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100553738A CN101752227B (en) | 2009-07-24 | 2009-07-24 | Manufacturing method of shallow groove isolation structure for MOS capacitance |
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| CN101752227A CN101752227A (en) | 2010-06-23 |
| CN101752227B true CN101752227B (en) | 2012-05-09 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6037208A (en) * | 1999-04-20 | 2000-03-14 | Mosel Vitelic Inc. | Method for forming a deep trench capacitor of a DRAM cell |
| CN101057323A (en) * | 2004-11-17 | 2007-10-17 | 国际商业机器公司 | Trench capacitor with hybrid surface orientation substrate |
-
2009
- 2009-07-24 CN CN2009100553738A patent/CN101752227B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6037208A (en) * | 1999-04-20 | 2000-03-14 | Mosel Vitelic Inc. | Method for forming a deep trench capacitor of a DRAM cell |
| CN101057323A (en) * | 2004-11-17 | 2007-10-17 | 国际商业机器公司 | Trench capacitor with hybrid surface orientation substrate |
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| Publication number | Publication date |
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| CN101752227A (en) | 2010-06-23 |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140514 |
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Effective date of registration: 20140514 Address after: 201203 Shanghai Zhangjiang hi tech park Zuchongzhi Road No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201203 Shanghai Guo Shou Jing Road, Zhangjiang hi tech Park No. 818 Patentee before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |