CN101752227A - Manufacturing method of shallow groove isolation structure for MOS capacitance - Google Patents
Manufacturing method of shallow groove isolation structure for MOS capacitance Download PDFInfo
- Publication number
- CN101752227A CN101752227A CN200910055373A CN200910055373A CN101752227A CN 101752227 A CN101752227 A CN 101752227A CN 200910055373 A CN200910055373 A CN 200910055373A CN 200910055373 A CN200910055373 A CN 200910055373A CN 101752227 A CN101752227 A CN 101752227A
- Authority
- CN
- China
- Prior art keywords
- shallow trench
- isolation structure
- groove isolation
- mos capacitance
- fleet plough
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Element Separation (AREA)
Abstract
The invention provides a manufacturing method of a shallow groove isolation structure for MOS capacitance, which comprises: forming a first shallow groove in a semiconductor substrate; growing insulation medium on the semiconductor substrate and in the first shallow groove; grinding the surface of the insulation medium to make the surface of the first shallow groove planar, and removing the insulation medium on the semiconductor substrate; forming a second shallow groove in the first shallow groove, wherein the second shallow groove is positioned on the MOS capacitance area of the semiconductor substrate; growing pad oxide layers on the side wall and the bottom of the second shallow groove; and growing polysilicon layers on the pad oxide layers. The shallow groove provided by the invention is used as the substrate of the MOS capacitance, effectively increasing the surface area of the MOS capacitance, thus greatly improving the storage capacity of the MOS capacitance.
Description
Technical field
The invention belongs to a kind of semiconductor technology, relate in particular to a kind of manufacture method that is used for the fleet plough groove isolation structure of mos capacitance.
Background technology
In integrated circuit flourish today, element downsizing and the integrated trend that is inevitable also are the important topics of all circles' develop actively.When component size is dwindled gradually, integrated level (Integration) improves gradually, and interelement isolation structure also must dwindle, so element separation technical difficulty degree also increases gradually.Element separation helps the application region oxidizing process, and (Local Oxidation, the field oxide that LOCOS) forms (Field Oxide) because field oxide is subject to beak (Birds Beak) feature of its profile, dwindles its size and have any problem in fact.In view of this, existing other element separation methods continue to be developed, wherein with shallow trench isolation from (Shallow Trench Isolation STI) is widely used most, especially is applied in the ic manufacturing process of time half micron (Sub-half Micron).
Shallow trench isolation from manufacturing, the general silicon nitride that uses is as hard mask, on the semiconductor-based end, define precipitous groove with anisotropy (anisotropy) etching method (dry etching), again groove is filled up oxide afterwards, form oxide plug, with as the element fleet plough groove isolation structure, for example in the cmos device, the isolation between nmos pass transistor and the PMOS transistor all adopts shallow trench isolation to form from (STI) technology to the element below 0.13 micron.
Please refer to Fig. 1, Fig. 1 is the flow chart that the prior art fleet plough groove isolation structure is made, and in the manufacturing process of fleet plough groove isolation structure, prior art comprises the steps: step 111: form described shallow trench on semiconductor-based bottom material; Step 112: carry out the annealing in process first time; Step 113: in described shallow trench sidewall and bottom grow liners oxide layer; Step 114: in described shallow trench, insert dielectric; Step 115: carry out the annealing in process second time; Step 116: described dielectric surface ground make the shallow trench flattening surface; Step 117: on the described semiconductor-based bottom material of described dielectric both sides, precipitate sacrificial oxide layer, on this shallow ditch groove structure, make mos capacitance afterwards.Because this shallow ditch groove structure is planar substrates, the surface area of the mos capacitance of Zhi Zuoing can't increase thereon, the stored charge of the mos capacitance of making indifferent.
Summary of the invention
In order to solve the above mentioned not strong problem of mos capacitance storage capacity of on common fleet plough groove isolation structure, making, the invention provides a kind of manufacture method that can effectively improve the fleet plough groove isolation structure of mos capacitance storage capacity.
In order to achieve the above object, the present invention proposes a kind of manufacture method that is used for the fleet plough groove isolation structure of mos capacitance, comprising: form first shallow trench in the semiconductor-based end; The dielectric of growing on the described semiconductor-based end and in described first shallow trench; Grind on surface to described dielectric, makes the described first shallow trench flattening surface, and remove the suprabasil described dielectric of described semiconductor; In described first shallow trench, form second shallow trench; In described second shallow trench sidewall and bottom grow liners oxide layer; Growing polycrystalline silicon layer on described second cushion oxide layer.
Optionally, adopt the dry etching method on the described semiconductor-based end, to form first shallow trench among the described step S1.
Optionally, adopt the dry etching method in described first shallow trench, to form second shallow trench among the described step S4.
Optionally, described dielectric is a silica.
Optionally, use the chemical meteorological precipitation method described cushion oxide layer of growing.
Optionally, the material of described cushion oxide layer is silica or silicon dioxide.
Optionally, the depth bounds of described shallow trench is 0.1 micron to 1 micron.
Optionally, the depth bounds of described deep trench is 5 microns to 15 microns.
The beneficial effect of manufacture method that the present invention is used for the fleet plough groove isolation structure of mos capacitance is: the present invention forms shallow trench in the mos capacitance zone, has increased the surface area of mos capacitance, thereby has made the storage capacity of mos capacitance be greatly enhanced.
Description of drawings
Fig. 1 is the flow chart that the prior art fleet plough groove isolation structure is made;
Fig. 2 is the flow chart of embodiment of the manufacture method of the present invention's fleet plough groove isolation structure of being used for mos capacitance;
Fig. 3 is the fleet plough groove isolation structure schematic diagram that the present invention is used for mos capacitance.
Embodiment
Below in conjunction with the drawings and specific embodiments the manufacture method that the present invention is used for the fleet plough groove isolation structure of mos capacitance is described in further detail.
At first please refer to Fig. 2, Fig. 2 is the flow chart of first embodiment of the invention, on scheming, can see, first embodiment comprises the steps: step 11: form first shallow trench in the semiconductor-based end, described semiconductor-based bottom material is a silicon, and the general shape of described shallow trench can be with reference to figure 3, form shallow trench isolation from, the general silicon nitride that uses defines precipitous groove as hard mask with anisotropy (anisotropy) etching method (dry etching) on the semiconductor-based end; After forming first shallow trench, also will be in described shallow trench sidewall and bottom grow liners oxide layer, the purpose of grow liners oxide layer is for fear of corner effect (CornerEffect), if the corner of shallow trench is point too, in follow-up manufacture process, when for example utilizing ion to inject the formation source electrode with drain electrode, this corner, edge will stored charge, cause abnormal threshold current (Subthreshold Current) in the transistor channels and cause neck knot effect (Kink Effect), make that transistor can't normal operation; Step 12: the dielectric of on the described semiconductor-based end and in described first shallow trench, growing, described dielectric is a silica, generally be to utilize chemical gaseous phase deposition (CVD) in described shallow trench, to insert dielectric, grown and carried out annealing in process behind the dielectric, annealing temperature is between 1000 ℃ to 1200 ℃, annealing herein, reach two purposes, the one, form dry etching method that the shallow trench process uses to damage that backing material caused in order to eliminate, the 2nd, in order to make the dielectric densification, testing result has afterwards also given proof, will do detailed argumentation in the back; Step 13: grind on the surface to described dielectric, make the described first shallow trench flattening surface, and remove the suprabasil described dielectric of described semiconductor, can on the described semiconductor-based bottom material of described dielectric both sides, precipitate sacrificial oxide layer afterwards, silicon dioxide for example, this is in follow-up ion implantation process substrate surface to be battered down, protected substrate surface, after ion injected, the sacrificial oxide layer that is battered down can be removed by the method for wet etching; Step 14: in described first shallow trench, form second shallow trench, in the subsequent technique, be to be the substrate fabrication mos capacitance with described second shallow trench, in other words, remove the dielectric in mos capacitance zone at the semiconductor-based end exactly, first shallow trench that is about to the suprabasil mos capacitance of described semiconductor zone becomes second shallow trench; Step 15: in described second shallow trench sidewall and bottom grow liners oxide layer, the purpose of grow liners oxide layer is for fear of corner effect; Step 16: growing polycrystalline silicon layer on described second cushion oxide layer, because mos capacitance is the mos capacitance that contains fleet plough groove isolation structure, so the surface area of mos capacitance obtained increase, thereby makes the storage capacity of mos capacitance be greatly enhanced.
Fig. 3 is the fleet plough groove isolation structure schematic diagram that the present invention is used for mos capacitance, on scheming, can see, inserted dielectric 21 in first shallow trench in the substrate 22, the grow liners oxide layer 25 also in described shallow trench sidewall and bottom, the purpose of grow liners oxide layer 25 is for fear of corner effect, described dielectric 21 is a silica, generally be to utilize chemical gaseous phase deposition (CVD) in described shallow trench, to insert dielectric, this is to use for the raceway groove insulation of other circuit, other circuit regions and mos capacitance zone are formed at first shallow trench simultaneously, afterwards the dielectric in first shallow trench in mos capacitance zone is all removed, formed second shallow trench.Second shallow trench bottom and sidewall are grown successively cushion oxide layer 24 and polysilicon layer 23 are arranged, and form shallow trench in the mos capacitance zone, have increased the surface area of mos capacitance, have therefore improved the storage capacity of mos capacitance.
Though the present invention discloses as above with preferred embodiment, so it is not in order to limit the present invention.The persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (8)
1. be used for the manufacture method of the fleet plough groove isolation structure of mos capacitance, comprise:
S1: in the semiconductor-based end, form first shallow trench;
S2: the dielectric of on the described semiconductor-based end and in described first shallow trench, growing;
S3: grind on the surface to described dielectric, makes the described first shallow trench flattening surface, and remove the suprabasil described dielectric of described semiconductor;
S4: in described first shallow trench, form second shallow trench;
S5: in described second shallow trench sidewall and bottom grow liners oxide layer;
S6: growing polycrystalline silicon layer on described second cushion oxide layer.
2. according to the manufacture method of the described fleet plough groove isolation structure of claim 1, it is characterized in that adopting among the described step S1 dry etching method on the described semiconductor-based end, to form first shallow trench.
3. according to the manufacture method of the described fleet plough groove isolation structure of claim 1, it is characterized in that adopting among the described step S4 dry etching method in described first shallow trench, to form second shallow trench.
4. according to the manufacture method of the described fleet plough groove isolation structure of claim 1, it is characterized in that described dielectric is a silica.
5. according to the manufacture method of the described fleet plough groove isolation structure of claim 1, it is characterized in that using the chemical meteorological precipitation method described cushion oxide layer of growing.
6. according to the manufacture method of the described fleet plough groove isolation structure of claim 1, the material that it is characterized in that described cushion oxide layer is silica or silicon dioxide.
7. according to the manufacture method of the described fleet plough groove isolation structure of claim 1, the depth bounds that it is characterized in that described shallow trench is 0.1 micron to 1 micron.
8. according to the manufacture method of the described fleet plough groove isolation structure of claim 1, the depth bounds that it is characterized in that described deep trench is 5 microns to 15 microns.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100553738A CN101752227B (en) | 2009-07-24 | 2009-07-24 | Manufacturing method of shallow groove isolation structure for MOS capacitance |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100553738A CN101752227B (en) | 2009-07-24 | 2009-07-24 | Manufacturing method of shallow groove isolation structure for MOS capacitance |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101752227A true CN101752227A (en) | 2010-06-23 |
| CN101752227B CN101752227B (en) | 2012-05-09 |
Family
ID=42478981
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009100553738A Active CN101752227B (en) | 2009-07-24 | 2009-07-24 | Manufacturing method of shallow groove isolation structure for MOS capacitance |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101752227B (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW415010B (en) * | 1999-04-20 | 2000-12-11 | Mosel Vitelic Inc | Method for fabricating trench capacitor |
| US7229877B2 (en) * | 2004-11-17 | 2007-06-12 | International Business Machines Corporation | Trench capacitor with hybrid surface orientation substrate |
-
2009
- 2009-07-24 CN CN2009100553738A patent/CN101752227B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN101752227B (en) | 2012-05-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100376238B1 (en) | Semiconductor device and method of manufacturing the same | |
| EP1213757B1 (en) | Integrated circuits having adjacent p-type doped regions having shallow trench isolation structures without liner layers therebetween and methods of forming same | |
| TW200428579A (en) | Manufacturing method of semiconductor device | |
| US6153478A (en) | STI process for eliminating kink effect | |
| US8338893B2 (en) | Method and resulting structure DRAM cell with selected inverse narrow width effect | |
| US7361571B2 (en) | Method for fabricating a trench isolation with spacers | |
| JP4508129B2 (en) | Method for forming active region and isolation region in semiconductor substrate and method for forming integrated circuit | |
| US20110057259A1 (en) | Method for forming a thick bottom oxide (tbo) in a trench mosfet | |
| US20020127818A1 (en) | Recess-free trench isolation structure and method of forming the same | |
| CN106257633A (en) | There is the semiconductor structure that junction leakage reduces | |
| CN101465323B (en) | Method for manufacturing a semiconductor device capable of preventing the decrease of the width of an active region | |
| CN105161450A (en) | Double-shallow-trench isolation forming method | |
| TWI240363B (en) | Substrate isolation in integrated circuits | |
| US6750097B2 (en) | Method of fabricating a patterened SOI embedded DRAM/eDRAM having a vertical device cell and device formed thereby | |
| CN101635271B (en) | Fabricating method of shallow trench isolation structure | |
| US7659599B2 (en) | Patterned silicon-on-insulator layers and methods for forming the same | |
| CN103000534A (en) | Manufacture method of groove-type P-type metal oxide semiconductor power transistor | |
| JP2006313901A (en) | Semiconductor device and fabrication method | |
| KR100587186B1 (en) | Low power flash memory cell and method | |
| US6287939B1 (en) | Method for fabricating a shallow trench isolation which is not susceptible to buried contact trench formation | |
| CN101752227B (en) | Manufacturing method of shallow groove isolation structure for MOS capacitance | |
| JP2005353892A (en) | Semiconductor substrate, semiconductor device and its manufacturing method | |
| US20030181014A1 (en) | Method of manufacturing semiconductor device with STI | |
| CN101866872A (en) | Manufacturing method of shallow trench isolation structure | |
| KR20010055525A (en) | Method for shallow trench isolation |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140514 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20140514 Address after: 201203 Shanghai Zhangjiang hi tech park Zuchongzhi Road No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201203 Shanghai Guo Shou Jing Road, Zhangjiang hi tech Park No. 818 Patentee before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |