KR20070077283A - Liquid crystal display - Google Patents

Abstract

An LCD is provided to prevent flicker or blur from being generated on a screen by preventing a second kickback voltage from being generated in pixels. A plurality of pixels are arranged in a matrix form on a substrate and include switching devices(Q). A plurality of pairs of first and second gate lines are connected to the switching devices and are separated from each other. The first and second gate lines transmit a gate signal including a gate-on voltage for turning on the switching devices. A plurality of data lines are connected to the switching devices and transfer a data voltage. A gate-on voltage applied to the first gate lines does not overlap a gate-on voltage applied to the second gate lines. Each date line is disposed per every two adjacent pixel columns.

Description

Liquid crystal display {LIQUID CRYSTAL DISPLAY}

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a diagram illustrating a spatial arrangement of pixels and signal lines of a liquid crystal display according to an exemplary embodiment of the present invention.

4 is a block diagram of a gate driver according to an exemplary embodiment of the present invention.

FIG. 5 is an example of a circuit diagram of the j-th stage of the shift register for gate driver shown in FIG. 4; FIG.

6 is a signal waveform diagram of a gate driver shown in FIG. 4;

7 and 8 are waveform diagrams showing the gate signal output of the gate driver according to an embodiment of the present invention.

The present invention relates to a liquid crystal display device.

The liquid crystal display is one of the most widely used flat panel display devices, and includes two display panels on which electric field generating electrodes, such as a pixel electrode and a common electrode, are formed, and a liquid crystal layer interposed therebetween. The liquid crystal display generates an electric field in the liquid crystal layer by applying a voltage to the field generating electrode, thereby determining an orientation of liquid crystal molecules in the liquid crystal layer and controlling the polarization of incident light to display an image.

The liquid crystal display also includes a switching element connected to each pixel electrode and a plurality of signal lines such as a gate line and a data line for controlling the switching element and applying a voltage to the pixel electrode. The gate line generates a gate signal generated by the gate driving circuit, the data line transfers the data voltage generated by the data driving circuit, and the switching element transfers the data voltage to the pixel electrode according to the gate signal.

The gate driving circuit and the data driving circuit are directly attached to the display panel in the form of a plurality of integrated circuit chips or attached to the display panel by being mounted on a flexible circuit film or the like, and such integrated circuit chips have a high ratio to the manufacturing cost of the liquid crystal display device. do. In particular, since the data driving integrated circuit chip is very expensive compared to the gate driving circuit chip, the number of high resolution, large area liquid crystal display devices needs to be reduced. In the case of the gate driving circuit, the cost can be reduced by integrating the gate line, the data line, and the switching element together with the display panel. However, the data driving circuit is more complicated in structure and difficult to integrate into the display panel. .

On the other hand, the gate driver is applied to the left and right sides of the display panel to apply the gate signal. After the gate signal is applied to apply the gate signal at a time for one frame, the next gate signal overlaps with the previous gate signal after a predetermined time. .

However, the parasitic capacitance exists in the pixel due to the overlapping of the signal lines, and the kickback voltage is generated due to the parasitic capacitance at the instant when the gate-on voltage becomes the gate-off voltage after the data voltage is applied. This causes the data voltage to decrease slightly, followed by the kickback voltage once again as the next gate-on voltage changes to the gate-off voltage. As a result, there is a difference between the positive and negative pixel voltages, which causes flicker, and may cause stains on the screen.

Accordingly, an object of the present invention is to provide a driving device of a display device that can remove flicker or screen unevenness.

According to an aspect of the present invention, a liquid crystal display device includes a substrate, a plurality of pixels arranged in a matrix form on the substrate and including a switching element, and a gate on voltage connected to the switching element and turning on the switching element. A plurality of pairs of first and second gate lines which are separated from each other, transferring a gate signal, including a plurality of data lines connected to the switching element and transferring data voltages, and applied to the first gate lines; The gate-on voltage is not overlapped with the gate-on voltage applied to the second gate line.

The gate-on voltage applied to the first gate line may be maintained for 1/2 H, and the gate-on voltage applied to the second gate line may be maintained for 1/2 H.

One data line may be disposed in each of two adjacent pixel columns.

The display device may further include a gate driver connected to the first and second gate lines and generating the gate signal based on a plurality of clock signals.

The gate driver may be integrated on the substrate.

The gate driver may include a first gate driver connected to an odd-numbered gate line among the gate lines, and a second gate driver connected to an even-numbered gate line among the gate lines.

The first and second gate drivers may be opposite to each other with the pixel therebetween.

The duty ratio of the plurality of clock signals may be 25%.

The plurality of clock signals may include first to fourth clock signals, and a phase difference between adjacent clock signals among the first to fourth clock signals may be 180 °.

The first and third clock signals may be input to the first gate driver, and the second and fourth clock signals may be input to the second gate driver.

First and second output start signals may be input to the first and second gate drivers, respectively.

Two pixels arranged adjacent to each other in a row direction between two adjacent data lines among the data lines may be connected to the same data line.

Two pixels adjacent in the column direction may be connected to different data lines.

When two pixels arranged adjacent to each other in the row direction among the data lines among the data lines are referred to as unit pixel pairs, the positions of the switching elements of the two unit pixel pairs adjacent in the row direction may be the same.

When two pixels arranged in the row direction between two adjacent data lines among the data lines are referred to as unit pixel pairs, the two pixels of the unit pixel pair may be connected to different gate lines.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

First, a liquid crystal display according to an exemplary embodiment of the present invention will be described with reference to FIGS. 1, 2, and 3.

1 is a block diagram of a liquid crystal display according to an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an embodiment of the present invention, and FIG. 3 is an embodiment of the present invention. It is a figure explaining the spatial arrangement of the pixel and signal line of the liquid crystal display device which concerns on an example.

1 and 2, a liquid crystal display according to an exemplary embodiment of the present invention may include a liquid crystal panel assembly 300, a pair of gate drivers 400R and 400L and a data driver connected thereto. 500, a gray voltage generator 800 connected to the data driver 500, and a signal controller 600 for controlling the gray voltage generator 800.

The liquid crystal panel assembly 300 includes a plurality of signal lines G ₁ -G _{2n and} D ₁ -D _m and a plurality of pixels PX connected to the plurality of signal lines G ₁ -G _{2n and} D ₁ -D _m , which are arranged in a substantially matrix form. Include. On the other hand, in the structure shown in FIG. 2, the liquid crystal panel assembly 300 includes lower and upper panels 100 and 200 facing each other and a liquid crystal layer 3 interposed therebetween.

The signal line includes a plurality of gate lines G ₁ -G _2n transmitting a gate signal (also referred to as a “scan signal”) and a plurality of data lines D ₁ -D _m transmitting a data signal. The gate lines G ₁ -G _2n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

Each pixel PX includes a switching element Q connected to a signal line, a liquid crystal capacitor Clc, and a storage capacitor Cst connected thereto. Holding capacitor Cst can be omitted as needed.

The switching element Q is a three-terminal element of a thin film transistor or the like provided in the lower panel 100, the control terminal of which is connected to the gate line G _i , and the input terminal of which is connected to the data line D _j . The output terminal is connected to the liquid crystal capacitor Clc and the storage capacitor Cst.

The liquid crystal capacitor Clc has two terminals, the pixel electrode 191 of the lower panel 100 and the common electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 191 and 270 is a dielectric material. Function as. The pixel electrode 191 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives the common voltage Vcom. Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, at least one of the two electrodes 191 and 270 may be formed in a linear or bar shape.

The storage capacitor Cst, which serves as an auxiliary part of the liquid crystal capacitor Clc, is formed by overlapping a separate signal line (not shown) and the pixel electrode 191 provided on the lower panel 100 with an insulator interposed therebetween. A predetermined voltage such as the common voltage Vcom is applied to the separate signal line. However, the storage capacitor Cst may be formed such that the pixel electrode 191 overlaps the front gate line directly above the insulator.

As shown in FIG. 3, a pair of gate lines G _i and G _{i + 1} , G _{i + 2} and G _{i + 3} ,... Are disposed above and below a row of pixel electrodes 191. have. In addition, the data lines D ₁ -D _m are disposed one by one between the pixel electrodes 191 of two columns. That is, one data line is arranged between the pair of pixel columns. Hereinafter, two pixels disposed between two adjacent data lines are called unit pixel pairs.

Now, the connection between the gate lines G ₁ -G _2n and the data lines D ₁ -D _m and the pixel electrode 191 will be described in more detail.

The plurality of pairs of gate lines G ₁ -G _2n connected to the top and bottom of the pixel electrode 191 are connected to the corresponding pixel electrode 191 through a switching element Q disposed above or below each pixel electrode 191. Is connected to.

That is, in the odd-numbered pixel row, the switching element Q located on the left side of one data line D ₁ -D _{m is} connected to the gate lines G _i , G _{i + 4} located above, The switching element Q located on the right side of one data line D ₁ -D _{m is} connected to the gate lines G _{i + 1} and G _{i + 5} located below. On the other hand, the connection between the upper gate line (G _{i + 3} , G _{i + 6} ) and the lower gate line (G _{i + 4} , G _{i + 7} ) and the switching element Q in the even-numbered pixel row is odd-numbered pixel row. The opposite is true. That is, the switching element Q positioned on the right side of one data line D ₁ -D _{m is} connected to the gate lines G _{i + 2} and G _{i + 6} located above and one data. The switching element Q located on the left side of the line D ₁ -D _{m is} connected to the gate lines G _{i + 3} and G _{i + 7} located below.

In the odd-numbered pixel rows, the pixel electrode 191 positioned to the left of the data lines D ₁ -D _m is connected to the immediately adjacent data line through the switching element Q, and the data lines D ₁ -D. the pixel electrode 191 on the right about the D _m) is via the switching element (Q) connected to the car adjacent to the data lines (D ₁ -D _m). In the even-numbered pixel row, the pixel electrode 191 positioned to the left of the data lines D ₁ -D _m is connected to the immediately preceding data line through the switching element Q, and the data lines D ₁ -D. The pixel electrode 191 positioned on the right side of D _m ) is connected to the immediately adjacent data line through the switching element Q.

In addition, in the arrangement shown in Fig. 3, the position of the switching element Q changes every pixel row. That is, the switching element Q is formed at the upper right side of the pixel PX positioned to the left of the data lines D ₁ -D _m among the pixel pairs positioned in the odd pixel rows, and the data lines D ₁ -D _m. The switching element Q is formed at the lower right side of the pixel positioned on the right side of the panel.

On the other hand, the formation position of the switching element Q of the pixel located in the even-numbered pixel row is opposite to the formation position of the adjacent pixel row. That is, the right side of the pair of the even-numbered pixels located in the second line the data lines (D ₁ -D _m) pixel is formed on the switching element (Q) at the bottom left, to the left of the data lines (D ₁ -D _m) The switching element Q is formed in the upper left portion of the pixel.

The reason why the position of the switching element Q is changed every pixel row is to keep the connection length of the switching element Q formed in each pixel and the data lines D ₁ -D _m as short as possible.

When the connection between the pixel electrode 191 and the data lines D ₁ -D _m shown in FIG. 3 is summarized, in each pixel row, the switching elements Q of the unit pixel pairs are connected to the same data line. That is, in the odd-numbered pixel rows, the switching elements Q of the unit pixel pairs are connected to the data lines located on the right side, and in the even-numbered pixel rows, the switching elements Q of the unit pixel pairs are connected to the data lines located on the left side thereof. have.

The arrangement shown in FIG. 3 is just one example, and the connection of the pixel electrodes 191 and the data lines D ₁ -D _m and the gate lines G ₁ -G _{2n in the} odd and even rows are mutually different. It can be changed and can also have other connections.

On the other hand, in order to implement color display, each pixel PX uniquely displays one of the primary colors (spatial division) or each pixel PX alternately displays the primary colors over time (time division). The desired color is recognized by the spatial and temporal sum of these primary colors. Examples of the primary colors include three primary colors such as red, green, and blue. FIG. 2 illustrates that each pixel PX includes a color filter 230 representing one of the primary colors in an area of the upper panel 200 corresponding to the pixel electrode 191 as an example of spatial division. Unlike FIG. 2, the color filter 230 may be formed above or below the pixel electrode 191 of the lower panel 100.

At least one polarizer (not shown) for polarizing light is attached to an outer surface of the liquid crystal panel assembly 300.

Referring back to FIG. 1, the gray voltage generator 800 generates two sets of gray voltage sets (or reference gray voltage sets) related to the transmittance of the pixel PX. One of the two sets has a positive value for the common voltage Vcom and the other set has a negative value.

The gate drivers 400L and 400R include first and second gate drivers 400L and 400R which are disposed on the right and left sides of the liquid crystal panel 300, respectively. The gate drivers 400L and 400R are connected to the gate lines G ₁ -G _2n of the liquid crystal panel assembly 300 to receive a gate signal formed of a combination of the gate on voltage Von and the gate off voltage Voff. G ₁ -G _2n ).

Gate lines G _i , G _{i + 2} , G _{i + 4} , and G _{i + 6} positioned upward in each pixel row are connected to the first gate driver 400L, and are positioned below each pixel row. The gate lines G _{i + 1} , G _{i + 3} , G _{i + 5} , and G _{i + 7} are connected to the second gate driver 400R.

The gate drivers 400L and 400R include a plurality of stages substantially arranged in a row as a shift register, and include a signal line G ₁ -G _2n , D ₁ -D _m and a thin film transistor switching element Q. And are formed and integrated in the same process. Gate drivers 400L and 400R may also be mounted directly onto assembly 300 in the form of integrated circuit chips, and flexible printed circuit films (not shown). It may be mounted on the liquid crystal panel assembly 300 in the form of a tape carrier package (TCP) or mounted on a separate printed circuit board (not shown).

The data driver 500 is connected to the data lines D ₁ -D _m of the liquid crystal panel assembly 300 and selects a gray voltage from the gray voltage generator 800 and uses the data line D ₁ as a data signal. -D _m ). However, when the gray voltage generator 800 provides only a predetermined number of reference gray voltages instead of providing all of the voltages for all grays, the data driver 500 divides the reference gray voltages to divide the gray voltages for all grays. Generate and select the data signal from it.

The signal controller 600 controls the gate driver 400, the data driver 500, and the like.

Each of the driving devices 500, 600, and 800 may be mounted directly on the liquid crystal panel assembly 300 in the form of at least one integrated circuit chip, or mounted on a flexible printed circuit film (not shown). And attached to the liquid crystal panel assembly 300 in the form of a tape carrier package (TCP) or mounted on a separate printed circuit board (not shown). Alternatively, these driving devices 500, 600, and 800 may be integrated in the liquid crystal panel assembly 300 together with the signal lines G ₁ -G _2n , D ₁ -D _m and the thin film transistor switching element Q. . In addition, the driving apparatuses 500, 600, and 800 may be integrated into a single chip, in which case at least one of them or at least one circuit element constituting them may be outside the single chip.

Next, the operation of the liquid crystal display will be described in detail.

The signal controller 600 receives input image signals R, G, and B and an input control signal for controlling the display thereof from an external graphic controller (not shown). Examples of the input control signal include a vertical sync signal Vsync, a horizontal sync signal Hsync, a main clock MCLK, and a data enable signal DE.

The signal controller 600 properly processes the input image signals R, G, and B according to operating conditions of the liquid crystal panel assembly 300 based on the input image signals R, G, and B and the input control signal, and controls the gate. After generating the signal CONT1 and the data control signal CONT2, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signal DAT are transmitted to the data driver 500. Export to).

The gate control signal CONT1 includes a scan start signal STV indicating a scan start and at least one clock signal controlling an output period of the gate-on voltage Von. The gate control signal CONT1 may also further include an output enable signal OE that defines the duration of the gate-on voltage Von.

The data control signal CONT2 is a load for applying a data signal to the horizontal synchronization start signal STH and the data lines D ₁ -D _m indicating the start of image data transmission for the pixels PX in one row [bundling]. Signal LOAD and data clock signal HCLK. The data control signal CONT2 is also an inverted signal that inverts the voltage polarity of the data signal relative to the common voltage Vcom (hereinafter referred to as " polarity of the data signal " by reducing the " voltage polarity of the data signal for the common voltage ") RVS) may be further included.

According to the data control signal CONT2 from the signal controller 600, the data driver 500 receives the digital image signal DAT for the pixel PX in one row (bundling), and each digital image signal DAT. By converting the digital image signal DAT into an analog data signal by selecting a gray scale voltage corresponding to), it is applied to the corresponding data lines D ₁ -D _m .

The gate drivers 400L and 400R apply the gate-on voltage Von to the gate lines G ₁ -G _2n according to the gate control signal CONT1 from the signal controller 600, thereby applying the gate lines G ₁ -G. _2n ) turns on the switching element Q connected. Then, the data signal applied to the data lines D ₁ -D _m is applied to the pixel PX through the switching element Q turned on.

The difference between the voltage of the data signal applied to the pixel PX and the common voltage Vcom is shown as the charging voltage of the liquid crystal capacitor Clc, that is, the pixel voltage. The arrangement of the liquid crystal molecules varies depending on the magnitude of the pixel voltage, thereby changing the polarization of light passing through the liquid crystal layer 3. The change in polarization is represented by a change in transmittance of light by a polarizer attached to the display panel assembly 300.

This process is repeated in units of one horizontal period (also referred to as "1H" and equal to one period of the horizontal sync signal Hsync and the data enable signal DE), so that all the gate lines G ₁ -G _2n are repeated. ), The gate-on voltage Von is sequentially applied to the data signal to all the pixels PX, thereby displaying an image of one frame.

When one frame ends, the state of the inversion signal RVS applied to the data driver 500 is controlled so that the next frame starts and the polarity of the data signal applied to each pixel PX is opposite to the polarity of the previous frame. "Invert frame"). In this case, the polarities of the data signals flowing through one data line are changed (eg, row inversion and point inversion) according to the characteristics of the inversion signal RVS within one frame, or the polarities of data signals applied to one pixel row are also different from each other. Can be different (eg invert columns, invert points).

Next, a gate driver according to an exemplary embodiment of the present invention will be described with reference to FIGS. 4 to 6.

4 is a block diagram of a gate driver according to an embodiment of the present invention, FIG. 5 is a circuit diagram of a j-th stage of a shift register for a gate driver according to an embodiment of the present invention, and FIG. 6 is shown in FIG. Signal waveform diagram of the gate driver.

The first and second scan start signals LSTV and RSTV and the first to fourth clock signals LCLK1, RCLK1, LCLK2 and RCLK2 are input to the shift registers 400L and 400R shown in FIG. 4. Each of the shift registers 400L and 400R is arranged in a line and includes a plurality of stages 410L and 410R connected to the gate lines, respectively.

As shown in FIG. 6, the first scan start signal LSTV input to the left shift register 400L and the second scan start signal RSTV input to the right shift register 400R have a plurality of widths of 1H. It is a signal of one frame period including one pulse in one frame. The first to fourth clock signals LCLK1, RCLK1, LCLK2, and RCLK2 have a period of 2H and exhibit a high level for 1 / 2H, resulting in a duty ratio of 25%. The first clock signal LCLK1 and the second clock signal RCLK1 have a phase difference of 180 °, and the second clock signal RCLK1 and the third clock signal RCLK1 also have a phase difference of 180 ° and the third clock signal RCLK1 ) And the fourth clock signal RCLK2 also have a 180 ° phase difference.

The first clock signal LCLK1 is located in the high period of the first clock signal LCLK1 in a part of the high period of the first vertical synchronization start signal LSTV input to the first stage 410L of the left shift register 400L. Becomes low and becomes low at the same time, the high of the second clock signal RCLK1 is also high in a part of the high period of the second vertical synchronization start signal RSTV input to the first stage 410R of the right shift register 400R. Located in the interval, the second clock signal RCLK1 goes low and goes low.

Different clock signals LCLK1, RCLK1, LCLK2, and RCLK2 are input to two adjacent stages 410L and 410R in each of the shift registers 400L and 400R. For example, the first clock signal LCLK1 is input to the first stage of the left shift register 400L, the third clock signal LCLK2 is input to the second stage, and the first stage is input to the first stage of the right shift register 400R. The fourth clock signal RCLK2 is input to the second clock signal RCLK1 and the second stage.

Each clock signal LCLK1, RCLK1, LCLK2, RCLK2 is also a gate-on voltage (V _on ) when it is high, and gate-off voltage (V _off ) when it is low so as to drive the switching element (Q) of the pixel. desirable.

Each stage 410L, 410R includes a set terminal S, a gate voltage terminal GV, a pair of clock terminals CK1 and CK2, a reset terminal R, a frame reset terminal FR, and a gate output. It has a terminal OUT1 and a carry output terminal OUT2.

Carry output of the front stage ST (j-2), that is, the front carry output Cout (j-2), is reset to the set terminal S of each stage, for example, the j-th stage STj. The gate output of the rear stage ST (j + 2), that is, the rear gate output Gout (j + 2), is input to the terminal R, and the clock signals LCLK1 and LCLK2 are supplied to the clock terminals CK1 and CK2. Is input, and the gate-off voltage V _off is input to the gate voltage terminal GV. The gate output terminal OUT1 outputs the gate output Gout (j) and the carry output terminal OUT2 outputs the carry output Cout (j).

However, the scan start signals LSTV and RSTV are input to the first stage of each shift register 400L and 400R instead of the front carry output. Also, when the clock signal LCLK1 is input to the clock terminal CK1 of the j-th stage STj and the clock signal LCLK2 is input to the clock terminal CK2, the (j-2) th and (j + The clock signal LCLK2 is input to the clock terminal CK1 of the 2nd-th stage ST (j-2, ST (j + 2)), and the clock signal LCLK1 is input to the clock terminal CK2.

Referring to FIG. 5, each stage of the gate driver 400 according to an embodiment of the present invention, for example, the j-th stage, includes an input unit 420, a pull-up driver 430, a pull-down driver 440, and an output unit. (450). These include at least one NMOS transistor T1-T14, and the pull-up driver 430 and the output unit 450 further include capacitors C1-C3. However, PMOS transistors may be used instead of NMOS transistors. In addition, the capacitors C1-C3 may actually be parasitic capacitances between the gate and the drain / source formed during the process.

The input unit 420 includes three transistors T11, T10, and T5 connected in series to the set terminal S and the gate voltage terminal GV. Gates of the transistors T11 and T5 are connected to the clock terminal CK2, and gates of the transistor T10 are connected to the clock terminal CK1. The contact between the transistor T11 and the transistor T10 is connected to the contact J1, and the contact between the transistor T10 and the transistor T5 is connected to the contact J2.

The pull-up driving unit 430 includes a transistor T4 connected between the set terminal S and the contact J1, a transistor T12 connected between the clock terminal CK1 and the contact J3, and a clock terminal ( And transistor T7 connected between CK1 and contact J4. The gate and the drain of the transistor T4 are commonly connected to the set terminal S, the source is connected to the contact J1, and the gate and the drain of the transistor T12 are commonly connected to the clock terminal CK1. And the source is connected to contact J3. The gate of the transistor T7 is connected to the contact J3 and at the same time connected to the clock terminal CK1 through the capacitor C1, the drain is connected to the clock terminal CK1, the source is connected to the contact J4. , Capacitor C2 is connected between contact J3 and contact J4.

The pull-down driver 440 receives the gate-off voltage V _off through a source and outputs a plurality of transistors T6, T9, T13, T8, T3, and T2 through a drain to the contacts J1, J2, J3, and J4. ). The gate of the transistor T6 is connected to the frame reset terminal FR, the drain is connected to the contact J1, the gate of the transistor T9 is connected to the reset terminal R, and the drain is connected to the contact J1. The gates of the transistors T13 and T8 are commonly connected to the contact J2, and the drains are connected to the contacts J3 and J4, respectively. The gate of the transistor T3 is connected to the contact J4, the gate of the transistor T2 is connected to the reset terminal R, and the drains of the two transistors T3 and T2 are connected to the contact J2.

The output unit 450 includes a pair of transistors T1 and T14 having a drain and a source connected between the clock terminal CK1 and the output terminals OUT1 and OUT2 and a gate connected to the contact J1, respectively. And a capacitor C3 connected between the gate and the drain of T1, that is, between the contact J1 and the contact J2. The source of transistor T1 is also connected to contact J2.

The operation of such a stage will now be described.

For convenience of explanation, the voltage corresponding to the high level of the clock signals LCLK1, LCKL2, RCLK1, and RCLK2 is called a high voltage, and the magnitude of the voltage corresponding to the low level of the clock signals LCLK1, LCLK2, RCLK1, and RCLK2 is a gate. It is equal to the off voltage V _off and is called low voltage.

First, when the clock signal LCLK2 and the front carry output Cout (j-2) become high, the transistors T11 and T5 and the transistor T4 are turned on. Then, the two transistors T11 and T4 transfer a high voltage to the contact J1, and the transistor T5 transfers a low voltage to the contact J2. As a result, the transistors T1 and T14 are turned on so that the clock signal CLK1 is output to the output terminals OUT1 and OUT2. At this time, since the voltage of the contact J2 and the clock signal LCLK1 are both low voltages, the output voltage [ Gout (j) and Cout (j)] become low voltage. At the same time, the capacitor C3 charges a voltage having a magnitude corresponding to the difference between the high voltage and the low voltage.

At this time, since the clock signal LCLK1 and the rear gate output Gout (j + 2) are low and the contact J2 is also low, the transistors T10, T9, T12, T13, T8, and T2 connected to the gate are connected. ) Are all off.

Subsequently, when the clock signal LCLK2 becomes low, the transistors T11 and T5 are turned off. At the same time, when the clock signal LCLK1 becomes high, the output voltage of the transistor T1 and the voltage of the contact J2 become high. do. At this time, a high voltage is applied to the gate of the transistor T10, but since the potential of the source connected to the contact J2 is also the same high voltage, the potential difference between the gate sources becomes zero, so that the transistor T10 remains turned off. . Accordingly, the contact J1 is in a floating state, whereby the potential is further increased by the high voltage by the capacitor C3.

On the other hand, since the potentials of the clock signal LCLK1 and the contact J2 are high voltage, the transistors T12, T13, and T8 are turned on. In this state, the transistor T12 and the transistor T13 are connected in series between the high voltage and the low voltage, so that the potential of the contact J3 is divided by the resistance value of the resistance state at the turn-on of the two transistors T12 and T13. Voltage value. However, assuming that the resistance value of the resistance state at the turn-on of the two transistors T13 is set to be very large compared to the resistance value of the resistance state at the turn-on of the transistor T12, for example, about 10,000 times, the voltage of the contact J3 is a high voltage. Is almost the same as Accordingly, the transistor T7 is turned on and connected in series with the transistor T8, whereby the potential of the contact J4 is divided by the resistance value of the resistance state at the turn-on of the two transistors T7 and T8. Has a value. At this time, if the resistance values of the resistance states of the two transistors T7 and T8 are set to be almost the same, the potential of the contact J4 has an intermediate value between the high voltage and the low voltage, whereby the transistor T3 is turned off. Keep it. At this time, since the rear gate output Gout (j + 2) is still low, the transistors T9 and T2 also remain turned off. Therefore, the output terminals OUT1 and OUT2 are connected only to the clock signal CLK1 and cut off from the low voltage to emit a high voltage.

On the other hand, the capacitor C1 and the capacitor C2 charge voltages corresponding to the potential difference between both ends, respectively, and the voltage of the contact J3 is lower than the voltage of the contact J5.

Subsequently, when the rear gate output Gout (j + 1) and the clock signal CLK2 go high and the clock signal CLK1 goes low, the transistors T9 and T2 are turned on to low voltage to the contacts J1 and J2. To pass. At this time, the voltage of the contact J1 falls to the low voltage while the capacitor C3 discharges, but it takes some time to completely lower to the low voltage due to the discharge time of the capacitor C3. Therefore, the two transistors T1 and T14 remain turned on for a while even after the rear gate output Gout (j + 1) becomes high, so that the output terminals OUT1 and OUT2 are connected to the clock signal CLK1. To emit low voltage. Subsequently, when the capacitor C3 is completely discharged and the potential of the contact J1 reaches a low voltage, the transistor T14 is turned off and the output terminal OUT2 is cut off from the clock signal CLK1, so that the carry output Cout (j) is performed. Becomes floating and maintains low voltage. At the same time, the output terminal OUT1 is continuously connected to the low voltage through the transistor T2 even when the transistor T1 is turned off, thereby continuously outputting a low voltage.

On the other hand, since the transistors T12 and T13 are turned off, the contact J3 is in a floating state. In addition, the voltage of the contact J5 is lower than the voltage of the contact J4. The transistor T7 is turned off because the voltage of the contact J3 is kept lower than the voltage of the contact J5 by the capacitor C1. . At the same time, since the transistor T8 is also turned off, the voltage at the contact J4 is lowered by that amount, so that the transistor T3 also remains turned off. In addition, the transistor T10 maintains the turn-off state because the gate is connected to the low voltage of the clock signal CLK1 and the voltage of the contact J2 is low.

Next, when the clock signal CLK1 becomes high, the transistors T12 and T7 turn on, the voltage of the contact J4 rises, turns on the transistor T3, and transfers a low voltage to the contact J2. ) Continues to emit low voltage. That is, even if the rear gate output Gout (j + 1) has a low output, the voltage of the contact J2 can be made low.

Meanwhile, since the gate of the transistor T10 is connected to the high voltage of the clock signal CLK1 and the voltage of the contact J2 is a low voltage, the gate of the transistor T10 is turned on to transfer the low voltage of the contact J2 to the contact J1. On the other hand, the clock terminal CK1 is connected to the drains of the two transistors T1 and T14, and the clock signal CLK1 is continuously applied. In particular, the transistor T1 is made relatively larger than the rest of the transistors, so that the parasitic capacitance between gate drains is large, so that the voltage change of the drain may affect the gate voltage. Therefore, when the clock signal CLK1 becomes high, the gate voltage may increase due to the parasitic capacitance between the gate and drain gates, thereby turning on the transistor T1. Therefore, the low voltage of the contact J2 is transferred to the contact J1 to maintain the gate voltage of the transistor T1 at a low voltage, thereby preventing the transistor T1 from turning on.

Thereafter, the voltage at the contact J1 maintains a low voltage until the front carry output Cout (j-2) becomes high, and the voltage at the contact J2 has the clock signal CLK1 high and the clock signal CLK2. Is low, the low voltage is maintained through the transistor T3, and vice versa, the low voltage is maintained through the transistor T5.

On the other hand, the transistor T6 receives the initialization signal INT generated in the last dummy stage (not shown) and transfers the gate-off voltage V _off to the contact J1 to transfer the voltage of the contact J1 once more. Set to low voltage.

In this manner, the stage 410 is based on the front carry signal Cout (j-2) and the back gate signal Gout (j + 2) and is synchronized with the clock signals LCLK1 and LCLK2 to carry the carry signal Cout ( j)] and the gate signal Gout (j).

A signal waveform of the liquid crystal display according to the exemplary embodiment of the present invention will now be described in detail with reference to FIGS. 7 and 8.

7 and 8 illustrate signal waveforms of a liquid crystal display according to an exemplary embodiment of the present invention, and in particular, FIG. 7 illustrates signal waveforms of the first and second pixels PXa and PXb of FIG. 3. 8 illustrates signal waveforms of the third and fourth pixels PXc and PXd of FIG. 3.

The gate signal is located in the same pixel row as shown in FIG. 3, and is connected to the j th output Gout (j) applied to the pixel sets a and b connected to the same data lines D ₁ -D _m . The (j + 1) th output [Gout (j + 1)] is shown.

The data voltage is applied from the data driver 500 to the data lines D ₁ -D _m , and the first gate driver 400L applies the gate-on voltage Von in response to the first scan start signal LSTV. is applied to _{(G i, G i + 2} ...) turns on the switching element (Q) connected to a gate line _{(G i, G i + 2} ...). At this time, the gate-on voltage (Von) is maintained for 1/2 H and then changed to the gate-off voltage (Voff). While the gate-on voltage Von is applied, a data signal applied to the data lines D ₁ -D _m is applied to the first pixel PXa through the turned-on switching element Q. Then, the kickback occurs as soon as the first pixel electrode voltage Vpa of the negative polarity (-) is changed to the positive polarity (+) and increases, and then the gate-on voltage Von is changed to the gate-off voltage Voff. Then, the first pixel electrode voltage Vpa is reduced by the kickback voltage ΔVk to maintain the common voltage Vcom and a constant voltage ΔVpa.

The data voltage is applied from the data driver 500 to the data lines D ₁ -D _m , and the second gate driver 400R applies the gate-on voltage Von in response to the second scan start signal RSTV. is applied to _{(G i + 1, G i} + 3 ...) it turns on the switching element (Q) connected to a gate line _{(G i + 1, G i} + 3 ...). The gate-on voltage Von is maintained for 1/2 H without overlapping the waveform with the previous gate-on voltage Von. After that, the gate-off voltage Voff is changed. While the gate-on voltage Von is applied, a data signal applied to the data lines D ₁ -D _m is applied to the second pixel PXb through the turned-on switching element Q. Then, the kickback occurs when the pixel electrode voltage Vpb of negative polarity is changed to positive polarity (+) and then increases, and the gate-on voltage Von is changed to the gate-off voltage Voff. Then, the second pixel electrode voltage Vpb is reduced by the kickback voltage ΔVk to maintain the common voltage Vcom and a constant voltage ΔVpb.

The first pixel electrode voltage Vpa and the second pixel electrode voltage Vpb are all kicked once and have the same difference ΔVpa and ΔVpb from the common voltage Vcom. Therefore, the gradation to be actually displayed can be accurately represented without change. In other words, a voltage higher or lower than a voltage corresponding to the target gray level is expressed to prevent vertical streaks caused by pixels being brighter or darker than the target gray level.

The data voltage is applied from the data driver 500 to the data lines D ₁ -D _m , and the first gate driver 400L applies the gate-on voltage Von in response to the first scan start signal LSTV. is applied to _{(G i, G i + 2} ...) turns on the switching element (Q) connected to a gate line _{(G i, G i + 2} ...). At this time, the gate-on voltage (Von) is maintained for 1/2 H and then changed to the gate-off voltage (Voff). While the gate-on voltage Von is applied, the data signal applied to the data lines D ₁ -D _m is applied to the third pixel PXc through the turned-on switching element Q. Then, the kickback occurs as soon as the third pixel electrode voltage Vpc of positive polarity (+) is changed to negative polarity (−) and then increases, and the gate-on voltage (Von) is changed to the gate-off voltage (Voff). As a result, the third pixel electrode voltage Vpc is reduced by the kickback voltage ΔVk to maintain the common voltage Vcom and a constant voltage ΔVpc.

The data voltage is applied from the data driver 500 to the data lines D ₁ -D _m , and the second gate driver 400R applies the gate-on voltage Von in response to the second scan start signal RSTV. is applied to _{(G i + 1, G i} + 3 ...) it turns on the switching element (Q) connected to a gate line _{(G i + 1, G i} + 3 ...). The gate-on voltage Von is maintained for 1/2 H without overlapping the waveform with the previous gate-on voltage Von. After that, the gate-off voltage Voff is changed. While the gate-on voltage Von is applied, the data signal applied to the data lines D ₁ -D _m is applied to the fourth pixel PXd through the turned-on switching element Q. Then, a kickback occurs as the pixel electrode voltage Vpd of positive polarity (+) changes to negative polarity (-) and increases, and the gate-on voltage (Von) changes to the gate-off voltage (Voff). As a result, the fourth pixel electrode voltage Vpd decreases by the kickback voltage ΔVk to maintain the common voltage Vcom and a constant voltage ΔVpd.

The third pixel electrode voltage Vpc and the fourth pixel electrode voltage Vpd are all kickbacks, but the differences ΔVpc and ΔVpd are the same as those of the common voltage Vcom. Therefore, the target gradation can be expressed.

According to the present invention, the secondary kickback may be prevented from occurring in some pixels, thereby preventing flicker or smearing of the screen.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (15)

Board, A plurality of pixels arranged in a matrix on the substrate and having a switching element, A plurality of pairs of first and second gate lines connected to the switching element and transmitting a gate signal including a gate on voltage for turning on the switching element, and separated from each other; A plurality of data lines connected to the switching elements and transferring data voltages Including, And a gate-on voltage applied to the first gate line and a gate-on voltage applied to the second gate line do not overlap. In claim 1, And a gate-on voltage applied to the first gate line for 1/2 H, and a gate-on voltage applied to the second gate line for 1/2 H. In claim 1, And one data line for each of two adjacent pixel columns. In claim 1, And a gate driver connected to the first and second gate lines to generate the gate signal based on a plurality of clock signals. In claim 4, And the gate driver is integrated on the substrate. In claim 5, The gate driver, A first gate driver connected to an odd-numbered gate line among the gate lines, and A second gate driver connected to an even-numbered gate line among the gate lines Liquid crystal display comprising a. In claim 6, The first and second gate drivers are disposed opposite to each other with the pixel therebetween. In claim 6, The duty ratio of the plurality of clock signals is 25%. In claim 6, The plurality of clock signals include first to fourth clock signals, And a phase difference between adjacent clock signals among the first to fourth clock signals is 180 degrees. In claim 9, And the first and third clock signals are input to the first gate driver, and the second and fourth clock signals are input to the second gate driver. In claim 10, And first and second output start signals are respectively input to the first and second gate drivers. In claim 1, And two pixels arranged in a row direction between two adjacent data lines among the data lines are connected to the same data line. In claim 1, 2. A liquid crystal display device in which two pixels adjacent in a column direction are connected to different data lines. In claim 1, When two pixels arranged adjacently in a row direction between two adjacent data lines among the data lines are referred to as unit pixel pairs, 2. The liquid crystal display of claim 2, wherein the positions of the switching elements of the two unit pixel pairs adjacent in the row direction are the same. In claim 1, When two pixels arranged adjacently in a row direction between two adjacent data lines among the data lines are referred to as unit pixel pairs, Two pixels of the unit pixel pair are connected to different gate lines.

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