KR20070076177A - Liquid crystal display - Google Patents

Abstract

An LCD is provided to cover a gate driver formed on a display panel even with an edge portion of a sealing member, thereby effectively protecting the gate driver from an external environment. A plurality of pixels are arranged on a substrate in a matrix type, wherein the pixels have switching elements. A plurality of gate lines are extended in a row direction, and electrically connected to the switching elements. A gate driver(400) includes a plurality of gate driving ICs(410) mounted on the substrate, wherein the gate driving ICs are electrically connected to the gate lines. The gate driver includes a first region(400a) linearly aligned and a second region(400b) across the first region.

Description

Liquid crystal display {LIQUID CRYSTAL DISPLAY}

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a block diagram of a liquid crystal display according to another exemplary embodiment of the present invention.

4 is a plan view of a liquid crystal panel assembly according to an embodiment of the present invention.

FIG. 5 is a cross-sectional view of the liquid crystal panel assembly of FIG. 4 taken along the line VV. FIG.

FIG. 6 is a plan view showing a part of the liquid crystal panel assembly shown in FIG. 4 in detail. FIG.

7 is a block diagram of a gate driver according to an exemplary embodiment of the present invention.

FIG. 8 is an example of a circuit diagram of the j-th stage of the shift register for gate driver shown in FIG. 7; FIG.

9 is a schematic layout view of a gate driver according to an exemplary embodiment of the present invention.

<Description of Drawing>

3: liquid crystal layer 110, 210: substrate

100: lower panel 191: pixel electrode

200: upper display panel 220: light blocking member

270: common electrode 300: liquid crystal panel assembly

310: sealing material 400, 400R, 400L: gate drive unit

500: data driver

The present invention relates to a liquid crystal display device.

The liquid crystal display is one of the most widely used flat panel display devices, and includes two display panels on which an electric field generating electrode such as a pixel electrode and a common electrode are formed, and a liquid crystal layer interposed therebetween. The liquid crystal display generates an electric field in the liquid crystal layer by applying a voltage to the field generating electrode, thereby determining an orientation of liquid crystal molecules in the liquid crystal layer and controlling the polarization of incident light to display an image.

The liquid crystal display also includes a switching element connected to each pixel electrode and a plurality of signal lines such as a gate line and a data line for controlling the switching element and applying a voltage to the pixel electrode. The gate line generates a gate signal generated by the gate driving circuit, the data line transfers the data voltage generated by the data driving circuit, and the switching element transfers the data voltage to the pixel electrode according to the gate signal.

The gate driver and the data driver are formed in a chip form and mounted on the display panel. However, in recent years, in order to increase productivity while reducing the overall size of the display device, a structure for integrating the gate driver into the display panel has been developed.

An object of the present invention is to effectively protect the gate driver integrated in the display panel from the external environment.

According to an aspect of the present invention, a liquid crystal display device includes a substrate, a plurality of pixels arranged in a matrix form on the substrate, each pixel including a switching element, and a plurality of gates connected to the switching element and extending in a row direction. And a gate driver connected to a line and the gate line, respectively, and integrated and formed on the substrate, wherein the gate driver includes an aligned first region and a second region intersected with the first region.

The second region may include third and fourth regions divided by the first region.

The distance between the first region and the pixel may be longer than the distance between the second region and the pixel.

The gate driver may include a plurality of circuit parts connected to the gate line and a plurality of wiring parts connected to the circuit area to transmit a signal.

At least two of the plurality of circuit units may be arranged in a line, and at least one may be arranged in a staggered manner.

The wiring may be bent in the first region and the second region.

The display device may further include a sealing material formed to surround the pixel.

The sealant may cover the gate driver.

The sealant may cover all of the plurality of wirings of the gate driver.

The distance between the wiring portion of the first region and the wiring portion of the second region may be 300 μm or less.

The gate driver may include a first gate driver connected to an odd-numbered gate line among the gate lines, and a second gate driver connected to an even-numbered gate line among the gate lines.

The first gate driver and the second gate driver may be opposite to each other with the pixel therebetween.

According to another aspect of the present invention, a liquid crystal display device includes a substrate, a plurality of pixels arranged in a matrix form on the substrate, each pixel including a switching element, a plurality of gate lines connected to the switching element, and extending in a row direction; A gate driver connected to the gate line, the gate driver being integrally formed on the substrate, and a sealing member covering the gate driver, wherein the gate driver is aligned with the first region and the second region intersected with the first region. It includes an area.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

First, a liquid crystal display according to an exemplary embodiment of the present invention will be described with reference to FIGS. 1 and 2.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of one pixel of the liquid crystal display according to an exemplary embodiment of the present invention.

1 and 2, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a pair of gate drivers 400, and a data driver 500 connected thereto. The gray voltage generator 800 connected to the data driver 500 and a signal controller 600 for controlling the gray voltage generator 800 are included.

The liquid crystal panel assembly 300 may include a plurality of signal lines G ₁ -G _{n and} D ₁ -D _m and a plurality of pixels PX connected to the plurality of signal lines G ₁ -G _{n and} D ₁ -D _m , which are arranged in a substantially matrix form. Include. In contrast, in the structure shown in FIG. 2, the liquid crystal panel assembly 300 includes lower and upper panels 100 and 200 facing each other and a liquid crystal layer 3 interposed therebetween.

The signal line includes a plurality of gate lines G ₁ -G _n transmitting a gate signal (also referred to as a “scan signal”) and a plurality of data lines D ₁ -D _m transmitting a data signal. The gate lines G ₁ -G _n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

Each pixel PX includes a switching element Q connected to a signal line, a liquid crystal capacitor Clc, and a storage capacitor Cst connected thereto. Holding capacitor Cst can be omitted as needed.

The switching element Q is a three-terminal element of a thin film transistor or the like provided in the lower panel 100, the control terminal of which is connected to the gate line G _i , and the input terminal of which is connected to the data line D _j . The output terminal is connected to the liquid crystal capacitor Clc and the storage capacitor Cst.

The liquid crystal capacitor Clc has two terminals, the pixel electrode 191 of the lower panel 100 and the common electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 191 and 270 is a dielectric material. Function as. The pixel electrode 191 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives the common voltage Vcom. Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, at least one of the two electrodes 191 and 270 may be formed in a linear or bar shape.

The storage capacitor Cst, which serves as an auxiliary role of the liquid crystal capacitor Clc, is formed by overlapping a separate signal line (not shown) and the pixel electrode 191 provided on the lower panel 100 with an insulator interposed therebetween. A predetermined voltage such as the common voltage Vcom is applied to the separate signal line. However, the storage capacitor Cst may be formed such that the pixel electrode 191 overlaps the front gate line directly above the insulator.

On the other hand, in order to implement color display, each pixel PX uniquely displays one of the primary colors (spatial division) or each pixel PX alternately displays the primary colors over time (time division). The desired color is recognized by the spatial and temporal sum of these primary colors. Examples of the primary colors include three primary colors such as red, green, and blue. FIG. 2 illustrates that each pixel PX includes a color filter 230 representing one of the primary colors in an area of the upper panel 200 corresponding to the pixel electrode 191 as an example of spatial division. Unlike FIG. 2, the color filter 230 may be formed above or below the pixel electrode 191 of the lower panel 100.

At least one polarizer (not shown) for polarizing light is attached to an outer surface of the liquid crystal panel assembly 300.

Referring back to FIG. 1, the gray voltage generator 800 generates two sets of gray voltage sets (or reference gray voltage sets) related to the transmittance of the pixel PX. One of the two sets has a positive value for the common voltage Vcom and the other set has a negative value.

The gate driver 400 is connected to the gate lines G ₁ -G _n of the liquid crystal panel assembly 300 to receive a gate signal formed of a combination of the gate on voltage Von and the gate off voltage Voff. ₁ -G _n ). The gate driver 400 includes a plurality of stages substantially arranged in a row as a shift register, and together with the signal lines G ₁ -G _n , D ₁ -D _m , and the thin film transistor switching element Q. In the same process, the liquid crystal panel assembly 300 is formed and integrated.

The data driver 500 is connected to the data lines D ₁ -D _m of the liquid crystal panel assembly 300 and selects a gray voltage from the gray voltage generator 800 and uses the data line D ₁ as a data signal. -D _m ). However, when the gray voltage generator 800 provides only a predetermined number of reference gray voltages instead of providing all of the voltages for all grays, the data driver 500 divides the reference gray voltages to divide the gray voltages for all grays. Generate and select the data signal from it.

The signal controller 600 controls the gate driver 400, the data driver 500, and the like.

Each of the driving devices 500, 600, and 800 may be mounted directly on the liquid crystal panel assembly 300 in the form of at least one integrated circuit chip, or mounted on a flexible printed circuit film (not shown). And attached to the liquid crystal panel assembly 300 in the form of a tape carrier package (TCP) or mounted on a separate printed circuit board (not shown). Alternatively, these driving devices 500, 600, and 800 may be integrated in the liquid crystal panel assembly 300 together with the signal lines G ₁ -G _n , D ₁ -D _m , and the thin film transistor switching element Q. . In addition, the driving apparatuses 500, 600, and 800 may be integrated into a single chip, in which case at least one of them or at least one circuit element constituting them may be outside the single chip.

A liquid crystal display according to another exemplary embodiment of the present invention will now be described with reference to FIG. 3.

3 is a block diagram of a liquid crystal display according to another exemplary embodiment of the present invention.

Referring to FIG. 3, the liquid crystal display according to the present exemplary embodiment includes a liquid crystal panel assembly 300, a gate driver 400 connected thereto, a data driver 500, and a gray level connected to the data driver 500. And a voltage generator 800 and a signal controller 600 for controlling the voltage generator 800.

However, in the liquid crystal display of FIG. 3, unlike the liquid crystal display of FIG. 1, a pair of gate lines G ₁ -G _2n are arranged for each pixel row.

In addition, the gate driver 400 is divided into first and second gate drivers 400L and 400R disposed on the right and left sides of the liquid crystal panel 300. The first gate driver 400L is connected to odd-numbered gate lines G ₁ , G ₃ ,... G _2n-1 , and the second gate driver 400R is even-numbered gate lines G ₂ , G ₄ ,... G _2n ). However, the present invention is not limited thereto, and the odd-numbered gate lines G ₁ , G ₃ ,... G _2n-1 are connected to the second gate driver 400R, and the even-numbered gate lines G ₂ , G ₄ ,..., G _2n ) May be connected to the first gate driver 400L.

As such, the first and second gate drivers 400L and 400R are connected to the gate lines G ₁ -G _2n of the liquid crystal panel assembly 300, respectively, to combine the gate on voltage Von and the gate off voltage Voff. Is applied to each gate line G ₁ -G _2n .

As a result, gate signals may be applied to the gate lines G ₁ -G _2n at both sides of the liquid crystal panel assembly 300, thereby preventing the gate signals from being delayed at one side of the gate lines G ₁ -G _2n . Therefore, the gate signal can be more effectively transmitted over the entire gate line G ₁ -G _2n .

Next, the operation of the liquid crystal display will be described in detail.

The signal controller 600 receives input image signals R, G, and B and an input control signal for controlling the display thereof from an external graphic controller (not shown). Examples of the input control signal include a vertical sync signal Vsync, a horizontal sync signal Hsync, a main clock MCLK, and a data enable signal DE.

The signal controller 600 properly processes the input image signals R, G, and B according to operating conditions of the liquid crystal panel assembly 300 based on the input image signals R, G, and B and the input control signal, and controls the gate. After generating the signal CONT1 and the data control signal CONT2, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signal DAT are transmitted to the data driver 500. Export to).

The gate control signal CONT1 includes a scan start signal STV indicating a scan start and at least one clock signal controlling an output period of the gate-on voltage Von. The gate control signal CONT1 may also further include an output enable signal OE that defines the duration of the gate-on voltage Von.

The data control signal CONT2 is a load for applying a data signal to the horizontal synchronization start signal STH and the data lines D ₁ -D _m indicating the start of image data transmission for the pixels PX in one row [bundling]. Signal LOAD and data clock signal HCLK. The data control signal CONT2 is also an inverted signal that inverts the voltage polarity of the data signal relative to the common voltage Vcom (hereinafter referred to as " polarity of the data signal " by reducing the " voltage polarity of the data signal for the common voltage &quot;) RVS) may be further included.

According to the data control signal CONT2 from the signal controller 600, the data driver 500 receives the digital image signal DAT for the pixels PX in one row (bundling), and each digital image signal DAT. By converting the digital image signal DAT into an analog data signal by selecting a gray scale voltage corresponding to), it is applied to the corresponding data lines D ₁ -D _m .

The gate driver 400 applies the gate-on voltage Von to the gate lines G ₁ -G _2n according to the gate control signal CONT1 from the signal controller 600, thereby applying the gate lines G ₁ -G _2n . Turn on the switching element (Q) connected to. Then, the data signal applied to the data lines D ₁ -D _m is applied to the pixel PX through the switching element Q turned on.

The difference between the voltage of the data signal applied to the pixel PX and the common voltage Vcom is shown as the charging voltage of the liquid crystal capacitor Clc, that is, the pixel voltage. The arrangement of the liquid crystal molecules varies depending on the magnitude of the pixel voltage, thereby changing the polarization of light passing through the liquid crystal layer 3. The change in polarization is represented by a change in transmittance of light by a polarizer attached to the display panel assembly 300.

This process is repeated in units of one horizontal period (also referred to as "1H" and equal to one period of the horizontal sync signal Hsync and the data enable signal DE), so that all the gate lines G ₁ -G _2n are repeated. ), The gate-on voltage Von is sequentially applied to the data signal to all the pixels PX, thereby displaying an image of one frame.

When one frame ends, the state of the inversion signal RVS applied to the data driver 500 is controlled so that the next frame starts and the polarity of the data signal applied to each pixel PX is opposite to the polarity of the previous frame. "Invert frame"). In this case, the polarity of the data signal flowing through one data line is changed (eg, row inversion and point inversion) or the polarity of the data signal applied to one pixel row is different depending on the characteristics of the inversion signal RVS within one frame. (E.g. column inversion, point inversion).

Next, the liquid crystal panel assembly and the gate driver formed in the liquid crystal panel assembly according to the exemplary embodiment of the present invention will be described in detail with reference to FIGS. 4 to 9.

4 is a plan view illustrating a liquid crystal panel assembly according to an exemplary embodiment of the present invention. FIG. 5 is a cross-sectional view of the liquid crystal panel assembly of FIG. 4 taken along the line VV. FIG. 6 is a view of the liquid crystal panel of FIG. 4. It is a top view which shows the edge part of an assembly in detail.

4 to 6, a liquid crystal panel assembly according to an exemplary embodiment of the present invention may include a thin film transistor array panel 100, a common electrode display panel 200, and a liquid crystal layer interposed between the two display panels 100 and 200. 3) and a sealing material 310 for sealing the liquid crystal layer 3.

The liquid crystal panel assembly 300 is divided into a display area DA displaying an image and a peripheral area PA on one side of the display area DA.

The data driver 500 connected to the data lines D ₁ -D _m is mounted on the substrate 110 of the peripheral area PA.

The substrate 110 of the display area DA has a gate line G ₁ -G _n , a data line D ₁ -D _m intersecting with the gate lines G ₁ -G _n , and a gate line G ₁ -G. _n ), a thin film transistor (not shown) connected to the data lines D ₁ -D _m , a pixel electrode 191 connected to the thin film transistor, and the like are formed.

The gate driver 400 is integrated around both sides of the display area DA. The gate driver 400 includes a plurality of gate driving circuits 410. In addition, the gate driver 400 includes a first region 400a arranged in a line and a second region 400b intersected with the first region 400a. The second area 400b is divided into two parts, the top area and the bottom area with the first area 400a therebetween.

At least one gate driving circuit 410 is disposed closer to the display area DA than the gate driving circuit 410 of the first region 400a in the second region 400b. The distance D between the gate driving circuit 410 disposed at the top of the second region 400b and the gate driving circuit 410 of the first region 400a is preferably 300 μm or less.

The sealing material 310 is formed around the display area DA, and the corner portion 311 of the sealing material 310 is formed by being rounded or chamfered in the process.

The second region 400b of the gate driver 400 substantially coincides with the position of the edge portion 311 of the sealant 310. Therefore, the gate driver 400 is covered by the sealing material 310. As a result, the gate driver 400 may be exposed to the external environment to prevent corrosion. In particular, the portion 410a of the gate driver 400 in the direction opposite to the display area DA is completely covered with the sealant 310 in all portions including the edge portion 311 of the sealant 310.

The common electrode panel 200 is bonded to the thin film transistor array panel 100 by a sealing material 310. The light blocking layer 220 is formed on the substrate 210 of the common electrode display panel 200, and the common electrode 270 is formed on the light blocking layer 220. A color filter (not shown) may be formed between the substrate 210 and the common electrode 270. However, the color filter may be formed on the thin film transistor array panel 100.

7 to 8, the gate driver 400 of the liquid crystal panel assembly according to the exemplary embodiment of the present invention will be described in detail.

7 is a block diagram of a gate driver according to an embodiment of the present invention, and FIG. 8 is a circuit diagram of the j-th stage of a shift register for a gate driver according to an embodiment of the present invention, and FIG. 9 is an embodiment of the present invention. It is a layout view of the gate drive part which concerns on an example.

7 to 9, the first and second scan start signals LSTV and RSTV and the first to fourth clock signals LCLK1, RCLK1, and LCLK2 are included in the shift registers 400R and 400L, which are the gate driver 400. , RCLK2) is input. Each shift register 400L and 400R includes a plurality of stages ST1-STj + 3 connected to gate lines, respectively. The plurality of stages ST1-STj + 3 are dependently connected to each other, and the first and second scan start signals LSTV and RSTV and the first to fourth clock signals LCLK1, RCLK1, LCLK2, and RCLK2 are inputted. do.

As shown in FIG. 6, the first scan start signal LSTV input to the left shift register 400L and the second scan start signal RSTV input to the right shift register 400R have a plurality of widths of 1H. It is a signal of one frame period including one pulse in one frame.

Different clock signals LCLK1, RCLK1, LCLK2, and RCLK2 are input to two adjacent stages 410L and 410R in each of the shift registers 400L and 400R. For example, the first clock signal LCLK1 is input to the first stage of the left shift register 400L, the third clock signal LCLK2 is input to the second stage, and the first stage is input to the first stage of the right shift register 400R. The fourth clock signal RCLK2 is input to the second clock signal RCLK1 and the second stage.

Each clock signal LCLK1, RCLK1, LCLK2, RCLK2 is a gate on voltage V _on capable of driving the switching element Q of the pixel when high, and a gate off voltage V _off when low. It is preferable.

Each stage 410L, 410R includes a set terminal S, a gate voltage terminal GV, a pair of clock terminals CK1 and CK2, a reset terminal R, a frame reset terminal FR, and a gate output. It has a terminal OUT1 and a carry output terminal OUT2.

In each stage, for example, the set terminal S of the j-th stage STj, the carry output of the front stage ST (j-2), that is, the front carry output Cout (j-2), is a reset terminal. The gate output of the rear stage [ST (j + 2)], that is, the rear gate output Gout (j + 2), is input to (R), and the clock signals LCLK1 and LCLK2 are supplied to the clock terminals CK1 and CK2. The gate off voltage V _off is input to the gate voltage terminal GV. The gate output terminal OUT1 outputs the gate output Gout (j) and the carry output terminal OUT2 outputs the carry output Cout (j).

However, the scan start signals LSTV and RSTV are input to the first stage of each shift register 400L and 400R instead of the front carry output. Also, when the clock signal LCLK1 is input to the clock terminal CK1 of the j-th stage STj and the clock signal LCLK2 is input to the clock terminal CK2, the (j-2) th and (j + The clock signal LCLK2 is input to the clock terminal CK1 of the 2nd-th stage ST (j-2, ST (j + 2)), and the clock signal LCLK1 is input to the clock terminal CK2.

Referring to FIG. 8, each stage of the gate driver 400 according to an embodiment of the present invention, for example, the j-th stage, includes an input unit 420, a pull-up driver 430, a pull-down driver 440, and an output. A portion 450 is included. These include at least one NMOS transistor T1-T14, and the pull-up driver 430 and the output unit 450 further include capacitors C1-C3. However, PMOS transistors may be used instead of NMOS transistors. In addition, the capacitors C1-C3 may actually be parasitic capacitances between the gate and the drain / source formed during the process.

The input unit 420 includes three transistors T11, T10, and T5 connected in series to the set terminal S and the gate voltage terminal GV. Gates of the transistors T11 and T5 are connected to the clock terminal CK2, and gates of the transistor T10 are connected to the clock terminal CK1. The contact between the transistor T11 and the transistor T10 is connected to the contact J1, and the contact between the transistor T10 and the transistor T5 is connected to the contact J2.

The pull-up driving unit 430 includes a transistor T4 connected between the set terminal S and the contact J1, a transistor T12 connected between the clock terminal CK1 and the contact J3, and a clock terminal ( And transistor T7 connected between CK1 and contact J4. The gate and the drain of the transistor T4 are commonly connected to the set terminal S, the source is connected to the contact J1, and the gate and the drain of the transistor T12 are commonly connected to the clock terminal CK1. And the source is connected to contact J3. The gate of the transistor T7 is connected to the contact J3 and at the same time connected to the clock terminal CK1 through the capacitor C1, the drain is connected to the clock terminal CK1, the source is connected to the contact J4. , Capacitor C2 is connected between contact J3 and contact J4.

The pull-down driver 440 receives the gate-off voltage V _off through a source and outputs a plurality of transistors T6, T9, T13, T8, T3, and T2 through a drain to the contacts J1, J2, J3, and J4. ). The gate of the transistor T6 is connected to the frame reset terminal FR, the drain is connected to the contact J1, the gate of the transistor T9 is connected to the reset terminal R, and the drain is connected to the contact J1. The gates of the transistors T13 and T8 are commonly connected to the contact J2, and the drains are connected to the contacts J3 and J4, respectively. The gate of the transistor T3 is connected to the contact J4, the gate of the transistor T2 is connected to the reset terminal R, and the drains of the two transistors T3 and T2 are connected to the contact J2.

The output unit 450 includes a pair of transistors T1 and T14 having a drain and a source connected between the clock terminal CK1 and the output terminals OUT1 and OUT2 and a gate connected to the contact J1, respectively. And a capacitor C3 connected between the gate and the drain of T1, that is, between the contact J1 and the contact J2. The source of transistor T1 is also connected to contact J2.

The operation of such a stage will now be described.

For convenience of explanation, the voltage corresponding to the high level of the clock signals LCLK1, LCKL2, RCLK1, and RCLK2 is called a high voltage, and the magnitude of the voltage corresponding to the low level of the clock signals LCLK1, LCLK2, RCLK1, and RCLK2 is a gate. It is equal to the off voltage (V _off ) and is called low voltage.

First, when the clock signal LCLK2 and the front carry output Cout (j-2) become high, the transistors T11 and T5 and the transistor T4 are turned on. Then, the two transistors T11 and T4 transfer a high voltage to the contact J1, and the transistor T5 transfers a low voltage to the contact J2. As a result, the transistors T1 and T14 are turned on so that the clock signal CLK1 is output to the output terminals OUT1 and OUT2. At this time, since the voltage of the contact J2 and the clock signal LCLK1 are both low voltages, the output voltage [ Gout (j) and Cout (j)] become low voltage. At the same time, the capacitor C3 charges a voltage having a magnitude corresponding to the difference between the high voltage and the low voltage.

At this time, since the clock signal LCLK1 and the rear gate output Gout (j + 2) are low and the contact J2 is also low, the transistors T10, T9, T12, T13, T8, and T2 connected to the gate are connected. ) Are all off.

Subsequently, when the clock signal LCLK2 becomes low, the transistors T11 and T5 are turned off. At the same time, when the clock signal LCLK1 becomes high, the output voltage of the transistor T1 and the voltage of the contact J2 become high. do. At this time, a high voltage is applied to the gate of the transistor T10, but since the potential of the source connected to the contact J2 is also the same high voltage, the potential difference between the gate sources becomes zero, so that the transistor T10 remains turned off. . Accordingly, the contact J1 is in a floating state, whereby the potential is further increased by the high voltage by the capacitor C3.

On the other hand, since the potentials of the clock signal LCLK1 and the contact J2 are high voltage, the transistors T12, T13, and T8 are turned on. In this state, the transistor T12 and the transistor T13 are connected in series between the high voltage and the low voltage, so that the potential of the contact J3 is divided by the resistance value of the resistance state at the turn-on of the two transistors T12 and T13. Voltage value. However, assuming that the resistance value of the resistance state at the turn-on of the two transistors T13 is set to be very large compared to the resistance value of the resistance state at the turn-on of the transistor T12, for example, about 10,000 times, the voltage of the contact J3 is a high voltage. Is almost the same as Accordingly, the transistor T7 is turned on and connected in series with the transistor T8, so that the potential of the contact J4 is divided by the resistance value of the resistance state at the turn-on of the two transistors T7 and T8. Have At this time, if the resistance values of the resistance states of the two transistors T7 and T8 are set to be almost the same, the potential of the contact J4 has an intermediate value between the high voltage and the low voltage, whereby the transistor T3 is turned off. Keep it. At this time, since the rear gate output Gout (j + 2) is still low, the transistors T9 and T2 also remain turned off. Therefore, the output terminals OUT1 and OUT2 are connected only to the clock signal CLK1 and cut off from the low voltage to emit a high voltage.

On the other hand, the capacitor C1 and the capacitor C2 charge voltages corresponding to the potential difference between both ends, respectively, and the voltage of the contact J3 is lower than the voltage of the contact J5.

Subsequently, when the rear gate output Gout (j + 1) and the clock signal CLK2 go high and the clock signal CLK1 goes low, the transistors T9 and T2 are turned on to low voltage to the contacts J1 and J2. To pass. At this time, the voltage of the contact J1 falls to the low voltage while the capacitor C3 discharges, but it takes some time to completely lower to the low voltage due to the discharge time of the capacitor C3. Therefore, the two transistors T1 and T14 remain turned on for a while even after the rear gate output Gout (j + 1) becomes high, so that the output terminals OUT1 and OUT2 are connected to the clock signal CLK1. To emit low voltage. Subsequently, when the capacitor C3 is completely discharged and the potential of the contact J1 reaches a low voltage, the transistor T14 is turned off and the output terminal OUT2 is cut off from the clock signal CLK1, so that the carry output Cout (j) is performed. Becomes floating and maintains low voltage. At the same time, the output terminal OUT1 is continuously connected to the low voltage through the transistor T2 even when the transistor T1 is turned off, thereby continuously outputting the low voltage.

On the other hand, since the transistors T12 and T13 are turned off, the contact J3 is in a floating state. In addition, the voltage of the contact J5 is lower than the voltage of the contact J4. The transistor T7 is turned off because the voltage of the contact J3 is kept lower than the voltage of the contact J5 by the capacitor C1. . At the same time, since the transistor T8 is also turned off, the voltage at the contact J4 is lowered by that amount, so that the transistor T3 also remains turned off. In addition, the transistor T10 maintains the turn-off state because the gate is connected to the low voltage of the clock signal CLK1 and the voltage of the contact J2 is low.

Next, when the clock signal CLK1 becomes high, the transistors T12 and T7 turn on, the voltage of the contact J4 rises, turns on the transistor T3, and transfers a low voltage to the contact J2. ) Continues to emit low voltage. That is, even if the rear gate output Gout (j + 1) has a low output, the voltage of the contact J2 can be made low.

Meanwhile, since the gate of the transistor T10 is connected to the high voltage of the clock signal CLK1 and the voltage of the contact J2 is a low voltage, the gate of the transistor T10 is turned on to transfer the low voltage of the contact J2 to the contact J1. On the other hand, the clock terminal CK1 is connected to the drains of the two transistors T1 and T14, and the clock signal CLK1 is continuously applied. In particular, the transistor T1 is made relatively larger than the rest of the transistors, so that the parasitic capacitance between gate drains is large, so that the voltage change of the drain may affect the gate voltage. Therefore, when the clock signal CLK1 becomes high, the gate voltage may increase due to the parasitic capacitance between the gate and drain gates, thereby turning on the transistor T1. Therefore, the low voltage of the contact J2 is transferred to the contact J1 to maintain the gate voltage of the transistor T1 at a low voltage, thereby preventing the transistor T1 from turning on.

Thereafter, the voltage at the contact J1 maintains a low voltage until the front carry output Cout (j-2) becomes high, and the voltage at the contact J2 has the clock signal CLK1 high and the clock signal CLK2. Is low, the low voltage is maintained through the transistor T3, and vice versa, the low voltage is maintained through the transistor T5.

On the other hand, the transistor T6 receives the initialization signal INT generated in the last dummy stage (not shown) and transfers the gate-off voltage V _off to the contact J1 to transfer the voltage of the contact J1 once more. Set to low voltage.

In this manner, the stage 410 is based on the front carry signal Cout (j-2) and the back gate signal Gout (j + 2) and is synchronized with the clock signals LCLK1 and LCLK2 to carry the carry signal Cout ( j)] and the gate signal Gout (j).

Next, an arrangement on the thin film transistor array panel 100 of the gate driver 400 illustrated in FIG. 4 will be described in detail with reference to FIG. 9.

9 is a schematic layout view of a gate driver 400 according to an embodiment of the present invention.

Referring to FIG. 9, the gate driver 400 according to the present invention includes the circuit unit CS including the stages ST1-STj + 3 described above, and various signals Voff and LCKV1 input to the stages ST1-STj + 3. And a wiring unit LS for transmitting RCKV1, LCKV2, RCKV2, and INT). 9 illustrates only the gate driver 400 formed on the left side of the display area DA.

The wiring part LS may include a gate-off voltage line SL1 that transmits a gate-off voltage Voff, and first and second clock signal lines that transmit first and second clock signals LCKV1, RCKV1, LCKV2, and RCKV2, respectively. SL2 and SL3 and an initialization signal line SL4 for transmitting the initialization signal INT. Each signal line SL1 -SL4 extends mainly in the vertical direction, and is disposed in order from the left in the order of the gate-off voltage line SL1, the clock signal lines SL2 and SL3, and the initialization signal line SL4 to the shift register 400. Getting closer. The positions of the gate-off voltage line SL1 and the initialization signal line SL4 may be interchanged. In addition, these signal lines SL1-SL4 have connecting lines extending horizontally toward the stages ST1, ST3, ST5, and ST7. The gate-off voltage line SL1 and the initialization signal line SL4 are connected to one stage ST1, ST3, Although one connection line is provided to each of ST5 and ST7, the first and second clock signal lines SL2 and SL3 are positioned near the boundary of the stages ST1, ST3, ST5, and ST7, and alternately form one connection line.

In the circuit section CS, when the stages ST1, ST3, ST5, ST7 and the transistors T1-T13, T15 in the first stage ST1 are disposed, the front carry signal Cout (j- 1)] is disposed, and transistors T1 and T15 that receive the first clock signal LCKV1 are arranged along the connection line of the first clock signal line SL2 extending in the horizontal direction. The transistors T7, T10, and T12, which receive the first clock signal LCKV1, are also disposed below the transistor T15. In addition, the transistors T11 and T5 connected to the connection line of the second clock signal line SL3 rising from the bottom to receive the second clock signal LCKV2 are disposed on the lower left side, and the initialization signal line SL4 coming from the left side. The transistor T6 connected to the connection line of the signal receiving the initialization signal INT is disposed on the leftmost side. In addition, the transistors T2, T3, T8, T9, and T13 that receive the gate-off voltage Voff are disposed below the connection line of the gate-off voltage line SL1 extending in the horizontal direction.

In the case of the second stage ST2 adjacent thereto, the first clock signal line SL2 and the first clock signal LCKV1 are converted into the second clock signal line SL3 and the second clock signal LCKV2 and vice versa. The arrangement of each transistor is the same as that of the first stage ST1, except that SL3 and the second clock signal LCKV2 are changed to the first clock signal line SL2 and the first clock signal CKV.

A part of the circuit part CS and the wiring part LS are aligned in a line, and the other part is arranged in staggered manner. That is, the distance between the first stage ST1 and the display area DA is shortest, the distance between the second stage ST2 and the display area DA is next shortest, and the third stage ST3 and the display area DA are shortest. The distance between DA) is the longest. The stages after the fourth stage ST4 are aligned with the third stage ST3.

As a result, the wiring unit LS adjacent to the stage below the third stage ST3 is aligned in a line. However, the wiring part LS adjacent to the second stage ST2 is turned toward the display area DA and is crossed in the wiring part LS adjacent to the third stage ST3, and the wiring part LS adjacent to the first stage ST1 is crossed. Is turned toward the display area DA and is crossed in the wiring part LS adjacent to the second stage ST2.

Therefore, the gate driver 400 is divided into a first region 400b arranged in a line and a second region 400a intersected with the first region 400b, and the first and second stages ST1 and ST2 are connected to each other. The adjacent wiring units LS form the first region 400a, and the third and fourth stages ST3 and ST4 and the adjacent wiring units LS form the second region 400b.

Although not shown in detail in FIG. 9, as shown in FIG. 4, the lower portion of the gate driver 400 also has the same shape as in FIG. 9.

According to the present invention, the gate driver integrated on the display panel may be covered with the sealing material even at the edge of the sealing material. Thus, the gate driver is effectively protected from the external environment.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (13)

Board, A plurality of pixels arranged in a matrix form on the substrate, each pixel including a switching element; A plurality of gate lines connected to the switching element and extending in a row direction, and A gate driver connected to each of the gate lines and integrally formed on the substrate; Including, The gate driver includes an aligned first region and a second region intersected with the first region. Liquid crystal display. In claim 1, And the second region includes third and fourth regions divided by the first region. In claim 1, And a distance between the first area and the pixel is longer than a distance between the second area and the pixel. In claim 1, And the gate driver includes a plurality of circuit parts connected to the gate line and a plurality of wiring parts connected to the circuit area to transmit a signal. In claim 4, And at least two of the plurality of circuit parts are arranged in a line, and at least one of them is staggered. In claim 4, And wherein the wiring is bent in the first area and the second area. In claim 4, And a sealing material formed to surround the pixel. In claim 7, And the sealant covers the gate driver. In claim 7, And the sealing member covers all the plurality of wirings of the gate driver. In claim 4, The distance between the wiring portion of the first region and the wiring portion of the second region is 300 μm or less. In claim 1, The gate driver, And a second gate driver connected to an odd-numbered gate line among the gate lines, and a second gate driver connected to an even-numbered gate line among the gate lines. In claim 11, The first gate driver and the second gate driver are disposed opposite to each other with the pixel therebetween. Board, A plurality of pixels arranged in a matrix form on the substrate, each pixel including a switching element; A plurality of gate lines connected to the switching element and extending in a row direction, A gate driver connected to the gate line and integrally formed on the substrate, and Sealant covering the gate driver Including, The gate driver includes an aligned first region and a second region intersected with the first region. Liquid crystal display.

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