KR20070069760A - Saddle fin transistor and method for forming thereof - Google Patents

Abstract

A saddle fin transistor and a method for forming the same are provided to prevent the over-etching effect of a field oxide layer for forming a gate by etching the field oxide layer by using a photoresist pattern for covering only a protruded active region. A semiconductor substrate(10) having a protruded active region is prepared. A field oxide layer(20) is formed on the remaining region except for the active region. The height of the field oxide layer is equal to the height of the active region. A photoresist pattern is formed on the semiconductor substrate including the field oxide layer to expose a gate region. A groove is formed by etching the gate region of the exposed active region. The photoresist pattern is removed. The field oxide layer is etched to expose an upper end of the etched gate region and to round a lateral surface of the exposed upper end. A gate material is formed on the semiconductor substrate including the etched field oxide layer.

Description

Saddle fin transistor and method for forming thereof

1A to 1C are plan views for each process for explaining a method of manufacturing a conventional saddle protrusion transistor.

2A to 2D are cross-sectional views of processes for explaining a method of manufacturing a conventional saddle protrusion transistor.

3A to 3C are plan views for each process for explaining a method of manufacturing a saddle protrusion transistor according to the present invention;

Figures 4a to 4d is a cross-sectional view for each process for explaining the manufacturing method of the saddle protrusion transistor according to the invention.

Explanation of symbols on the main parts of the drawings

10: semiconductor substrate 20: field oxide film

30: first photosensitive film pattern 40: groove

50a: polysilicon film 50b: tungsten silicide film

50c: hardmask 50: gate

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method of forming a saddle fin transistor.

In recent years, as the design rules of highly integrated MOSFETs decrease rapidly, the channel length and width of the transistors correspondingly decrease, and the doping concentration to the junction region increases, thereby increasing the electric field. As the field increases, the junction leakage current increases. As a result, the transistor structure having a planar channel structure has reached a limit in improving the refresh characteristics by increasing the doping concentration of the channel region in order to obtain the threshold voltage value required by the highly integrated device. Accordingly, research on the idea and actual process development of the MOSFET device having a channel having a three-dimensional structure capable of expanding a channel region has been actively conducted.

As one of such efforts, a saddle fin transistor structure has been recently proposed as a transistor having a three-dimensional channel in the device field. The saddle protrusion transistor exposes both sides and the upper surface of the active region by etching the field region to protrude the active region. At this time, the protruding active region has a rounding profile, which is referred to as a saddle, and is called a saddle protrusion transistor.

Then, the gate line is formed so as to surround the protruding active region. In this case, a channel is formed on all three exposed surfaces of the active region, thereby greatly improving the current drive characteristic of the channel. Due to these advantages, the saddle protrusion transistor structure is attracting attention as the most ideal structure for implementing the next generation ultra-high density device (device).

Here, a method of forming a saddle protrusion transistor currently being performed will be briefly described with reference to FIGS. 2A to 2D.

FIG. 2A is a cross-sectional view taken along the line X-X 'of FIG. 1A, FIG. 2B is a cross-sectional view taken along the line Y-Y' of FIG. 1B, FIG. 2C is a cross-sectional view taken along the line Z-Z 'of FIG. 1B, and FIG. 2D Is a cross-sectional view taken along the line Y-Y 'of FIG. 1C.

Referring to FIG. 2A, after the semiconductor substrate 1 having the field oxide film 2 defining the active region is prepared, the photoresist pattern 3 exposing the gate forming region is formed on the substrate resultant. Then, the exposed portion of the substrate is etched using the photoresist pattern 3 to form the grooves 4.

2B and 2C, a portion of the field oxide film 2 is etched using the photoresist pattern 3 to protrude an active region of the substrate. In this case, the protruding active region has a rounding profile. Then, the photoresist pattern is removed.

Referring to FIG. 2D, a gate insulating film (not shown), a polysilicon film 5a, a tungsten silicide film 5b, and a hard mask film 5c are sequentially deposited on the entire surface of the substrate including the groove 4. These are etched to form a gate 5 on the groove 4.

Subsequently, although not shown, a series of successive known processes are subsequently carried out in order to fabricate a saddle protrusion transistor.

However, the conventional method of manufacturing the saddle protrusion transistor as described above has the following problems.

When the photoresist pattern used to etch a portion of the substrate to form the groove is used as an etching mask when the field oxide film is etched to protrude the active region, the field oxide film is overetched by a cleaning process. Due to the transient etching of the field oxide film (part A), when the gate formed in the field oxide film becomes an inner gate structure, a bridge with a landing plug contact when the gate misaligns. As a result, leakage current is generated between the cell and the cell, thereby degrading the characteristics of the transistor and also depressing the refresh characteristic.

Accordingly, an object of the present invention is to provide a method of forming a saddle protrusion transistor which can improve the excellent current driving capability and refresh characteristics of the saddle protrusion transistor. have.

In order to achieve the above object, the present invention comprises the steps of providing a semiconductor substrate protruding active region; Forming a field oxide film on a region other than the active region of the substrate at the same height as the substrate active region; Forming a photoresist pattern on the substrate resultant on which the field oxide film is formed to expose a gate predetermined region; Etching a portion of the gate predetermined region of the exposed substrate active region to form a groove; Removing the photoresist pattern; Etching the field oxide layer to expose the upper end of the etched gate region and round the side surface of the exposed upper end; And forming a gate material on the entire surface of the substrate including the etched field oxide film.

Here, the step of forming the field oxide film is characterized in that it is performed to 2500 to 35003 depth.

The etching of the field oxide layer may include forming a photoresist pattern covering a portion of the active region protruding from the front surface of the substrate including a groove, and etching the unobstructed field oxide portion using the photoresist pattern. It is characterized by.

The etching of the field oxide layer may be performed using an etching process using a selectivity ratio between the silicon substrate and the field oxide layer.

 The etching of the field oxide layer may be performed so as to remain at a depth of 1000 to 2000 microns from the depth of the entire field oxide layer.

The etching of the field oxide layer may be performed such that the etched field oxide layer is disposed 200 to 500 mm lower than the bottom of the groove.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4A through 4D are cross-sectional views illustrating processes for manufacturing a saddle fin transistor according to the present invention.

4A is a cross-sectional view taken along the line X-X 'of FIG. 3A, FIG. 4B is a cross-sectional view taken along the line Y-Y' of FIG. 3B, and FIG. 4C is a cross-sectional view taken along the line Z-Z 'of FIG. 3B. 4D is a cross sectional view along the line Y-Y ′ of FIG. 3C.

Referring to FIG. 4A, after the semiconductor substrate 10 having the active region protrudes is provided, the field oxide layer 20 is formed on the region other than the active region of the substrate at the same height as the substrate active region. Here, the field oxide film 20 is formed to a depth of 2500 to 3500∼. Then, a first photoresist pattern 30 is formed on the substrate resultant on which the field oxide film 20 is formed to expose the gate predetermined region. Next, a portion of the gate predetermined region of the exposed substrate active region is etched to form the groove 40.

4B and 4C, after the first photoresist pattern is removed, a second photoresist pattern (not shown) covering a portion of the active region protruding from the front surface of the substrate including the groove 40 is formed. By using the second photoresist pattern, the unetched field oxide portion 20 is etched so as to remain at a depth of 1000 to 2000 microns at the depth of the entire field oxide layer to expose the upper end of the etched gate region. Allow the sides of the exposed top to be rounded. The rounded side of the exposed upper end is referred to as a saddle. In addition, the etched field oxide layer 20 is formed such that the portion of the etched field oxide layer 200 to 500 Å lower than the bottom surface of the groove 40.

On the other hand, the etching of the field oxide film 20 is an etching process using the selectivity of the silicon substrate and the field oxide film so that the first photoresist pattern is removed, so as to remain at a depth of 1000 ~ 2000Å from the depth of the entire field oxide film The upper end of the etched gate planar region is exposed to be exposed, and the side surface of the exposed upper end is rounded. In addition, the etched field oxide layer 20 is formed such that the portion of the etched field oxide layer 200 to 500 Å lower than the bottom surface of the groove 40.

Here, the present invention does not perform the etching process of the field oxide film 20 for exposing the protruding active region by using the same photoresist pattern as the photoresist pattern 30 for forming the groove 40, and the gate is to be formed. The entire portion of the field oxide film except for the region is etched, or the etching process using the selectivity between the silicon substrate and the field oxide film without the photoresist pattern is performed.

As a result, grooves are not formed in the field oxide film portion where the gate is to be formed, thereby preventing over-etching of the field oxide film portion in the conventional cleaning process, so that a bridge between the gate and the subsequent landing plug contact occurs. Problems can be prevented.

Referring to FIG. 4D, a gate insulating film (not shown), a polysilicon film 50a, a tungsten silicide film 50b, and a hard mask film 50c are formed on the entire surface of the substrate including the etched field oxide film 20. After deposition in order, these are etched to form a gate 50.

Thereafter, although not shown, a subsequent series of known processes are subsequently carried out to manufacture the saddle-proof transistor according to the present invention.

Hereinbefore, the present invention has been illustrated and described with reference to specific preferred embodiments, but the present invention is not limited thereto, and it does not depart from the spirit or the field of the present invention provided by the following claims. It will be readily apparent to those skilled in the art that the present invention may be modified and changed in various ways.

As described above, according to the present invention, the field oxide layer portion on which the gate is to be formed is etched without using the photoresist pattern, or the field oxide layer portion is etched using the photoresist pattern covering only the protruding active region portion. It is possible to prevent overetching of the portion of the field oxide film in which the gate is to be formed.

As a result, a phenomenon in which a bridge is generated between the gate and the landing plug contact can be prevented, thereby improving the excellent current driving capability and the refresh characteristic.

As a result, according to the present invention, as the degree of integration of the device is increased, it is possible to secure an improved process yield compared to the existing process, thereby contributing to productivity improvement.

Claims (6)

Providing a semiconductor substrate on which an active region protrudes; Forming a field oxide film on a region other than the active region of the substrate at the same height as the substrate active region; Forming a photoresist pattern on the substrate resultant on which the field oxide film is formed to expose a gate predetermined region; Etching a portion of the gate predetermined region of the exposed substrate active region to form a groove; Removing the photoresist pattern; Etching the field oxide layer to expose the upper end portion of the etched gate predetermined region and to round the side surface of the exposed upper end portion; And Forming a gate material on an entire surface of the substrate including the etched field oxide film; Transistor manufacturing method comprising a. The method of claim 1, Forming the field oxide layer is performed at a depth of 2500 to 3500 Å. The method of claim 1, Etching the field oxide film, Forming a photoresist pattern covering a portion of the active region protruding from the front surface of the substrate including the groove; And etching a portion of the field oxide layer that is not covered by using the photoresist pattern. The method of claim 1, And etching the field oxide layer using an etching process using a selectivity ratio between a silicon substrate and a field oxide layer. The method of claim 1,  The etching of the field oxide film may be performed such that the depth of the field oxide film is maintained at a depth of 1000 to 2000 Å. The method of claim 1, The etching of the field oxide layer may be performed such that the etched field oxide portion is disposed 200 to 500 Å below the bottom of the groove.

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