KR20070066418A - Manufacturing method for floating gate of eeprom - Google Patents

Manufacturing method for floating gate of eeprom Download PDF

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KR20070066418A
KR20070066418A KR1020050127559A KR20050127559A KR20070066418A KR 20070066418 A KR20070066418 A KR 20070066418A KR 1020050127559 A KR1020050127559 A KR 1020050127559A KR 20050127559 A KR20050127559 A KR 20050127559A KR 20070066418 A KR20070066418 A KR 20070066418A
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nitride film
enhanced nitride
plasma
floating gate
polysilicon
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Korean (ko)
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문정훈
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매그나칩 반도체 유한회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02247—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by nitridation, e.g. nitridation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02252—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by plasma treatment, e.g. plasma oxidation of the substrate

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  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Plasma & Fusion (AREA)
  • Ceramic Engineering (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

A method for fabricating a floating gate of an EEPROM is provided to prevent a linear defect from being generated by forming a floating gate while using a thinner hard mask. Polysilicon(2) is deposited on a substrate(1), and a buffer oxide layer(3) is deposited on the polysilicon. A plasma enhanced nitride layer(4) is deposited on the resultant structure having a thickness of 1000 A or more . A photoresist pattern is formed on a part of the upper surface of the plasma enhanced nitride layer, a part of the plasma enhanced nitride layer selectively exposed by the photoresist pattern is etched, and the buffer oxide layer exposed by the etching of the plasma enhanced nitride layer is etched. The photoresist pattern is removed, and the exposed polysilicon is patterned by an etch process using the plasma enhanced nitride layer as a hard mask.

Description

이이피롬의 플로팅 게이트 제조방법{Manufacturing method for floating gate of EEPROM}Manufacturing method for floating gate of EEPROM}

도 1a 내지 도 1e는 본 발명의 일실시예에 따른 이이피롬의 플로팅 게이트 제조방법을 설명하기 위한 공정별 단면도.1A to 1E are cross-sectional views illustrating processes for manufacturing a floating gate of Y. pyrom according to an embodiment of the present invention.

*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

1:기판 2:폴리실리콘1: Substrate 2: Polysilicon

3:버퍼산화막 4:플라즈마 강화 질화막3: Buffer Oxide 4: Plasma Reinforced Nitride

본 발명은 이이피롬의 플로팅 게이트 제조방법에 관한 것으로, 특히 하드마스크를 단순화하여 이이피롬의 특성을 개선할 수 있는 이이피롬의 플로팅 게이트 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a floating gate of ypyrom, and more particularly, to a method for manufacturing a floating gate of ypyrom which can improve the properties of ypyrom by simplifying a hard mask.

일반적으로, 이이피롬(Electrically Erasable and Programmable Read Only Memory, 이하 EEPROM)은 전기적으로 지우고 쓰기가 가능한 플로팅 게이트(Floating gate)와 콘트롤 게이트(Control gate)를 가지는 불휘발성 메모리이다.In general, an electrically erasable and programmable read only memory (EEPROM) is a nonvolatile memory having a floating gate and a control gate that are electrically erasable and writeable.

플로팅 게이트를 제조하는 공정에서 필름의 적층구조는 산화막/질화막/버퍼산화막/다결정실리콘/터널산화막 또는 질화막/버퍼산화막/다결정실리콘/터널산화막이 적층된 구조를 가진다. 이와 같은 플로팅 게이트 제조공정은 두꺼운 하드 마스크를 사용하는 특징이 있다.In the process of manufacturing the floating gate, the film lamination structure has a structure in which an oxide film / nitride film / buffer oxide film / polycrystalline silicon / tunnel oxide film or a nitride film / buffer oxide film / polycrystalline silicon / tunnel oxide film is laminated. Such a floating gate manufacturing process is characterized by using a thick hard mask.

이와 같이 구조가 복잡하고, 하드마스크의 두께까지 두꺼운 경우, 하드 마스크의 식각공정에서 포토레지스트의 마진이 부족하여, 선형결함(striation)이 발생할 수 있으며, 스트레스의 증가로 인해 소자의 특성이 열화된다.When the structure is complicated and the thickness of the hard mask is thick, the photoresist margin is insufficient in the etching process of the hard mask, so that linear defects may occur and the stress of the device deteriorates the characteristics of the device. .

이러한 사항을 개선하기 위한 종래 플로팅 게이트 제조방법은 하드마스크의 구조를 단순화하기 위하여, 산화막, 질화막, 산화막이 순차 적층되는 하드마스크에서 질화막 또는 산화막을 생략하려는 노력이 있었으나, 질화막을 생략하는 경우 새부리(bird's beak)이 발생하는 문제점이 있으며, 상층의 산화막을 생략하는 경우 공정의 제어가 쉬워질 수 있으나 신장 스트레스(tensile stress)가 유발되어 채널 내의 이동도가 변화하여 소자의 특성이 변경되는 문제점이 있었다.The conventional floating gate manufacturing method for improving such a problem has been made to omit the nitride film or the oxide film from the hard mask in which the oxide film, the nitride film, and the oxide film are sequentially stacked in order to simplify the structure of the hard mask. bird's beak occurs, and if the oxide layer in the upper layer is omitted, the process can be easily controlled, but there is a problem that the characteristics of the device are changed due to the change of mobility in the channel due to elongation stress. .

상기와 같은 문제점을 감안한 본 발명은 하드마스크를 보다 단순화하여 선형결함의 발생을 방지하면서도, 스트레스를 유발하지 않는 이이피롬의 플로팅 게이트 제조방법을 제공함에 그 목적이 있다.In view of the above problems, an object of the present invention is to provide a method of manufacturing a floating gate of Y. pyrom that simplifies the hard mask to prevent the occurrence of linear defects and does not cause stress.

상기와 같은 목적은 달성하기 위한 본 발명은 a) 기판에 폴리실리콘을 증착하고, 그 폴리실리콘의 상부에 버퍼산화막을 증착하는 단계와, b) 상기 a) 단계의 결과물 상부전면에 플라즈마 강화 질화막을 증착하는 단계와, c) 상기 플라즈마 강화 질화막의 상부일부에 포토레지스트 패턴을 형성하고, 그 포토레지스트 패턴에 의해 선택적으로 노출된 플라즈마 강화 질화막의 일부를 식각하고, 그 플라즈마 강화 질화막의 식각으로 노출된 버퍼산화막을 식각하는 단계와, d) 상기 포토레지스트 패턴을 제거하고, 상기 플라즈마 강화 질화막을 하드마스크로 사용하는 식각공정으로 노출된 폴리실리콘을 패터닝하는 단계를 포함한다.The present invention for achieving the above object is a) depositing polysilicon on the substrate, the step of depositing a buffer oxide film on top of the polysilicon, and b) a plasma-enhanced nitride film on the upper surface of the resulting product C) forming a photoresist pattern on the upper portion of the plasma-enhanced nitride film, etching a portion of the plasma-enhanced nitride film selectively exposed by the photoresist pattern, and etching the plasma-enhanced nitride film. Etching the buffer oxide film; and d) removing the photoresist pattern and patterning the exposed polysilicon by an etching process using the plasma-enhanced nitride film as a hard mask.

이하 상기와 같이 구성된 본 발명의 바람직한 실시예를 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, described in detail with reference to the accompanying drawings a preferred embodiment of the present invention configured as described above.

도 1a 내지 도 1e는 본 발명의 일실시예에 따른 이이피롬의 플로팅 게이트 제조방법을 설명하기 위한 공정별 단면도이다.1A to 1E are cross-sectional views illustrating processes for manufacturing a floating gate of Y. pyrom according to an embodiment of the present invention.

이를 참조하면, 기판(1)의 상부에 다결정실리콘층(2)을 증착하고, 그 다결정실리콘층(2)의 상부전면에 버퍼산화막(3)을 증착한 후, 그 버퍼산화막(3)의 상부전면에 플라즈마 강화 질화막(plasma enhanced nitride, 4)를 형성하는 단계(도 1a)와, 상기 플라즈마 강화 질화막(4)의 상부 일부에 포토레지스트(PR) 패턴을 형성하는 단계(도 1b)와, 상기 포토레지스트(PR) 패턴을 식각마스크로 하여 노출된 플라즈마 강화 질화막(4)을 식각하고, 그 하부에 노출되는 버퍼산화막(3)을 식각하여 하드마스크를 형성하는 단계(도 1c)와, 상기 포토레지스트(PR) 패턴을 제거하여 상기 플라즈마 강화 질화막(4)의 상부면을 노출시키는 단계(도 1d)와, 상기 노출된 플라즈마 강화 질화막(4)을 식각의 하드마스크로 사용하여 노출된 폴리실리콘(2)을 식각하여 플로팅게이트를 형성하는 단계(도 1e)를 포함한다.Referring to this, the polysilicon layer 2 is deposited on the substrate 1, the buffer oxide film 3 is deposited on the top surface of the polysilicon layer 2, and then the top of the buffer oxide film 3 is deposited. Forming a plasma enhanced nitride film 4 on the entire surface (FIG. 1A), forming a photoresist (PR) pattern on an upper portion of the plasma enhanced nitride film 4 (FIG. 1B), and Etching the exposed plasma-enhanced nitride film 4 using the photoresist (PR) pattern as an etch mask, and etching the buffer oxide film 3 exposed below to form a hard mask (FIG. 1C), and the photo Exposing the upper surface of the plasma-enhanced nitride film 4 by removing the resist (PR) pattern (FIG. 1D), and using the exposed plasma-enhanced nitride film 4 as an etching hard mask. 2) etching to form a floating gate (Fig. 1e).

이하, 상기와 같이 구성되는 본 발명에 따른 EEPROM의 플로팅 게이트 제조방법을 보다 상세히 설명한다.Hereinafter, a method of manufacturing a floating gate of an EEPROM according to the present invention configured as described above will be described in more detail.

먼저, 도 1a에 도시한 바와 같이 기판(1)의 상부에 플로팅 게이트로 사용할 폴리실리콘(2)을 형성한다.First, as shown in FIG. 1A, polysilicon 2 to be used as a floating gate is formed on the substrate 1.

그 다음, 상기 폴리실리콘(2)의 상부에 버퍼산화막(3)을 증착하고, 그 버퍼산화막(3)의 상부에 플라즈마 강화 질화막(4)을 증착한다.Next, a buffer oxide film 3 is deposited on the polysilicon 2, and a plasma enhanced nitride film 4 is deposited on the buffer oxide film 3.

상기 플라즈마 강화 질화막(4)의 두께는 1000Å 이상이 되도록 증착하며, 증착과정에서 스트레스의 유발을 최소화할 수 있도록 전력을 조절하면서 증착한다.The thickness of the plasma-enhanced nitride film 4 is deposited to be 1000 Å or more, and is deposited while controlling the power to minimize the generation of stress in the deposition process.

그 다음, 도 1b에 도시한 바와 같이 상기 플라즈마 강화 질화막(4)의 상부전면에 포토레지스트(PR)를 도포하고, 노광 및 현상하여 상기 플라즈마 강화 질화막(4)의 상부일부에 위치하는 포토레지스트(PR) 패턴을 형성한다.Next, as shown in FIG. 1B, a photoresist PR is coated on the upper surface of the plasma enhanced nitride film 4, and the photoresist positioned on an upper portion of the plasma enhanced nitride film 4 by exposure and development. PR) to form a pattern.

그 다음, 도 1c에 도시한 바와 같이 상기 포토레지스트(PR) 패턴을 식각마스크로 하여 노출된 플라즈마 강화 질화막(4)을 식각한다.Next, as shown in FIG. 1C, the exposed plasma enhanced nitride film 4 is etched using the photoresist PR pattern as an etching mask.

그 다음, 플라즈마 강화 질화막(4)의 식각으로 인해 노출되는 버퍼산화막(3)을 식각하여 하드마스크를 형성한다.Next, the buffer oxide film 3 exposed by the etching of the plasma-enhanced nitride film 4 is etched to form a hard mask.

그 다음, 도 1d에 도시한 바와 같이 상기 포토레지스트(PR) 패턴을 제거하여 상기 플라즈마 강화 질화막(4)의 상부면을 노출시킨다.Next, as shown in FIG. 1D, the photoresist (PR) pattern is removed to expose the top surface of the plasma enhanced nitride film 4.

그 다음, 도 1e에 도시한 바와 같이, 상기 노출된 플라즈마 강화 질화막(4) 을 식각의 하드마스크로 사용하여 노출된 폴리실리콘(2)을 식각하여 플로팅게이트를 형성한다.1E, the exposed polysilicon 2 is etched using the exposed plasma-enhanced nitride film 4 as an etching hard mask to form a floating gate.

이상에서는 본 발명을 특정의 바람직한 실시 예들을 들어 도시하고 설명하였으나, 본 발명은 상기한 실시 예들에 한정되지 않으며 본 발명의 개념을 벗어나지 않는 범위 내에서 당해 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에 의해 다양한 변경과 수정이 가능하다.The present invention has been shown and described with reference to certain preferred embodiments, but the present invention is not limited to the above-described embodiments and has ordinary skill in the art to which the present invention pertains without departing from the concept of the present invention. Various changes and modifications are possible by the user.

상기한 바와 같이 본 발명에 의한 이이피롬의 플로팅 게이트 제조방법은 보다 얇은 두께의 하드마스크를 이용하여 플로팅 게이트를 형성함으로써 선형결함의 발생을 방지하는 효과가 있으며, 플라즈마 강화 질화막을 하드마스크로 사용하여 하드마스크에 의한 스트레스 발생을 방지하여 소자의 특성열화를 방지하는 효과가 있다.As described above, the method for manufacturing a floating gate of Y. pyrom according to the present invention has an effect of preventing the occurrence of linear defects by forming a floating gate using a thinner hard mask, and using a plasma-enhanced nitride film as a hard mask. It is effective to prevent the deterioration of the characteristics of the device by preventing the stress caused by the hard mask.

Claims (2)

a) 기판에 폴리실리콘을 증착하고, 그 폴리실리콘의 상부에 버퍼산화막을 증착하는 단계;a) depositing polysilicon on a substrate, and depositing a buffer oxide film on top of the polysilicon; b) 상기 a) 단계의 결과물 상부전면에 플라즈마 강화 질화막을 증착하는 단계;b) depositing a plasma-enhanced nitride film on the entire upper surface of the resultant of step a); c) 상기 플라즈마 강화 질화막의 상부일부에 포토레지스트 패턴을 형성하고, 그 포토레지스트 패턴에 의해 선택적으로 노출된 플라즈마 강화 질화막의 일부를 식각하고, 그 플라즈마 강화 질화막의 식각으로 노출된 버퍼산화막을 식각하는 단계; 및c) forming a photoresist pattern on an upper portion of the plasma enhanced nitride film, etching a portion of the plasma enhanced nitride film selectively exposed by the photoresist pattern, and etching the exposed buffer oxide film by etching the plasma enhanced nitride film step; And d) 상기 포토레지스트 패턴을 제거하고, 상기 플라즈마 강화 질화막을 하드마스크로 사용하는 식각공정으로 노출된 폴리실리콘을 패터닝하는 단계를 포함하는 이이피롬의 플로팅 게이트 제조방법.d) removing the photoresist pattern and patterning polysilicon exposed by an etching process using the plasma-enhanced nitride film as a hard mask. 제1항에 있어서,The method of claim 1, 상기 b) 단계에서 플라즈마 강화 질화막은 1000Å 이상의 두께로 증착하는 것을 특징으로 하는 이이피롬의 플로팅 게이트 제조방법.Plasma-enhanced nitride film in the step b) is characterized in that to deposit a thickness of 1000 Å or more floating gate manufacturing method of ypyrom.
KR1020050127559A 2005-12-22 2005-12-22 Manufacturing method for floating gate of eeprom KR20070066418A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100827541B1 (en) * 2007-06-28 2008-05-06 주식회사 하이닉스반도체 Method of forming a semiconductor memory device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100827541B1 (en) * 2007-06-28 2008-05-06 주식회사 하이닉스반도체 Method of forming a semiconductor memory device

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