KR20070064917A - Thin film transistor array substrate and manufacturing method of the same - Google Patents

Abstract

A thin film transistor array substrate and a method for manufacturing the same are provided to suppress the leakage current generated in a semiconductor pattern due to backlight, by forming the semiconductor pattern to have a smaller line width than a source/drain pattern including a data line, a source electrode, and a drain electrode. A gate pattern includes a gate line(102) formed on a substrate and a gate electrode(108) connected to the gate line. A source/drain pattern includes a data line(104) crossing the gate line with a gate insulating layer interposed therebetween, a source electrode(110) connected to the data line, and a drain electrode(112) facing the source electrode. A semiconductor pattern(114) is positioned below the source/drain pattern. A line width of the semiconductor pattern is equal to or smaller than a line width of the source/drain pattern. A pixel electrode(118) is electrically connected to a portion of the drain electrode. A passivation layer is formed on the resultant substrate except the pixel electrode.

Description

Thin Film Transistor Array Substrate and Method for Manufacturing the Same {THIN FILM TRANSISTOR ARRAY SUBSTRATE AND MANUFACTURING METHOD OF THE SAME}

1 is a plan view showing a portion of a conventional thin film transistor array substrate.

FIG. 2 is a cross-sectional view of the thin film transistor array substrate of FIG. 1 taken along the line II ′. FIG.

3A to 3D are flowcharts sequentially illustrating a second mask process of the thin film transistor array substrate illustrated in FIG. 2.

4 is a cross-sectional view specifically showing a conventional data line and a semiconductor pattern.

5 is a plan view illustrating a thin film transistor array substrate according to an embodiment of the present invention.

FIG. 6 is a cross-sectional view taken along line II-II ′ of the thin film transistor array substrate of FIG. 5.

7A and 7D are flowcharts sequentially illustrating a method of manufacturing a thin film transistor array substrate, according to an embodiment of the present invention.

8A to 8D are flowcharts illustrating the fourth mask process of the present invention in detail.

9 is a cross-sectional view illustrating a thin film transistor array substrate according to still another embodiment of the present invention.

         <Explanation of symbols for the main parts of the drawings>

2, 102: gate line 4, 104: data line

6, 106 thin film transistor 8, 108 gate electrode

10, 110: source electrode 12, 112: drain electrode

14, 114: active layer 16: contact hole

18, 118: pixel electrodes 20, 120: storage capacitor

42, 142: lower substrate 44,144: gate insulating film

47, 147: ohmic contact layer 14,114: active layer

48,148 semiconductor pattern 50,150 protective film

55,155 photoresist pattern

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a thin film transistor array substrate capable of improving aperture ratio and display quality, and a method of manufacturing the same.

Conventional liquid crystal display devices display an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix, and a driving circuit for driving the liquid crystal panel.

The liquid crystal panel includes a thin film transistor array substrate and a color filter array substrate facing each other, a spacer positioned to maintain a constant cell gap between the two substrates, and a liquid crystal filled in the cell gap.

The thin film transistor array substrate includes a gate line and a data line, a thin film transistor formed of a switch element at each intersection of the gate lines and the data lines, a pixel electrode formed of a liquid crystal cell and connected to the thin film transistor, and the like. It consists of the applied alignment film. The gate lines and the data lines receive signals from the driving circuits through the respective pad parts. The thin film transistor supplies the pixel voltage signal supplied to the data line to the pixel electrode in response to the scan signal supplied to the gate line.

The color filter array substrate includes color filters formed in units of liquid crystal cells, a black matrix for distinguishing between color filters and reflecting external light, a common electrode for supplying a reference voltage to the liquid crystal cells in common, and an alignment layer applied thereon. It consists of.

The liquid crystal display panel is completed by separately manufacturing a thin film transistor array substrate and a color filter array substrate, and then injecting and encapsulating a liquid crystal.

1 is a plan view illustrating a conventional thin film transistor array substrate, and FIG. 2 is a cross-sectional view of the thin film transistor array substrate illustrated in FIG. 1 taken along the line II ′.

The thin film transistor array substrate shown in FIGS. 1 and 2 includes a gate line 2 and a data line 4 intersecting each other with a gate insulating film 44 interposed on the lower substrate 42, and a thin film formed at each intersection thereof. The transistor 6 and the pixel electrode 18 formed in the cell area provided in the cross structure are provided. The thin film transistor array substrate includes a storage capacitor 20 formed at an overlapping portion of the pixel electrode 18 and the front gate line 2.

The thin film transistor 6 includes a gate electrode 8 connected to the gate line 2, a source electrode 10 connected to the data line 4, and a drain electrode 12 connected to the pixel electrode 16. And an active layer 14 overlapping the gate electrode 8 and forming a channel between the source electrode 10 and the drain electrode 12. The active layer 14 is formed to overlap the data line 4, the source electrode 10, and the drain electrode 12, and further includes a channel portion between the source electrode 10 and the drain electrode 12. An ohmic contact layer 47 for ohmic contact with the data line 4, the source electrode 10, and the drain electrode 12 is further formed on the active layer 14. Here, the active layer 14 and the ohmic contact layer 47 are referred to as a semiconductor pattern 48.

The thin film transistor 6 causes the pixel voltage signal supplied to the data line 4 to be charged and held in the pixel electrode 18 in response to the gate signal supplied to the gate line 2.

The pixel electrode 18 is connected to the drain electrode 12 of the thin film transistor 6 through a contact hole 16 penetrating through the passivation layer 50. The pixel electrode 18 generates a potential difference from the common electrode formed on the upper substrate (not shown) by the charged pixel voltage. This potential difference causes the liquid crystal located between the thin film transistor substrate and the upper substrate to rotate by dielectric anisotropy, and transmits light incident through the pixel electrode 18 from the light source (not shown) toward the upper substrate.

The gate line 2 is electrically connected to the gate driver (not shown) to receive a gate voltage from the gate driver (not shown), and the data line 4 is electrically connected to the data driver (not shown) to provide a gate voltage from the gate driver. The data voltage (or pixel voltage) is supplied.

The manufacturing method of the thin film transistor substrate which has such a structure is formed by a 4 mask process. If this is outlined as follows.

First, in the first mask process, a gate pattern including the gate line 2 and the gate electrode 8 is formed. In the second mask process, a source / drain pattern including the semiconductor pattern 48, the source electrode 10, the drain electrode 12, and the data line 4 and the thin film transistor 6 are formed. In the third mask process, the passivation layer 50 having the contact hole 16 exposing the drain electrode 12 of the thin film transistor 6 is formed. In the fourth mask process, the pixel electrode 18 contacting the drain electrode 12 through the contact hole 16 is formed.

In the conventional thin film transistor array substrate, since the end of the source / drain pattern is partially etched in the ashing process of the second mask process, the line width of the semiconductor pattern 48 is wider than that of the source / drain pattern.

This will be described in detail with reference to FIGS. 3A to 3D sequentially illustrating the second mask process.

First, a gate insulating film 44, an amorphous silicon layer 14a, and an n + amorphous silicon layer are deposited on a lower substrate on which a gate pattern such as a gate electrode 8 and a gate line (not shown) are formed through a deposition method such as PECVD or sputtering. 47a and the source / drain metal layer 10a are sequentially formed. 3A, a photoresist pattern 55a having a step may be formed on the source / drain metal layer 10a by a photolithography process using a second mask. In this case, the photoresist pattern 55a of the channel portion has a lower height than the other source / drain pattern portions by using a diffraction exposure mask having a diffraction exposure portion in the channel portion of the thin film transistor 6 as the second mask.

Subsequently, the source / drain metal layer 10a is patterned by a wet etching process using the photoresist pattern 55a, so that the data line 4, the source electrode 10, and the source electrode 10 and the source electrode 10 are patterned as shown in FIG. Source / drain patterns are formed that include the integrated drain electrode 12.

Next, the amorphous silicon layer 14a and the n + amorphous silicon layer 47a are simultaneously patterned by a dry etching process using the same photoresist pattern 55a, thereby forming a semiconductor pattern including the ohmic contact layer 47 and the active layer 14 ( 47) is formed.

As a result of the ashing process, the photoresist pattern 55a having a relatively low height is partially removed from the channel part to expose the source / drain metal corresponding to the channel part as shown in FIG. 3C. The resist pattern 55b remains.

Here, the ashing gas used is O ₂ And SF ₆ Ashing gas with a ratio of about 20: 1 is used. However, when the ashing gas is used to ash the photoresist pattern 55a, not only the thickness of the photoresist pattern 55a but also an end of the photoresist pattern 55a is partially removed. Accordingly, the photoresist pattern 55b after the ashing process is completed exposes the end A of the source / drain metal layer. Thereafter, the source / drain pattern of the channel portion exposed by the photoresist pattern 55b remaining in the dry etching process and the ohmic contact layer 47 are etched to expose the active layer 14 to expose the source electrode 10 and the drain electrode ( 12) is separated. Here, as the channel portion is formed, the end A of the source / drain metal layer is also etched so that the line width of the semiconductor pattern 148 includes the data line 104 as shown in FIGS. 1 and 2. It is formed wider than the line width.

Subsequently, the photoresist pattern 55b remaining on the source / drain pattern part is removed by a stripping process, so that the source / drain pattern and the source / drain including the data line 4, the source electrode 10, and the drain electrode 12 are removed. A semiconductor pattern 48 is formed below the pattern and has a line width wider than that of the source / drain pattern.

Here, as the line width of the semiconductor pattern 48 under the source / drain pattern is formed to be wider than the line width of the source / drain pattern, in particular, the semiconductor pattern 48 under the data line 4 is the data line 104. As shown in FIG. 4, the semiconductor pattern 48 has an ohmic contact region P1 contacting the data line 4 and a non-contact contact region P2 not contacting the data line 4 as shown in FIG. 4. ). Here, the ohmic contact region P1 in the semiconductor pattern 48 comes into contact with the source / drain metal and the non-ohmic contact region P2 does not come in contact with the source / drain metal, thereby making ohmic contact in the semiconductor pattern 48. The active state of the current between the region P1 and the non-ohmic contact region P2 is different. That is, the non-contact contact region P2 that is not in contact with the source / drain metal in the semiconductor pattern 48 is not in direct contact with the source / drain metal when exposed to backlight light, thereby generating abnormal leakage currents. As described above, the abnormal leakage current is a current that cannot be controlled by the user and is very unstable and distorts the pixel voltage charged in the adjacent pixel electrode 18, thereby degrading display quality.

In addition, as the end A of the source / drain metal layer described above is removed, the line width of the data line 4 or the like is formed to be smaller than the designed line width of the designer, thereby causing a problem in that the data voltage is not normally supplied. To prevent this, the designer designs the initial design to be about 2% larger in consideration of the reduction in the line width of the data line 4 in the ashing process. However, in this case, when the line width of the data line 4 is widened, in the four mask structure, the semiconductor pattern 48 is inevitably formed at the bottom of the data line 4 so that the semiconductor pattern (located below the data line 4) 48) It also becomes wide. As a result, there arises a problem that the total aperture ratio is lowered.

Accordingly, an object of the present invention is to provide a thin film transistor array substrate and a method of manufacturing the same, which can improve the aperture ratio and display quality.

In order to achieve the above object, the thin film transistor array substrate according to the present invention comprises a gate pattern including a gate line formed on the substrate, the gate electrode in contact with the gate line; A source / drain pattern including a data line crossing the gate line with a gate insulating layer interposed therebetween, a source electrode connected to the data line, and a drain electrode facing the source electrode; A semiconductor pattern positioned below the source / drain pattern and having a line width equal to or less than that of the source / drain pattern; A pixel electrode formed to partially overlap the drain electrode; A protective film formed in an area except the pixel electrode.

The semiconductor pattern is covered by the source / drain pattern.

And a storage capacitor provided by the gate line and the pixel electrode with the gate insulating layer interposed therebetween.

A method of manufacturing a thin film transistor array substrate according to the present invention includes forming a gate pattern including a gate electrode of a thin film transistor and a gate line connected to the gate electrode on a substrate by a first mask process; Forming a gate insulating film on the gate pattern; Forming a semiconductor pattern partially overlapping the gate electrode with the gate insulating layer interposed therebetween by using a second mask process; Forming a source / drain pattern including a data line crossing the gate line, a source electrode connected to the data line, and a drain electrode facing the source electrode by a third mask process; Forming a pixel electrode on which the portion of the drain electrode extends by using a fourth mask process and forming a passivation layer on a region other than the pixel electrode, wherein the semiconductor pattern is formed of the source / drain Characterized in that the line width is less than or equal to the line width of the pattern.

The source / drain pattern is formed to cover the semiconductor pattern.

The forming of the pixel electrode and the passivation layer may include forming a transparent electrode material on the substrate on which the source / drain pattern is formed; Forming a photoresist pattern on a region where the pixel electrode is to be formed on the transparent electrode material; Forming a pixel electrode by removing a transparent electrode material which is not overlapped with the photoresist pattern; Forming an insulating material on an entire surface of the lower substrate on which the photoresist pattern is formed; And removing the photoresist pattern by the strip process and simultaneously removing an insulating material overlapping the photoresist pattern, thereby forming a protective layer that is not overlapped with the pixel electrode.

      Other objects and advantages of the present invention in addition to the above object will be apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 5 to 9.

5 is a plan view of a thin film transistor array substrate according to an exemplary embodiment of the present invention, and FIG. 6 is a cross-sectional view of the thin film transistor array substrate illustrated in FIG. 5 taken along a line II-II '.

The thin film transistor array substrate illustrated in FIGS. 5 and 6 includes a gate line 102 and a data line 104 formed to intersect on the lower substrate 142 with a gate insulating layer 144 interposed therebetween, and a thin film formed at each intersection thereof. The transistor 106, the pixel electrode 118 formed in the cell region provided in the intersection structure, the storage capacitor 120, and the pixel electrode 118 formed at the overlapping portion of the pixel electrode 118 and the front gate line 102. A protective film 150 formed in the region except for the.

The pixel electrode 118 is formed to span the drain electrode 112 of the thin film transistor 106 without a separate contact hole. As a result, the contact area between the drain electrode 112 and the pixel electrode 118 becomes wider than in the related art.

The passivation layer 150 is not overlapped with the pixel electrode 118 and is formed on the entire area except the pixel electrode 118 to protect the thin film transistor 106, the data line 104, and the like.

The gate line 102 is electrically connected to the gate driver (not shown) to receive a gate voltage from the gate driver (not shown), and the data line 104 is electrically connected to the data driver (not shown) to provide a gate voltage from the gate driver. The data voltage (or pixel voltage) is supplied.

The storage capacitor 120 is provided by the pixel electrode 118 overlapping the front gate line 102 and the gate insulating layer 144 therebetween. Here, the pixel electrode 118 and the passivation layer 150 are non-overlapping so that the passivation layer 150 is not positioned inside the storage capacitor 120.

The thin film transistor 106 includes a gate electrode 108 connected to the gate line 102, a source electrode 110 connected to the data line 104, and a drain electrode 112 connected to the pixel electrode 118. And an active layer 114 overlapping the gate electrode 108 and forming a channel between the source electrode 110 and the drain electrode 112. The active layer 114 is formed to overlap the data line 104, the source electrode 110, and the drain electrode 112, and further includes a channel portion between the source electrode 110 and the drain electrode 112. An ohmic contact layer 147 for ohmic contact with the data line 104, the source electrode 110, and the drain electrode 112 is further formed on the active layer 114.

Here, the semiconductor pattern 148 including the active layer 114 and the ohmic contact layer 147 has the same line width as the line width of the source / drain pattern including the data line 104, the source electrode 110, and the drain electrode 112. Will have Accordingly, as shown in FIG. 4, in the semiconductor pattern 48, the non-ohmic contact region P2 not directly contacting the source / drain pattern does not appear. As a result, an abnormal leakage current does not occur conventionally, and the pixel voltage to the pixel electrode 118 is also not distorted, thereby preventing display quality from being lowered.

In other words, in the present invention, the line width of the semiconductor pattern 148 is formed to have the same line width as the source / drain pattern of the data line 104 or the like so that the entire surface of the semiconductor pattern 148 is in ohmic contact with the source / drain pattern. Accordingly, leakage current generated in the semiconductor pattern 148 by the backlight light can be stabilized by the source / drain pattern. As a result, the pixel voltage charged in the pixel electrode 118 adjacent to the data line 104 is not distorted and normal current can flow through the data line. As a result, the display electrode is prevented from deteriorating display quality such that the pixel electrode 118 is normally charged with the pixel voltage so that the conventional pixel distortion does not appear.

In addition, since the semiconductor pattern 148 and the source / drain pattern in the present invention are formed through a photolithography process using a separate mask, a conventional ashing process is not required. Therefore, the end of the source / drain pattern is not partially exposed in the conventional ashing process. As a result, even if the process of exposing the active layer 114 by removing the ohmic contact layer 148 of the channel region is performed, the end of the source / drain pattern is not reduced. Accordingly, in view of the reduction in the line width of the data line 104, it is not necessary to form the line width of the data line 104 in a wide manner, thereby reducing the opening ratio.

In addition, the pixel electrode 118 in the present invention is formed to be non-overlapping with the passivation layer 150 so as to extend directly over the drain electrode 112 without a separate contact hole. As a result, contact reliability between the pixel electrode 118 and the drain electrode 112 is improved.

The thin film transistor array substrate having such a structure can be formed by a patterning process using four masks by employing a lift off process.

Hereinafter, a method of manufacturing the TFT array substrate according to the present invention will be described in detail with reference to FIGS. 7A to 8D.

First, a gate metal layer is formed on the lower substrate 142 through a deposition method such as a sputtering method. Subsequently, the gate metal layer is patterned by a photolithography process and an etching process using a first mask to form gate patterns including a gate line (see FIG. 5) and a gate electrode 108 as illustrated in FIG. 7A. As the gate metal, chromium (Cr), molybdenum (Mo), aluminum-based metal, etc. are used in a single layer or a double layer structure.

First, the gate insulating layer 144, the amorphous silicon layer 114a, and n + are deposited on the lower substrate 142 on which the gate patterns such as the gate electrode 108 and the gate line (not shown) are formed through a deposition method such as PECVD or sputtering. After the amorphous silicon layer 147a is sequentially deposited and patterned by a photolithography process and an etching process using a second mask, as illustrated in FIG. 7B, the semiconductor pattern 148 and the data line of the thin film transistor 106 are formed. A semiconductor pattern 148 is formed below the 104. Here, the semiconductor pattern 148 to be positioned below the data line 104 may not be formed as necessary. Here, the semiconductor pattern 148 includes an active layer 114 and an ohmic contact layer 147.

After the source / drain metal layer is formed on the lower substrate 142 on which the semiconductor pattern 148 is formed through a deposition method such as PECVD or sputtering, the data line 104 is patterned by a photolithography process and an etching process using a third mask. ), A source / drain pattern including a source electrode 110 connected to the data line 104 and a drain electrode 112 facing the source electrode 110 is formed, and the source electrode 110 and the drain electrode 112 are formed. The ohmic contact layer 147 between the () is removed to expose the active layer 114 of the channel portion.

Here, the source / drain pattern has the same line width as the semiconductor pattern 148 formed under the source / drain pattern.

That is, conventionally, the source / drain pattern and the semiconductor pattern 148 are formed by a patterning process using one mask, thereby using a photoresist pattern having a step using a diffraction exposure mask. As a result, the ashing process is inevitably carried out, thereby causing a problem in that the line width of the source / drain pattern is reduced.

However, in the present invention, since the semiconductor pattern 148 and the source / drain pattern are each formed by a process using a separate mask, the ashing process is not performed. As a result, the line width of the source / drain pattern is not smaller than the line width of the semiconductor pattern 148. In addition, since the source / drain pattern is formed by an independent process separate from the semiconductor pattern 148, the source / drain pattern may be designed regardless of the line width of the semiconductor pattern 148. Accordingly, the line width of the source / drain pattern may be equal to or larger than the line width of the semiconductor pattern 148.

Molybdenum (Mo), titanium, tantalum, molybdenum alloy (Mo alloy), etc. are used as a source / drain metal.

Thereafter, the passivation layer 150 and the pixel electrode 118 are simultaneously patterned by a photolithography process and an etching process using a fourth mask including a lift-off process, thereby partially disposing the drain electrode 112 as illustrated in FIG. 7D. The spreading pixel electrode 118 and the passivation layer 150 positioned in the region excluding the pixel electrode 118 are formed.

Hereinafter, a patterning process using a fourth mask including a lift-off process will be described in detail with reference to FIGS. 8A to 8D.

First, the transparent electrode material 118a is entirely deposited on the lower substrate 142 on which the source / drain patterns are formed by a deposition method such as sputtering.

After the photoresist is applied, a photolithography process including an exposure and development process is performed to form a photoresist (PR) pattern 155 as shown in FIG. 8A. Here, the photoresist (PR) pattern 155 is formed in the region where the pixel electrode 118 is to be formed.

By performing a patterning process (etching process) using the photoresist pattern 155 as a mask, the transparent electrode material 118a not overlapped with the photoresist pattern 155 is removed. As a result, as illustrated in FIG. 8B, the pixel electrode 118 in contact with the drain electrode 112 is formed.

The insulating material 150a for forming the passivation layer 150 is formed on the lower substrate 142 on which the photoresist pattern 155 and the like are formed through a deposition method such as PECVD or sputtering. Thereafter, a lift-off process is performed in which the photoresist pattern 155 is removed using a stripper, and at the same time, the insulating material 150a formed on the photoresist pattern 155 is also removed. As a result, as shown in FIG. 8D, the passivation layer 150 is formed in the region excluding the pixel electrode 118 while forming a boundary with the pixel electrode 118.

As the material of the insulating material 150a, an inorganic insulating material such as the gate insulating film 144 or an organic insulating material such as an acryl-based organic compound having a low dielectric constant, BCB, or PFCB is used, and the transparent electrode material 118a is used. Indium tin oxide (ITO), tin oxide (TO) or indium zinc oxide (IZO) is used as the furnace.

5 to 8D have described the case where the line width of the semiconductor pattern and the line width of the source / drain pattern are the same.

However, since the semiconductor pattern 148 may be formed through a mask process separate from the source / drain pattern, as shown in FIG. 9, the semiconductor pattern 148 may be formed to have a small line width, and the source / drain pattern may be a semiconductor pattern. 148 may be formed to cover. In addition, a separate semiconductor pattern 148 may not be formed on the data line 104.

Such a method of manufacturing the thin film transistor array substrate illustrated in FIG. 9 may be formed by the same method as the method of FIGS. 7A to 8D described above.

As described above, the thin film transistor array substrate according to the present invention may prevent the display quality and the aperture ratio from being lowered by forming the semiconductor pattern 148 smaller than or equal to the line width of the source / drain pattern. In addition, the pixel electrode 118 is formed to span the drain electrode 112, thereby increasing the contact area between the pixel electrode 118 and the drain electrode 112. Accordingly, the contact reliability between the drain electrode 112 and the pixel electrode 118 can be improved.

Furthermore, the manufacturing process of the above-described thin film transistor array substrate of the present invention includes a lift-off process so that it can be formed by a conventional fourth mask process, so that no additional cost is required.

As described above, in the method of manufacturing the thin film transistor array substrate according to the present invention, the line width of the semiconductor pattern is formed to be equal to or smaller than the line width of the source / drain pattern such as the data line. As a result, the leakage current generated in the semiconductor pattern by the backlight light can be stabilized by the source / drain metal. As a result, the pixel voltage charged in the pixel electrode adjacent to the data line is not distorted, thereby preventing display quality deterioration.

In addition, the present invention eliminates the need for an ashing process, thereby eliminating the need to form a wide source / drain pattern in consideration of the source / drain line width reduced by the conventional ashing process. As a result, the total aperture ratio can be improved as compared with the conventional art.

Finally, the pixel electrode is formed to be non-overlapping with the passivation layer so as to directly extend to the drain electrode without a separate contact hole, thereby increasing the contact area between the drain electrode and the pixel electrode. As a result, the contact reliability between the pixel electrode and the drain electrode is improved.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (6)

A gate pattern including a gate line formed on the substrate and a gate electrode in contact with the gate line; A source / drain pattern including a data line crossing the gate line with a gate insulating layer interposed therebetween, a source electrode connected to the data line, and a drain electrode facing the source electrode; A semiconductor pattern positioned below the source / drain pattern and having a line width equal to or less than that of the source / drain pattern; A pixel electrode formed to partially overlap the drain electrode; And a passivation film formed in a region excluding the pixel electrode. The method of claim 1, And the semiconductor pattern is covered by the source / drain pattern. The method of claim 1, And a storage capacitor provided by the gate line and the pixel electrode with the gate insulating layer interposed therebetween. Forming a gate pattern including a gate electrode of a thin film transistor and a gate line connected to the gate electrode on a substrate by a first mask process; Forming a gate insulating film on the gate pattern; Forming a semiconductor pattern partially overlapping the gate electrode with the gate insulating layer interposed therebetween by using a second mask process; Forming a source / drain pattern including a data line crossing the gate line, a source electrode connected to the data line, and a drain electrode facing the source electrode by a third mask process; Forming a pixel electrode on which the portion of the drain electrode extends by using a fourth mask process and forming a protective film positioned in a region other than the pixel electrode; And the semiconductor pattern is formed to have a line width less than or equal to the line width of the source / drain pattern. The method of claim 4, wherein The source / drain pattern may be formed to cover the semiconductor pattern. The method of claim 4, wherein Forming the pixel electrode and the passivation layer Forming a transparent electrode material on the substrate on which the source / drain pattern is formed; Forming a photoresist pattern on a region where the pixel electrode is to be formed on the transparent electrode material; Forming a pixel electrode by removing a transparent electrode material which is not overlapped with the photoresist pattern; Forming an insulating material on an entire surface of the lower substrate on which the photoresist pattern is formed; And removing the photoresist pattern by the strip process and simultaneously removing an insulating material overlapping the photoresist pattern to form a passivation layer non-overlapping with the pixel electrode. Way.

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