KR101200883B1 - Manufacturing method of thin film transistor array substrate - Google Patents

Abstract

The present invention relates to a method of manufacturing a thin film transistor array substrate capable of preventing degradation of display quality.

A method of manufacturing a thin film transistor array substrate according to an embodiment of the present invention includes forming a gate pattern including a gate line and a gate electrode connected to the gate line on a substrate by a first mask process; Forming a gate insulating film on the gate pattern; Forming a source / drain pattern including a data line crossing the gate line, a source electrode connected to the data line, and a drain electrode facing the source electrode by a second mask process; Forming a semiconductor pattern positioned and having a line width smaller than the source / drain pattern; Forming a protective film having a contact hole partially exposing the drain electrode by a third mask process; And forming a pixel electrode contacting the drain electrode through the contact hole using a fourth mask process.

Description

The manufacturing method of a thin film transistor array board | substrate {MANUFACTURING METHOD OF THIN FILM TRANSISTOR ARRAY SUBSTRATE}

1 is a plan view showing a portion of a conventional thin film transistor array substrate.

FIG. 2 is a cross-sectional view of the thin film transistor array substrate shown in FIG. 1 taken along the line I-I '; FIG.

3A to 3D are flowcharts sequentially illustrating a second mask process of the thin film transistor array substrate illustrated in FIG. 2.

4 is a cross-sectional view specifically showing a conventional data line and a semiconductor pattern.

5 is a plan view illustrating a thin film transistor array substrate according to an embodiment of the present invention.

FIG. 6 is a cross-sectional view taken along line II-II ′ of the thin film transistor array substrate of FIG. 5.

7A and 7D are flowcharts sequentially illustrating a method of manufacturing a thin film transistor array substrate, according to an embodiment of the present invention.

8A to 8E are process charts specifically showing a second mask process of the present invention.

9 is a view for explaining a semiconductor pattern is partially etched by an etching gas containing F (fluorine).

         <Explanation of symbols for the main parts of the drawings>

2, 102: gate line 4, 104: data line

6, 106: thin film transistors 8, 108: gate electrode

10, 110: source electrode 12, 112: drain electrode

14, 114: active layer 16: contact hole

18, 118: pixel electrode 20, 120: storage capacitor

42, 142: lower substrate 44,144: gate insulating film

47, 147: ohmic contact layer 14,114: active layer

148: semiconductor pattern

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a method of manufacturing a thin film transistor array substrate capable of preventing degradation of display quality.

A conventional liquid crystal display device displays an image by adjusting the light transmittance of a liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix form, and a driving circuit for driving the liquid crystal panel.

The liquid crystal panel includes a thin film transistor array substrate and a color filter array substrate facing each other, a spacer positioned to maintain a constant cell gap between the two substrates, and a liquid crystal filled in the cell gap.

The thin film transistor array substrate includes gate lines and data lines, a thin film transistor formed as a switching element for each intersection of the gate lines and the data lines, a pixel electrode formed in a unit of a liquid crystal cell and connected to the thin film transistor, And an applied alignment film. The gate lines and the data lines are supplied with signals from the driving circuits through respective pad portions. The thin film transistor supplies a pixel voltage signal supplied to the data line in response to a scan signal supplied to the gate line.

The color filter array substrate includes color filters formed in units of liquid crystal cells, a black matrix for distinguishing between color filters and reflecting external light, a common electrode for supplying a reference voltage to the liquid crystal cells in common, and an alignment layer applied thereon. It consists of.

The liquid crystal panel is completed by separately manufacturing a thin film transistor array substrate and a color filter array substrate, and then injecting and encapsulating a liquid crystal.

1 is a plan view illustrating a conventional thin film transistor array substrate, and FIG. 2 is a cross-sectional view of the thin film transistor array substrate illustrated in FIG. 1 taken along the line II ′.

The thin film transistor array substrate shown in FIGS. 1 and 2 includes a gate line 2 and a data line 4 intersecting each other with a gate insulating film 44 interposed on the lower substrate 42, and a thin film formed at each intersection thereof. The transistor 6 and the pixel electrode 18 formed in the cell area provided in the cross structure are provided. The thin film transistor array substrate includes a storage capacitor 20 formed at an overlapping portion of the pixel electrode 18 and the front gate line 2.

The thin film transistor 6 includes a gate electrode 8 connected to the gate line 2, a source electrode 10 connected to the data line 4, a drain electrode 12 connected to the pixel electrode 16, And an active layer 14 superimposed on the gate electrode 8 and forming a channel between the source electrode 10 and the drain electrode 12. The active layer 14 is formed to overlap the data line 4, the source electrode 10, and the drain electrode 12, and further includes a channel portion between the source electrode 10 and the drain electrode 12. An ohmic contact layer 47 for ohmic contact with the data line 4, the source electrode 10, and the drain electrode 12 is further formed on the active layer 14. Here, the active layer 14 and the ohmic contact layer 47 are referred to as a semiconductor pattern 48.

The thin film transistor 6 causes the pixel voltage signal supplied to the data line 4 to be charged and held in the pixel electrode 18 in response to the gate signal supplied to the gate line 2.

The pixel electrode 18 is connected to the drain electrode 12 of the thin film transistor 6 through a contact hole 16 penetrating through the passivation layer 50. The pixel electrode 18 generates a potential difference with the common electrode formed on the upper substrate (not shown) by the charged pixel voltage. This potential difference causes the liquid crystal located between the thin film transistor substrate and the upper substrate to rotate by dielectric anisotropy, and transmits light incident through the pixel electrode 18 from the light source (not shown) toward the upper substrate.

The gate line 2 is electrically connected to the gate driver (not shown) to receive a gate voltage from the gate driver (not shown), and the data line 4 is electrically connected to the data driver (not shown) to provide a gate voltage from the gate driver. The data voltage (or pixel voltage) is supplied.

A method of manufacturing a thin film transistor substrate having such a configuration is formed by a four mask process. If this is outlined as follows.

First, in the first mask process, a gate pattern including the gate line 2 and the gate electrode 8 is formed. In the second mask process, a source / drain pattern including the semiconductor pattern 48, the source electrode 10, the drain electrode 112, and the data line 104 and the thin film transistor 6 are formed. In the third mask process, the passivation layer 50 having the contact hole 16 exposing the drain electrode 12 of the thin film transistor 6 is formed. In the fourth mask process, the pixel electrode 18 contacting the drain electrode 12 through the contact hole 16 is formed.

In the conventional thin film transistor array substrate, since the end of the source / drain pattern is partially etched in the ashing process of the second mask process, the line width of the semiconductor pattern 48 is wider than that of the source / drain pattern.

This will be described in detail with reference to FIGS. 3A to 3D sequentially illustrating the second mask process.

First, a gate insulating film 44, an amorphous silicon layer 14a, and an n + amorphous silicon layer are deposited on a lower substrate on which a gate pattern such as a gate electrode 8 and a gate line (not shown) are formed through a deposition method such as PECVD or sputtering. 47a and the source / drain metal layer 10a are sequentially formed. 3A, a photoresist pattern 55a having a step may be formed on the source / drain metal layer 10a by a photolithography process using a second mask. In this case, the photoresist pattern 55a of the channel portion has a lower height than the other source / drain pattern portions by using a diffraction exposure mask having a diffraction exposure portion in the channel portion of the thin film transistor 6 as the second mask.

Subsequently, the source / drain metal layer 10a is patterned by a wet etching process using the photoresist pattern 55a, so that the data line 4, the source electrode 10, and the source electrode 10 and the source electrode 10 are patterned as shown in FIG. Source / drain patterns are formed that include the integrated drain electrode 12.

Next, the amorphous silicon layer 14a and the n + amorphous silicon layer 47a are simultaneously patterned by a dry etching process using the same photoresist pattern 55a, thereby forming a semiconductor pattern including the ohmic contact layer 47 and the active layer 14 ( 47) is formed.

As a result of the ashing process, the photoresist pattern 55a having a relatively low height is partially removed from the channel part to expose the source / drain metal corresponding to the channel part as shown in FIG. 3C. The resist pattern 55b remains.

Here, the ashing gas used is O ₂ And SF ₆ Ashing gas with a ratio of about 20: 1 is used. However, when the ashing gas is used to ash the photoresist pattern 55a, not only the photoresist pattern 55a but also the end A of the source / drain metal layer under the photoresist pattern 55a is partially removed. do. That is, since the source / drain metal layer reacts with ashing gas in part, the thickness of the photoresist pattern 55a is lowered and the end of the source / drain metal layer is partially exposed while the end of the photoresist pattern 55a is partially removed. A) will also be removed. Accordingly, as shown in FIGS. 1 and 2, the line width of the semiconductor pattern 148 is wider than that of the source / drain pattern including the data line 104.

Thereafter, the source / drain pattern of the channel portion exposed by the photoresist pattern 55b remaining in the dry etching process and the ohmic contact layer 47 are etched to expose the active layer 14 to expose the source electrode 10 and the drain electrode ( 12) is separated. Subsequently, the photoresist pattern 55b remaining on the source / drain pattern part is removed by a stripping process, so that the source / drain pattern and the source / drain including the data line 4, the source electrode 10, and the drain electrode 12 are removed. A semiconductor pattern 48 is formed below the pattern and has a line width wider than that of the source / drain pattern.

Here, as the line width of the semiconductor pattern 48 under the source / drain pattern is formed to be wider than the line width of the source / drain pattern, in particular, the semiconductor pattern 48 under the data line 4 is the data line 104. As shown in FIG. 4, the semiconductor pattern 48 has an ohmic contact area P1 contacting the data line 4 and a non-contact contact area P2 non-contacting the data line 4 as shown in FIG. 4. ). Here, the ohmic contact region P1 in the semiconductor pattern 48 is brought into contact with the source / drain metal, and the non-ohmic contact region P2 is not brought into contact with the source / drain metal. The active state of the current between the contact region P1 and the non-ohmic contact region P2 is different. That is, the non-contact contact region P2 that is not in contact with the source / drain metal in the semiconductor pattern 48 is not in direct contact with the source / drain metal when exposed to backlight light, thereby generating abnormal leakage currents. As described above, the abnormal leakage current is a current which cannot be controlled by the user and is very unstable and distorts the pixel voltage charged in the adjacent pixel electrode 18. As a result, when the pixel voltage also becomes unstable and implements an image, there arises a problem that a so-called wavy noise called wave noise appears.

Accordingly, it is an object of the present invention to provide a method for manufacturing a thin film transistor array substrate which can prevent the degradation of display quality.

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A method of manufacturing a thin film transistor array substrate according to an embodiment of the present invention includes forming a gate pattern including a gate line and a gate electrode connected to the gate line on a substrate by a first mask process; Forming a gate insulating film on the gate pattern; Forming a source / drain pattern including a data line crossing the gate line, a source electrode connected to the data line, and a drain electrode facing the source electrode by a second mask process; Forming a semiconductor pattern positioned and having a line width smaller than the source / drain pattern; Forming a protective film having a contact hole partially exposing the drain electrode by a third mask process; Forming a pixel electrode in contact with the drain electrode through the contact hole using a fourth mask process, and forming a source / drain pattern and a semiconductor pattern by the second mask process comprises: Sequentially forming a semiconductor layer and a source / drain metal layer on the insulating film; Forming a stepped photoresist pattern on the source / drain metal layer by a photolithography process, the region corresponding to the region where the channel is to be formed, having a relatively low height; Removing the semiconductor layer and the source / drain metal layer using the stepped photoresist pattern; O to ₂ than SF ₆ sheep using one of more of a mixed etching gas and O ₂ than CF ₄ both the etch gas mixture more of removing the end of the semiconductor pattern which is located in the source / drain metal layer lower portion Characterized in that it comprises a.

Forming the source / drain pattern and the semiconductor pattern by the second mask process may include partially removing the stepped photoresist to expose the source / drain metal layer corresponding to the region where the channel is to be formed by the ashing process. ; Patterning the exposed source / drain metal layer and the semiconductor pattern using the photoresist pattern remaining by the ashing process.

Removing the end of the semiconductor pattern is carried out under a pressure of 80 ~ 120mtorr.

O ₂ above And SF ₆ mixing ratio, the O ₂ And CF ₄ mixing ratio are 10 ~ 49%: 51 ~ 90%, respectively.

      Other objects and advantages of the present invention will become apparent from the following description of preferred embodiments of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 5 to 9.

5 is a plan view illustrating a thin film transistor array substrate according to an exemplary embodiment of the present invention, and FIG. 6 is a cross-sectional view of the thin film transistor array substrate illustrated in FIG. 5 taken along a line II-II ′.

The thin film transistor array substrate illustrated in FIGS. 5 and 6 includes a gate line 102 and a data line 104 formed to intersect on the lower substrate 142 with a gate insulating layer 144 interposed therebetween, and a thin film formed at each intersection thereof. The transistor 106 and the pixel electrode 118 formed in the cell region provided in the cross structure are provided. The thin film transistor array substrate includes a storage capacitor 120 formed at an overlapping portion of the pixel electrode 118 and the front gate line 102.

The pixel electrode 118 is connected to the drain electrode 112 of the thin film transistor 106 through the contact hole 116 penetrating the passivation layer 150.

The gate line 102 is electrically connected to the gate driver (not shown) to receive a gate voltage from the gate driver (not shown), and the data line 104 is electrically connected to the data driver (not shown) to provide a gate voltage from the gate driver. The data voltage (or pixel voltage) is supplied.

The thin film transistor 106 includes a gate electrode 108 connected to the gate line 102, a source electrode 110 connected to the data line 104, a drain electrode 112 connected to the pixel electrode 116, And an active layer 114 overlapped with the gate electrode 108 and forming a channel between the source electrode 110 and the drain electrode 112. The active layer 114 is formed to overlap the data line 104, the source electrode 110, and the drain electrode 112, and further includes a channel portion between the source electrode 110 and the drain electrode 112. An ohmic contact layer 147 for ohmic contact with the data line 104, the source electrode 110, and the drain electrode 112 is further formed on the active layer 114.

Here, the semiconductor pattern 148 including the active layer 114 and the ohmic contact layer 147 has a width smaller than the line width of the source / drain pattern including the data line 104, the source electrode 110, and the drain electrode 112. Is formed. Accordingly, as shown in FIG. 4, in the semiconductor pattern 48, the non-ohmic contact region P2 not directly contacting the source / drain pattern does not appear. As a result, an abnormal leakage current does not occur conventionally, and the pixel voltage to the pixel electrode 118 is also not distorted, thereby preventing display quality from being lowered.

In other words, in the present invention, the line width of the semiconductor pattern 148 is formed to be smaller than the source / drain pattern such as the data line 104 such that the entire surface of the semiconductor pattern 148 is in ohmic contact with the source / drain pattern. Accordingly, leakage current generated in the semiconductor pattern 148 by the backlight light can be stabilized by the source / drain pattern. As a result, the pixel voltage charged in the pixel electrode 118 adjacent to the data line 104 is not distorted and normal current can flow through the data line. As a result, the display quality is prevented from being deteriorated, such as no wavy irregularities such as wave noise due to pixel voltage distortion.

7A to 9 are views for explaining a method of manufacturing a thin film transistor array substrate according to the present invention.

First, a gate metal layer is formed on the lower substrate 142 through a deposition method such as a sputtering method. Subsequently, the gate metal layer is patterned by a photolithography process and an etching process using a first mask to form gate patterns including a gate line (see FIG. 5) and a gate electrode 108 as illustrated in FIG. 7A. As the gate metal, chromium (Cr), molybdenum (Mo), aluminum-based metal, etc. are used in a single layer or a double layer structure.

Subsequently, as shown in FIG. 7B, a source / drain pattern including the data line 104, the source electrode 110, and the drain electrode 112 is formed using the second mask process, and the source / drain pattern is formed. A semiconductor pattern 148 having a small line width is formed.

Here, the second mask process of the present invention will be described in detail with reference to FIGS. 8A to 8E.

First, the gate insulating layer 144, the amorphous silicon layer 114a, and n + are deposited on the lower substrate 142 on which the gate patterns such as the gate electrode 108 and the gate line (not shown) are formed through a deposition method such as PECVD or sputtering. The amorphous silicon layer 147a and the source / drain metal layer 110a are sequentially formed. Subsequently, as shown in FIG. 8A, a photoresist pattern 155a having a step is formed on the source / drain metal layer 110a by a photolithography process using a second mask. The use of a diffraction exposure mask having a diffraction exposure portion in the channel portion of 106 causes the photoresist pattern 155a of the channel portion to have a lower height than other source / drain pattern portions.

Subsequently, the source / drain metal layer 110a is patterned by a wet etching process using the photoresist pattern 155a so that the data line 104, the source electrode 110, and the drain electrode 112 integrated with the source electrode 110 are formed. Source / drain patterns including are formed.

Next, the amorphous silicon layer 114a and the n + amorphous silicon layer 147a are simultaneously patterned by a dry etching process using the same photoresist pattern, thereby forming the ohmic contact layer 147 and the active layer 114 as shown in FIG. 8B. A semiconductor pattern 147 is formed.

Since, O ₂ Than SF ₆ Only the semiconductor pattern 148 exposed to the outside is selectively etched using this more added etching gas. That is, as shown in FIG. 8C, the end C of the semiconductor pattern 148 exposed to the outside is exposed by the etching gas, so that the end C of the exposed semiconductor pattern 148 is partially etched.

This phenomenon can be explained by the photograph shown in FIG. The semiconductor pattern 148 includes SF ₆ containing fluorine (F). SF _{6 due} to its high reactivity to etching gases such as and CF ₄ . When the etching process is performed using an etching gas such as CF ₄ , an undercut phenomenon appears below the photoresist pattern PR as shown in FIG. 9. Will be partially etched.

Since the selective etching enables the etching of only the end B of the semiconductor pattern 148 using the etching gas, the semiconductor pattern 148 having a line width smaller than that of the source / drain pattern as illustrated in FIG. 8C may be formed. Will be.

Here, the etching gas used for the selective etching of the semiconductor pattern is O ₂ More amounts of SF ₆ (or CF ₄ ) are mixed than. More preferably, the amount of O ₂ added is about 10 to 49% of the total composition, and the amount of SF ₆ (or CF ₄ ) is about 51 to 90% of the total composition. In addition, the etching process is carried out under a pressure of 80 ~ 120mtorr.

Subsequently, an ashing process is performed to partially remove the photoresist pattern 155a having a relatively low height from the channel portion, thereby leaving the photoresist pattern 155b exposing the source / drain metal corresponding to the channel portion. Done.

Here, the ashing gas used is O ₂ And SF ₆ Ashing gas with a ratio of about 20: 1 is used. When the ashing gas is used to ash the photoresist pattern 155a, not only the photoresist pattern 155a but also the end B of the source / drain metal layer under the photoresist pattern 155a may be partially removed.

That is, the ashing process of FIG. 8D is performed to alleviate the line width difference between the semiconductor pattern 148 and the source / drain pattern in FIG. 8C and to reduce the thickness to expose the channel region of the source / drain pattern. The photoresist pattern 155b remains. As a result of the ashing process, the semiconductor pattern 148 having a line width smaller than the line width of the source / drain pattern such as the data line 104 can be formed as in the region B of FIGS. 5 (plan view) and 8d. do.

Thereafter, the source / drain pattern of the channel portion exposed by the photoresist pattern 155b remaining in the dry etching process and the ohmic contact layer 147 are etched to expose the active layer 114 to expose the source electrode 110 and the drain electrode. 112 is separated. Accordingly, as shown in FIG. 8E, a source / drain pattern including the data line 104, the source electrode 110, and the drain electrode 112 is completed.

As a material of the gate insulating film 144, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used. As the source / drain metal, molybdenum (Mo), titanium, tantalum, molybdenum alloy (Mo alloy) and the like are used.

Referring to FIG. 7C, the passivation layer 150 including the contact hole 116 is formed on the gate insulating layer 144 on which the source / drain patterns are formed.

The passivation layer 150 is entirely formed on the gate insulating layer 144 on which the source / drain patterns are formed by a deposition method such as PECVD. The passivation layer 150 is patterned by a photolithography process and an etching process using a third mask to form a contact hole 116. The contact hole 116 penetrates the passivation layer 150 to expose the drain electrode 112.

As the material of the protective film 150, an inorganic insulating material such as the gate insulating film 144, an acryl based organic compound having a small dielectric constant, or an organic insulating material such as BCB or PFCB is used.

Referring to FIG. 7D, the pixel electrode 118 is formed on the passivation layer 150.

The transparent electrode material is completely deposited on the protective film 150 by a deposition method such as sputtering. Subsequently, the transparent electrode material is etched through the photolithography process and the etching process using the fourth mask, thereby forming the pixel electrode 118 contacting the drain electrode 112 through the contact hole 116. As the transparent electrode material, indium tin oxide (ITO), tin oxide (TO), or indium zinc oxide (IZO) is used.

As described above, in the method of manufacturing the thin film transistor array substrate according to the present invention, the line width of the semiconductor pattern is formed to be smaller than the source / drain pattern such as the data line, so that the entire surface of the semiconductor pattern is in ohmic contact with the source / drain metal. do. Accordingly, the leakage current generated in the semiconductor pattern by the backlight light can be stabilized by the source / drain metal. As a result, the pixel voltage charged in the pixel electrode adjacent to the data line is not distorted and normal current can flow through the data line. As a result, the display quality is prevented from being deteriorated, such as no wavy irregularities such as wave noise due to pixel voltage distortion.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims (10)

delete delete delete delete Forming a gate pattern including a gate line and a gate electrode connected to the gate line on a substrate by a first mask process; Forming a gate insulating film on the gate pattern; Forming a source / drain pattern including a data line crossing the gate line, a source electrode connected to the data line, and a drain electrode facing the source electrode by a second mask process; Forming a semiconductor pattern positioned and having a line width smaller than the source / drain pattern; Forming a protective film having a contact hole partially exposing the drain electrode by a third mask process; Forming a pixel electrode in contact with the drain electrode through the contact hole using a fourth mask process; Forming the source / drain pattern and the semiconductor pattern by the second mask process, Sequentially forming a semiconductor layer and a source / drain metal layer on the gate insulating film; Forming a stepped photoresist pattern on the source / drain metal layer by a photolithography process, the region corresponding to the region where the channel is to be formed, having a relatively low height; Removing the semiconductor layer and the source / drain metal layer using the stepped photoresist pattern; O to ₂ than SF ₆ sheep using one of more of a mixed etching gas and O ₂ than CF ₄ both the etch gas mixture more of removing the end of the semiconductor pattern which is located in the source / drain metal layer lower portion Method of manufacturing a thin film transistor array substrate comprising a. 6. The method of claim 5, Forming the source / drain pattern and the semiconductor pattern by the second mask process, Partially removing the stepped photoresist such that the source / drain metal layer corresponding to the region where the channel is to be formed is exposed by an ashing process; And patterning the exposed source / drain metal layer and the semiconductor pattern by using the photoresist pattern remaining by the ashing process. The method of claim 6, Removing the end of the semiconductor pattern A method of manufacturing a thin film transistor array substrate, characterized in that carried out under a pressure of 80 ~ 120mtorr. The method of claim 6, O ₂ above And SF ₆ mixing ratio, the O ₂ And CF ₄ mixing ratio is 10 to 49%: 51 to 90%, respectively. 6. The method of claim 5, And the semiconductor pattern is covered by the data line on a plane. 6. The method of claim 5, One surface of the semiconductor pattern is formed in contact with the data line in front of the thin film transistor array substrate manufacturing method.

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