KR20070058142A - Method for forming gate of flash memory device - Google Patents

Abstract

A gate forming method in a flash memory device is provided to minimize exposure of a tungsten film by forming a cap poly film on the tungsten film. A tunnel oxide film(104) and first and second polycrystalline silicon films(106,108) are formed on a semiconductor substrate(100). After a dielectric film(110) is formed on the second polycrystalline silicon film, the dielectric film is removed from a cell selection transistor region. A third polycrystalline silicon film(112), a first tungsten nitride film(114), a tungsten film(116), a second tungsten nitride film(118), a cap poly film(120), and a hard mask film(122) are formed on the substrate. A portion of the hard mask is etched to expose the cap poly film. The exposed cap poly film and other films are etched to expose the substrate.

Description

Method for forming gate of flash memory device

1 is a plan view showing a portion of a cell array region of a flash memory device according to the present invention.

2A to 2C are cross-sectional views of a semiconductor device illustrating a gate forming process of a flash memory device according to an exemplary embodiment of the present invention with the line A-A of FIG. 1 cut away.

3A to 3C are cross-sectional views of a semiconductor device illustrating a gate forming process of a flash memory device according to an exemplary embodiment of the present invention with the line B-B of FIG. 1 cut out.

4A to 4C are cross-sectional views of a semiconductor device illustrating a gate forming process of a flash memory device according to an exemplary embodiment of the present invention in a state in which line C-C of FIG. 1 is cut away.

<Description of Symbols for Main Parts of Drawings>

              100 semiconductor substrate 102 device isolation films

              104 tunnel oxide film 106 polysilicon film

              108: second polysilicon 110: dielectric film

              112: conductive layer for control gate 114: tungsten layer

              116: hard mask 118: cell or transistor

       120: void 122: cell open mask

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a gate of a flash memory device. In particular, a flash memory capable of preventing a tungsten attack by changing the structure of a tungsten gate electrode so that tungsten (W) is not exposed during a wafer cleaning process. It relates to a gate forming method of the device.

Flash memory devices are manufactured using the advantages of EPROM with programming and erasing characteristics and EEPROM with programming and erasing characteristics. . Such a flash memory device realizes a bit storage state as one transistor, and can be electrically programmed and erased.

Such flash memory cells generally have a vertically stacked gate structure having a floating gate formed on a silicon substrate. The multilayer gate structure typically includes one or more tunnel oxide or dielectric films and a control gate formed on or around the floating gate.

Hereinafter, a gate forming process of a conventional flash memory device will be briefly described.

A tunnel oxide film is formed to a certain thickness on the semiconductor substrate, and a conductive layer for floating gate is formed on the tunnel oxide film. A dielectric film is formed on the conductive layer for the floating gate, which is formed by sequentially stacking an oxide film, a nitride film, and an oxide film.

After the control gate conductive layer is formed over the dielectric film, the control gate conductive layer except for the cell region (source / drain select line formation region and peripheral circuit region) is removed using a dielectric open mask. Next, the dielectric film except for the cell region is removed through a wet etching process using BOE and H ₃ PO ₄ .

Subsequently, after forming a tungsten and gate hard mask on the entire structure and performing an etching process, the cell region is etched away from the dielectric film and the region except the cell region is etched to the conductive layer for the floating gate because the dielectric is already etched. This is going on.

Next, the area except the cell area is covered with a mask and the dielectric layer and the floating gate conductive layer remaining in the cell area are removed using a SAE (Self Aligned Etch) mask. As a result, a gate is formed.

However, metal tungsten (Metal W) is used as the gate electrode to reduce wordline sheet resistance in NAND flash devices of 70 nm or less, but metal tungsten is more oxidized than tungsten silicide (WSix) and is used in wet etching process. There is a vulnerable problem.

In particular, when oxide is used as a hard mask, oxide loss occurs when the wafer is cleaned in a solution containing HF after the hard mask etching process. Therefore, it should be cleaned with Sulfuric Acid-Peroxide Mixture (SPM) and Ammonium Hydroxide Peroxide Mixture (APM) instead of HF. There is a problem in that various defects, including the Whisker Type, are generated by contamination.

The present invention is to change the structure of the tungsten gate electrode, to deposit a cap poly film on top of the tungsten gate electrode to stop the etching process in the cap poly film during the subsequent oxide hard mask etching process, thereby minimizing the exposure of the tungsten film A method of forming a gate of a flash memory device capable of preventing contamination and tungsten film attack (W Attack) is provided.

A method of forming a gate of a flash memory device according to the present invention may include forming a conductive layer for a tunnel oxide film and a floating gate over an entire structure including a cell string region and a cell select transistor region of a semiconductor substrate on which an isolation layer is formed; Forming a dielectric film on the conductive layer for the floating gate, and then removing the dielectric film in the cell select transistor region; Sequentially forming a control gate conductive layer, a first tungsten nitride film, a tungsten film, a second tungsten nitride film, a cap poly film, and a hard mask film on the entire resultant product; Performing a first etching process of etching a portion of the hard mask layer to expose a cap poly layer; And sequentially etching the cap poly film, the second tungsten nitride film, the tungsten film, the first tungsten nitride film, the control film conductive film, the dielectric film in the cell string region and the floating gate conductive film in the exposed region to expose the semiconductor substrate. And performing a second etching process.

The cap poly film has a thickness of 300 to 500 kPa, and is formed using a low pressure plasma enhanced type (LP-Plasma Enhanced) method.

The cap poly film may be formed of SiON. By the first etching process, the cap poly film is lost to 100 to 200 mm 3.

After the first etching process, the method may further include performing a wafer cleaning process with an SPM and an APM solution.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view showing a portion of a cell array region of a flash memory device according to the present invention. 2A to 2C are cut lines AA of FIG. 1, and FIGS. 3A to 3C are cut lines BB of FIG. 1, and FIGS. 4A to 4C are cut lines CC of FIG. 1. A cross-sectional view of a semiconductor device illustrating a gate forming process of a flash memory device according to an exemplary embodiment of the inventive concept.

2A to 2C, 3A to 3C, and 4A to 4C are different from each other, but the processes are performed at the same time in the entire semiconductor process, and thus, the processes of FIGS. 2A to 2C and 3A to 3C. It demonstrates in connection with a process and a process of FIGS. 4A-4C.

1, 2A, 3A, and 4A, device isolation layers 102 defining a plurality of active regions parallel to each other are formed in a predetermined region of the semiconductor substrate 100.

Referring to the process of forming the device isolation layers 102, a pad oxide layer (not shown) is formed on the semiconductor substrate 100, and a nitride layer (not shown) is formed on the pad oxide layer (not shown). Next, a photosensitive film (not shown) is coated on the nitride film (not shown), and the photosensitive film is exposed and developed to form a trench, which is an isolation region, on the surface of the semiconductor substrate 100.

Next, after the photosensitive film pattern is formed by exposure and development of the photosensitive film, a nitride film (not shown) is patterned using the photosensitive film pattern as a mask. Using a patterned nitride film (not shown) as a hard mask (not shown), the pad oxide film and the semiconductor substrate are etched to have a predetermined depth and width to form a trench, which is a semiconductor device isolation region, and then fills the trench. (Gap Fill) process is performed.

Next, after planarization using a chemical mechanical polishing (CMP) process to the position where the nitride film is located, the nitride film (not shown) and the pad oxide film (not shown) are removed.

After the tunnel oxide film 104 is formed in the space where the nitride film and the pad oxide film are not removed, the first polysilicon film 106 is formed only in the active regions of the semiconductor device 100 using, for example, polysilicon. ), And a second polysilicon film 108 is formed on the first polysilicon film 106 so as to overlap a part of the device isolation film 102. The first polysilicon film 106 and the second polysilicon film 108 are used as floating gates.

The dielectric film 110 (in the case of the cell string region), the third polysilicon film 112, the first tungsten nitride film 114, the tungsten film 116, and the second tungsten nitride film (which are used as control gates) on the entire structure. 118), the cap poly film 120 and the hard mask film 122 are sequentially stacked.

At this time, the cap poly film 120 is deposited using a low pressure plasma enhanced type (LP-Plasma Enhanced) method with a thickness of 300 to 500 kPa, and 300 to 500 kPa thickness instead of the cap poly film 120, low pressure plasma SiON may also be deposited using an incremental approach. Therefore, the process related to the Cappolymembrane 120 below applies similarly to the case where the SiON is used. In addition, the hard mask film 122 is preferably an oxide hard mask (Oxide Hard Mask).

The first tungsten nitride film 114 prevents the third polysilicon film 112 from reacting with the tungsten film 116 to form tungsten silicide, and the second tungsten nitride film 118 is formed by the cap poly film 120 being tungsten. Reacts with the film 116 to prevent tungsten silicide from forming.

In the cell string region, the dielectric film 110 remains, but the region where the transistor is formed is formed so that the second polysilicon film 108 and the third polysilicon film 112 are electrically connected by removing the dielectric film 110. .

2B, 3B, and 4B are cross-sectional views of semiconductor devices having the following processes of FIGS. 2A, 3A, and 4A. Referring to FIGS. 2B, 3B, and 4B, after the photoresist pattern (not shown) is formed on the hard mask layer 122, the etching process is performed using the photoresist pattern (not shown) as a mask. When the loss of 120 is 100 to 200 mW, the etching process is stopped, and the photoresist pattern (not shown) is removed.

Next, a wafer cleaning process is performed with a solution of Sulfuric Acid-Peroxide Mixture (SPM) and Ammonium Hydroxide Peroxide Mixture (PMM).

2C, 3C, and 4C are cross-sectional views of semiconductor devices that have undergone the following processes of FIGS. 2B, 3B, and 4B. 2C, 3C, and 4C, the cap poly film 120, the second tungsten nitride film 118, the tungsten film 116, the first tungsten nitride film 114, the third polysilicon film 112, The dielectric film 110 (in the case of the cell string region) and the second polysilicon film 108 are sequentially etched. As a result, a control gate and a floating gate are formed in the cell string region, and a transistor gate is formed in the cell select transistor region.

Next, a drain / source region (not shown) is formed based on the floating gate electrode by an impurity ion implantation process.

As described above, according to the present invention, the structure of the tungsten gate electrode is changed, and the cappoly film 120 is deposited on the tungsten gate electrode, so that the cap poly film 120 is formed during the subsequent etching process of the oxide hard mask film 122. In order to minimize the exposure of tungsten by stopping the etching process, it is possible to prevent tungsten contamination and tungsten attack.

In addition, in the present invention, since tungsten is not exposed during the wafer cleaning process, the wafer cleaning process may be performed with the SPM and AP solution, and the oxide hard mask loss may be minimized.

Although the present invention has been described with reference to the embodiments illustrated in the drawings, this is merely exemplary and will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. .

Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

The present invention is to change the structure of the tungsten gate electrode, to deposit a cap poly film on top of the tungsten gate electrode to stop the etching process in the cap poly film during the subsequent oxide hard mask etching process, thereby minimizing the exposure of the tungsten film Contamination and tungsten film attack can be prevented.

In addition, in the present invention, since the tungsten film is not exposed during the wafer cleaning process, the wafer cleaning process may be performed with the SPM and AP solution, and the oxide hard mask loss may be minimized.

Claims (5)

Forming a tunnel oxide film, a first polysilicon film, and a second polysilicon film on the semiconductor substrate on which the device isolation film is formed; Forming a dielectric film over the second polysilicon film, and then removing the dielectric film in a cell select transistor region; Sequentially forming a third polysilicon film, a first tungsten nitride film, a tungsten film, a second tungsten nitride film, a cap poly film, and a hard mask film on the entire product; Performing a first etching process of etching a portion of the hard mask layer to expose a cap poly layer; And Sequentially exposing the semiconductor substrate by sequentially etching the cap poly film, the second tungsten nitride film, the tungsten film, the first tungsten nitride film, the third polysilicon film, the dielectric film in the cell string region, and the second polysilicon film in the exposed region. A method of forming a gate of a flash memory device comprising the step of performing an etching process. The method of claim 1, And a cap poly film having a thickness of about 300 to about 500 kPa, and formed using a low pressure plasma enhanced (LP-Plasma Enhanced) method. The method of claim 1, The cap poly film may be formed of SiON. The method of claim 1, The method of claim 1, wherein the cap poly film is lost by 100 to 200 microseconds by the first etching process. The method of claim 1, And performing a wafer cleaning process with an SPM and an APM solution after the first etching process.

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