KR20070054895A - Method of manufacturing a semiconductor device including a ferroelectric capacitor - Google Patents

Abstract

A method of manufacturing a semiconductor device including a ferroelectric capacitor having improved characteristics is disclosed. The insulating structure formed on the substrate is etched to form an opening that exposes the substrate. The titanium aluminum nitride film covering the upper surface of the insulating structure is formed while the opening is buried. A chemical mechanical polishing process is performed on the titanium aluminum nitride layer to expose the surface of the insulating structure to form a contact pad in the opening. A lower electrode layer is formed on the insulating structure and the contact pad and electrically connected to the contact pad. By forming a ferroelectric layer and an upper electrode layer on the lower electrode layer, a semiconductor device including a ferroelectric capacitor is completed. The above-described method can form a lower electrode layer and a ferroelectric layer having a substantially uniform thickness by forming a contact having a flat top surface made of titanium aluminum nitride.

Description

Method of manufacturing a semiconductor device including a ferroelectric capacitor

1 to 6 are cross-sectional views illustrating a method of manufacturing a semiconductor device including a ferroelectric capacitor according to Embodiment 1 of the present invention.

7 to 9 are cross-sectional views illustrating a method of manufacturing a semiconductor device including a ferroelectric capacitor according to a second embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

305: contact pad 310: barrier metal film

320: lower electrode layer 330: ferroelectric layer

340: upper electrode layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a semiconductor device including a ferroelectric capacitor having ferroelectric electrical characteristics, and a method of manufacturing the same.

Generally, a semiconductor memory device is classified into a volatile semiconductor memory device which loses stored data when power supply is interrupted and a nonvolatile semiconductor memory device which does not lose stored data even when power supply is interrupted. The volatile semiconductor memory device may include a dynamic random access memory (DRAM) device or a static random access memory (SRAM) device. The nonvolatile semiconductor memory device may be an erasable programmable read only memory (EPROM) device or an EEPROM (EEPROM). Electrically Erasable Programmable Read Only Memory) devices or flash memory devices have been developed.

In comparison, a ferroelectric random access memory (FRAM) device has both characteristics of a volatile RAM device capable of both reading and writing, and characteristics of a nonvolatile ROM device. In the FRAM device, the operating speed of the FRAM device is relatively lower than that of the DRAM device because the current manufacturing technology level is less than that of the DRAM device. However, the FRAM device has spontaneous polarization characteristics of the ferroelectric material even when the power supply is interrupted. Stored information has the characteristic of excellent information preservation that cannot be erased. In addition, the FRAM device can be driven at a lower power than the EPROM device or the EEPROM device, and has the advantage of significantly increasing the number of input / output of information.

For the manufacture of the FRAM device, the ferroelectrics developed are largely divided into two types. One is a ferroelectric of PZT [Pb (Zr, Ti) O ₃ ] series and the other is a ferroelectric of SBT (SrBi ₂ Ta ₂ O ₉ ) series. PZT-based ferroelectrics can be manufactured at relatively low temperatures of about 650 ° C and have the advantage of high residual polarization, making them the best material among ferroelectrics.

As the ferroelectric capacitor including the ferroelectric is highly integrated in a semiconductor device, the thickness of the lower electrode and the ferroelectric (PZT) layer to which the noble metal is applied should be reduced. Generally, a buried contact connected to the lower electrode of the ferroelectric capacitor in the FRAM is formed by forming a tungsten film by a chemical vapor deposition method and then performing a chemical mechanical polishing process.

The gap is exposed when the chemical mechanical polishing process is performed, and then the gap is exposed when the bottom electrode (BE), the ferroelectric layer, and the top electrode (TE) are sequentially formed. This results in a problem that the lower electrode layer and the ferroelectric layer formed do not have a uniform profile. Therefore, when the thickness of the lower electrode of the ferroelectric capacitor having the above-described structure is reduced, oxygen contained in the ferroelectric layer passes through the lower electrode and diffuses into the contact pad, thereby causing the contact pad to be oxidized.

Technical contents for solving this problem are disclosed in US Pat. No. 691250. However, the U.S. Patent has proposed a method of etching a tungsten contact and then depositing tungsten nitride to planarize the titanium nitride. Caused. Therefore, the lower electrode layer and the ferroelectric layer formed thereafter due to the above-described problems do not have a uniform thickness.

An object of the present invention for solving the above problems is to provide a method for manufacturing a semiconductor device comprising a ferroelectric capacitor having a flat top and having a contact pad made of titanium aluminum nitride.

In the method of manufacturing a semiconductor device according to an embodiment of the present invention for achieving the above object of the present invention, an insulating structure is formed on a substrate. The insulating structure is etched to form openings that expose the substrate. While the opening is buried, a titanium aluminum nitride (Ti _X Al ( _1-X ) N) film covering the top surface of the insulating structure is formed. A chemical mechanical polishing process is performed on the titanium aluminum nitride layer to expose the surface of the insulating structure to form a contact pad in the opening. A lower electrode layer is formed on the insulating structure and the contact pad and electrically connected to the contact pad. After forming a ferroelectric layer on the lower electrode layer, an upper electrode layer is formed on the ferroelectric layer. As a result, a semiconductor device including a ferroelectric capacitor is completed.

In the method of manufacturing a semiconductor device according to another embodiment of the present invention for achieving the above object of the present invention, after forming an insulating structure on a substrate to form an opening for exposing the substrate by etching the insulating structure. do. While the opening is buried, a titanium aluminum nitride (Ti _X Al ( _1-X ) N) film covering the top surface of the insulating structure is formed. A chemical mechanical polishing process is performed on the titanium aluminum nitride layer to form a titanium aluminum nitride contact pad having a flat top surface on the insulating structure and burying the opening. A lower electrode layer is formed on the contact pad. After forming a ferroelectric layer on the lower electrode layer, an upper electrode layer is formed on the ferroelectric layer. As a result, a semiconductor device including a ferroelectric capacitor is completed.

The ferroelectric capacitor formed by the method according to the present invention has a flat top and includes a contact pad made of titanium aluminum nitride having no gap therein, so that the lower electrode layer, the ferroelectric layer and the upper electrode layer formed thereafter are substantially uniform. Has a thickness. That is, when the thickness of the lower electrode layer and the upper electrode layer is reduced for high integration of the semiconductor device, oxygen contained in the ferroelectric layer may prevent the problem of oxidizing the contact pad.

In addition, lifting may be prevented between the ferroelectric layer, the lower electrode layer, and the contact pad due to the thermal stress of the subsequent process, thereby preventing the leakage current from the ferroelectric layer. That is, the electrical characteristics and the reliability of the semiconductor device including the ferroelectric capacitor can be sufficiently secured.

Hereinafter, a method of manufacturing a ferroelectric capacitor and a method of manufacturing a semiconductor device using the same according to preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, but the present invention is not limited to the following embodiments. However, one of ordinary skill in the art may realize the present invention in various other forms without departing from the technical spirit of the present invention. In the accompanying drawings, the dimensions of the substrates, layers (films), regions, pads, patterns or structures are shown to be larger than actual for clarity of the invention. In addition, in the accompanying drawings, the same or similar reference numerals are used for substantially the same or similar members. In the present invention, each layer (film), region, pad, pattern or structures is formed to be "on", "top" or "bottom" of the substrate, each layer (film), region, pad or patterns. When mentioned, each layer (film), region, pad, pattern or structure is meant to be directly formed over or below the substrate, each layer (film), region, pad or patterns, or other layers (film), Other regions, different pads, different patterns or other structures may be additionally formed on the substrate. In addition, when each layer (film), region, pad, pattern, structure or electrode is referred to as "first", "second" and / or "third", it is not intended to limit these members but only each layer. (Film), regions, pads, patterns, structures or electrodes for differentiation. Thus, "first", "second" and / or "third" may be used selectively or interchangeably for each layer (film), region, pad, pattern, structure or electrodes, respectively.

Example 1

1 to 6 are cross-sectional views illustrating a method of manufacturing a semiconductor device including a ferroelectric capacitor according to Embodiment 1 of the present invention.

1 is a cross-sectional view illustrating a method of forming a lower structure on a substrate.

Referring to FIG. 1, a lower structure is formed on a substrate 200. The lower structure may include the first and second impurity regions 235 and 240, the gate structure 230, the first pad 250, the second pad 255, and the bit line 270 formed in the substrate 200. Include.

In detail, the isolation trench 205 is formed on the semiconductor substrate 200 by performing a shallow trench isolation (STI) process to divide the substrate 200 into an active region and a field region.

Subsequently, a gate insulating film is formed on the substrate 200 on which the device isolation film 205 is formed by thermal oxidation, chemical vapor deposition, or atomic layer deposition. Here, the gate insulating film may be a silicon oxide film (SiO ₂ ), or may be a thin film made of a material having a higher dielectric constant than the silicon oxide film.

A first conductive film and a gate mask are sequentially formed on the gate insulating film. The first conductive layer is made of polysilicon doped with an impurity, and is then patterned into a gate electrode. Subsequently, the first conductive layer and the gate insulating layer are sequentially patterned using the gate mask as an etching mask. Accordingly, the substrate 200 is formed of gate structures 230 including a gate insulating layer pattern, a gate electrode, and a gate mask, respectively.

Subsequently, after the silicon nitride layer is formed on the substrate 200 on which the gate structures 230 are formed, the silicon nitride layer is anisotropically etched to form gate spacers 225 on both sidewalls of the gate structures 230.

After the impurity is implanted into the substrate 200 exposed between the gate structures 230 by using the gate structures 230 having the gate spacer 225 formed as an ion implantation mask, an annealing process is performed. As a result, the first impurity region 235 and the second impurity region 240 corresponding to the source / drain regions are formed in the substrate 200.

The first impurity region 235 is in contact with the first pad 250 for the capacitor, and the second impurity region 240 is in contact with the second pad 250 for the bit line. The first interlayer insulating layer 245 made of oxide is formed on the entire surface of the substrate 200 while covering the gate structures 230. The first interlayer insulating film 245 is formed of BPSG, PSG, SOG, PE-TEOS, USG, or HDP-CVD oxide.

Subsequently, the upper surface of the first interlayer insulating layer 245 is planarized by performing a chemical mechanical polishing process to remove the upper portion of the first interlayer insulating layer 245. In an exemplary embodiment, the first interlayer insulating layer 245 is formed to have a predetermined height from an upper surface of the gate mask 220.

Subsequently, after forming a second photoresist pattern (not shown) on the first interlayer insulating layer 245 on which the planarization process is performed, the first interlayer insulating layer 245 using the second photoresist pattern as an etching mask. Is partially anisotropically etched to form first contact holes (not shown) that penetrate the first interlayer insulating film 245 to expose the first and second impurity regions 235 and 240. The first contact holes self-align with the gate structures 230 to expose the first and second impurity regions 235 and 240. Subsequently, after the second photoresist pattern is removed through an ashing and / or strip process, a second conductive layer covering the first interlayer insulating layer 245 is formed while the first contact holes are buried. The second conductive layer may be formed using polysilicon, a metal, or a conductive metal nitride doped with a high concentration of impurities.

Next, a first self-aligned contact (SAC) pad provided in the first contact holes by performing a chemical mechanical polishing process or an etch back process until the upper surface of the first interlayer insulating layer 245 is exposed. The pad 250 and the second pad 255 are formed. Accordingly, the first pad 250 is in electrical contact with the capacitor contact region, and the second pad 255 is in electrical contact with the bit line contact region.

Subsequently, a second interlayer insulating layer 260 is formed on the first interlayer insulating layer 245 including the first and second pads 250 and 255. The second interlayer insulating layer 260 electrically insulates the subsequently formed bit line (not shown) from the first pad 250. Subsequently, a second contact hole is formed in the second interlayer insulating layer 260 to expose the second pad 255 embedded in the first interlayer insulating layer 260. The second contact hole corresponds to a bit line contact hole for electrically connecting the subsequently formed bit line and the second pad 255 to each other.

Subsequently, a bit line 270 is formed to be electrically connected to the second pad 255 through a second contact hole. Bit line 270 is generally comprised of a first layer of metal / metal compound and a second layer of metal.

2 is a cross-sectional view for describing a method of forming an insulating structure covering a lower structure.

Referring to FIG. 2, an insulating structure 300 covering the lower structure is formed. The insulating structure 300 may have a structure in which a single interlayer insulating layer or an interlayer insulating layer and an etch stop layer are stacked. In this case, the etch stop layer is formed to a thickness of about 10 ~ 200Å.

3 is a cross-sectional view for describing a method of forming a contact pad and a barrier metal film that bury an opening of an insulating structure.

Referring to FIG. 3, the insulating structure 300 is partially etched to form an opening (not shown) corresponding to the third contact hole exposing the first pad 250. Thereafter, the opening is buried, thereby forming a titanium aluminum nitride (Ti _X Al ( _{1 -X} ) N) film covering the top surface of the insulating structure. The titanium aluminum nitride film is formed by atomic layer deposition. The titanium aluminum nitride film preferably has X of 0.5 to 0.95 in Ti _X Al ( _1-X ) N, more preferably X = 0.8. Therefore, a third pad formed of the titanium aluminum nitride film is formed to have a specific resistance of about 1000 uPacm and a contact resistance of about 100 kPa to 7000 kPa.

Subsequently, a chemical mechanical polishing process is performed on the titanium aluminum nitride layer until the surface of the insulating structure is exposed to form a third pad 305 provided in the opening. That is, a contact pad 305 which is a third pad electrically connected to the first pad 250 through the insulating structure is formed. Thereafter, in order to remove the residue generated during the chemical mechanical polishing process, a cleaning process using plasma ashing and hydrofluoric acid solution is performed.

After forming the contact pad 305, which is preferably the third pad, a barrier metal film 310 having a substantially uniform thickness is further formed. The barrier metal layer 310 serves to reduce electrical resistance between the third pad and the lower electrode layer formed later. Examples of the material constituting the barrier metal film include titanium aluminum nitride, titanium, titanium nitride, titanium oxide and the like.

As another example, although not shown in the drawing, a spacer may be further formed before the titanium aluminum nitride (Ti _X Al ( _1-X ) N) layer is formed. In addition, the process of etching the upper portion of the spacer to further extend the inlet of the opening in which the spacer is formed.

4 is a cross-sectional view for describing a method of forming a lower electrode layer.

Referring to FIG. 4, a conductive material for forming a lower electrode is deposited on an insulating structure on which the barrier metal layer 310 is formed to have a substantially uniform thickness. As a result, the lower electrode layer 320 is formed on the barrier metal film.

5 is a cross-sectional view illustrating a method of forming a ferroelectric layer and an upper electrode layer.

Referring to FIG. 5, the ferroelectric layer 330 and the upper electrode layer 340 having a substantially uniform thickness are sequentially formed on the lower electrode layer 320. Specifically, the ferroelectric layer 330 is formed using an organometallic chemical vapor deposition (MOCVD) process, a sol-gel process, an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process. The ferroelectric layer 330 is formed using a ferroelectric such as PZT, SBT, BLT, PLZT or BST. In addition, the ferroelectric layer 330 is formed using PZT, SBT, BLT, PLZT or BST doped with calcium, lanthanum, manganese or bismuth. In addition, the ferroelectric layer 330 is formed using titanium oxide, tantalum oxide, aluminum oxide, zinc oxide or hafnium oxide. Preferably, the ferroelectric layer 330 is formed by depositing PZT on the lower electrode layer 320 by an organometallic chemical vapor deposition (MOCVD) process. In forming the ferroelectric layer 330, the reaction chamber in which the substrate 200 is accommodated is maintained at a temperature of about 350 to 650 ° C. and a pressure of about 1 to 10 Torr.

Next, an upper electrode layer 340 having a substantially uniform thickness is formed on the ferroelectric layer 330. The upper electrode is iridium, platinum, ruthenium, palladium, gold, platinum-manganese alloy, iridium-ruthenium alloy, iridium oxide, strontium ruthenium oxide (SRO), strontium titanium oxide (STO), lanthanum nickel oxide (LNO) or calcium ruthenium It is formed using an oxide (CRO) or the like.

Subsequently, the ferroelectric layer 330 and the upper electrode layer 340 are heat treated by a rapid heat treatment process (RTP) under an oxygen gas, nitrogen gas, or a mixed gas atmosphere to form the upper electrode layer 340 and the ferroelectric layer 330. Crystallize them. The rapid heat treatment process is performed for about 30 seconds to 3 minutes at a temperature of about 500 ~ 650 ℃.

6 is a cross-sectional view illustrating a method of forming an upper electrode, a ferroelectric pattern, and a lower electrode.

Referring to FIG. 6, after forming an etch mask on the upper electrode layer 340, the upper electrode 345, the ferroelectric layer 330, and the lower electrode exposed to the etch mask are sequentially etched to form the upper electrode 345. The ferroelectric pattern 335 and the lower electrode 325 are formed. As a result, a ferroelectric capacitor including the lower electrode 325, the ferroelectric pattern 335, and the upper electrode 345 is completed.

Example 2

7 to 9 are cross-sectional views illustrating a method of manufacturing a semiconductor device including a ferroelectric capacitor according to a second embodiment of the present invention.

Referring to FIG. 7, the insulating structure 300 covering the lower structure is partially etched to form an opening (not shown) corresponding to the third contact hole exposing the first pad 250. Detailed descriptions of the substructure and the insulating structure are disclosed in FIGS. 1 and 2 of the first embodiment and are omitted to avoid duplication. The reference numerals for the components of the substructure and the insulating structure are the same as those in the first embodiment.

Subsequently, after forming the spacer 402 on the side of the opening formed in the insulating structure, the process of etching the upper portion of the spacer to further expand the width of the inlet of the opening in which the spacer 402 is formed.

Subsequently, the titanium aluminum nitride (Ti _X Al ( _{1 -X} ) N) layer 405 covering the top surface of the insulating structure 300 is formed while the opening in which the spacer 402 is formed is buried. The titanium aluminum nitride film 405 is formed by atomic layer deposition, and has a thickness of about 1000 to 1500 mW from an upper surface of the insulating structure. The titanium aluminum nitride film 405 preferably has X of 0.5 to 0.95 in Ti _X Al ( _1-X ) N, more preferably X = 0.8. Since the titanium aluminum nitride film 405 is formed while the opening is buried, a recess having a depth of about 300 to 600 kPa is formed on the upper surface thereof.

Referring to FIG. 8, a chemical mechanical polishing process is performed on the titanium aluminum nitride film 405 to form a titanium aluminum nitride contact pad 410 having a flat upper surface on the insulating structure while the opening is buried. In other words, a contact pad 410 is formed through the insulating structure 300 and includes a pad 410a electrically connected to the first pad and a layer 410b having a flat upper surface on the insulating structure. Thereafter, in order to remove the residue generated during the chemical mechanical polishing process, a cleaning process using plasma ashing and hydrofluoric acid solution is performed.

Referring to FIG. 9, lower electrode layers, ferroelectric layers, and upper electrode layers are sequentially formed on the contact pads. Thereafter, the exposed upper electrode layer, the ferroelectric layer, and the lower electrode layer are sequentially etched by applying an etch mask to complete the ferroelectric capacitor including the lower electrode 425, the ferroelectric pattern 435, and the upper electrode 445.

The ferroelectric capacitor formed by the method according to the present invention has a flat top and includes a contact pad made of titanium aluminum nitride having no gap therein, so that the lower electrode layer, the ferroelectric layer and the upper electrode layer formed thereafter are substantially uniform. Has a thickness. That is, when the thickness of the lower electrode layer and the upper electrode layer is reduced for high integration of the semiconductor device, oxygen contained in the ferroelectric layer may prevent the problem of oxidizing the contact pad.

In addition, lifting may be prevented between the ferroelectric layer, the lower electrode layer, and the contact pad due to the thermal stress of the subsequent process, thereby preventing the leakage current from the ferroelectric layer. That is, the electrical characteristics and the reliability of the semiconductor device including the ferroelectric capacitor can be sufficiently secured.

In the foregoing description, it has been described with reference to preferred embodiments of the present invention, but those skilled in the art can variously modify the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. It will be appreciated that it can be changed.

Claims (7)

Forming an insulating structure on the substrate; Etching the insulating structure to form an opening exposing the substrate; Forming a titanium aluminum nitride (Ti _X Al ( _1-X ) N) film covering the upper surface of the insulating structure while the opening is buried; Performing a chemical mechanical polishing process on the titanium aluminum nitride film to expose the surface of the insulating structure to form a contact pad in the opening; Forming a lower electrode layer formed on the insulating structure and the contact pad and electrically connected to the contact pad; Forming a ferroelectric layer on the lower electrode layer; And And forming an upper electrode layer on the ferroelectric layer. The method of claim 1, wherein the titanium aluminum nitride layer is formed by an atomic layer increasing method, and wherein X is 0.5 to 0.95 in Ti _X Al ( _1-X ) N. . The method of claim 1, wherein before forming the contact pad, And forming a spacer on the sidewall of the opening. The method of claim 1, wherein before forming the lower electrode layer, And forming a barrier metal film comprising one selected from the group consisting of titanium aluminum nitride, titanium, titanium nitride and titanium oxide. Forming an insulating structure on the substrate; Etching the insulating structure to form an opening exposing the substrate; Forming a titanium aluminum nitride (Ti _X Al ( _1-X ) N) film covering the upper surface of the insulating structure while the opening is buried; Performing a chemical mechanical polishing process on the titanium aluminum nitride layer to form a titanium aluminum nitride contact pad having a flat top surface on the insulating structure and embedding the opening; Forming a lower electrode layer on the contact pad; Forming a ferroelectric layer on the lower electrode layer; And And forming an upper electrode layer on the ferroelectric layer. The method of claim 5, wherein the contact pad has an upper portion having a thickness of about 100 to about 300 kHz from an upper surface of the insulating structure. The method of claim 5, wherein before forming the contact pad, Forming a spacer on a sidewall of the opening; And And etching the upper portion of the spacer to extend the inlet of the opening.

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