KR20070040654A - Method of forming a semiconductor device having capacitor - Google Patents

Method of forming a semiconductor device having capacitor Download PDF

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KR20070040654A
KR20070040654A KR1020050096215A KR20050096215A KR20070040654A KR 20070040654 A KR20070040654 A KR 20070040654A KR 1020050096215 A KR1020050096215 A KR 1020050096215A KR 20050096215 A KR20050096215 A KR 20050096215A KR 20070040654 A KR20070040654 A KR 20070040654A
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capacitor
forming
plasma treatment
silicon nitride
nitride film
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KR1020050096215A
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Korean (ko)
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김중헌
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삼성전자주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02244—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of a metallic layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02247—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by nitridation, e.g. nitridation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02252—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by plasma treatment, e.g. plasma oxidation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma

Abstract

커패시터를 포함하는 반도체 소자의 형성 방법이 제공된다. 커패시터를 포함하는 반도체 소자의 형성 방법은 기판의 상부에 하부 전극을 형성하는 단계, 제1 플라즈마 처리로 하부 전극의 상부에 실리콘 산화막을 형성하는 단계, 제2 플라즈마 처리로 실리콘 산화막의 상부에 실리콘 질화막을 형성하는 단계 및 제3 플라즈마 처리로 제2 플라즈마 처리 후의 미세 결점을 제거하는 단계를 포함한다.A method of forming a semiconductor device including a capacitor is provided. A method of forming a semiconductor device including a capacitor includes forming a lower electrode on an upper portion of a substrate, forming a silicon oxide layer on an upper portion of the lower electrode by a first plasma treatment, and a silicon nitride layer on the silicon oxide layer by a second plasma treatment. And forming a fine defect after the second plasma treatment by the third plasma treatment.

플라즈마, 커패시터 Plasma, capacitor

Description

커패시터를 포함하는 반도체 소자의 형성 방법{Method of forming a semiconductor device having capacitor}Method of forming a semiconductor device including a capacitor

도 1 내지 5는 본 발명의 일 실시예에 따른 커패시터를 포함하는 반도체 소자를 형성하는 공정도이다.1 to 5 are process diagrams for forming a semiconductor device including a capacitor according to an embodiment of the present invention.

(도면의 주요부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)

100 : 기판 110 : 하부 전극100 substrate 110 lower electrode

120 : 실리콘 산화막 130, 140 : 실리콘 질화막120: silicon oxide film 130, 140: silicon nitride film

150 : 상부 전극150: upper electrode

본 발명은 커패시터를 포함하는 반도체 소자의 형성 방법에 관한 것으로, 보다 상세하게는 신뢰성 높은 커패시터를 포함하는 반도체 소자의 형성 방법에 관한 것이다.The present invention relates to a method of forming a semiconductor device including a capacitor, and more particularly, to a method of forming a semiconductor device including a highly reliable capacitor.

반도체 소자의 고집적화, 고성능화에 따라, 커패시터는 소형화되지만 동일 또는 더 큰 유전 용량을 가지는 것이 필요하다. 이를 위해서 커패시터의 유전막은 유전상수 값은 크고 얇은 두께를 가지면서, 안정된 특성을 가지는 것이 요구되고 있다.With high integration and high performance of semiconductor devices, capacitors need to be miniaturized but have the same or larger dielectric capacitance. To this end, the dielectric film of the capacitor is required to have a stable characteristic while having a large dielectric constant and a thin thickness.

현재, MIM(Metal Insulator Metal) 커패시터 구조는 메탈 하부 전극, 유전막, 메탈 상부 전극의 구조를 가지며 유전막 물질로는 플라즈마 증착 방식을 사용하는 실리콘 질화막이 많이 사용되고 있다. 기존 MIM 구조에서의 커패시터의 용량은 1fF/㎛2 내외의 값이 사용되며, 이를 위한 유전막인 실리콘 질화막은 700~1000Å 정도의 두께를 가진다.Currently, a metal insulator metal (MIM) capacitor structure has a structure of a metal lower electrode, a dielectric layer, and a metal upper electrode, and a silicon nitride layer using plasma deposition is widely used as a dielectric layer material. The capacitance of the capacitor in the conventional MIM structure is a value of about 1fF / ㎛ 2 , the silicon nitride film, a dielectric film for this has a thickness of about 700 ~ 1000Å.

기존 방법의 MIM 커패시터 구조에서 실리콘 질화막 증착시 하부 전극인 알루미늄에서 막질의 스트레스 차에 의한 알루미늄 힐록(Al hillock)이 발생하는 경우가 있으며, 나이트라이드 증착시 파티클이 다발하여 누설 전류가 발생하게 된다.In the conventional MIM capacitor structure, when the silicon nitride film is deposited, an aluminum hillock may be generated due to the difference in film quality in the lower electrode aluminum, and a leakage current may be generated due to the occurrence of particles during nitride deposition.

또한, 2fF/㎛2 내외의 고용량을 요구하는 디바이스가 많아지면서 실리콘 질화막의 두께가 500Å 이하가 요구되고 있다. 그런데, 기존의 가스 비(gas ratio) 및 기존 조성비로 증착시 항복 전압이 급격하게 감소하고, 누설 전류가 증가하여 문제가 발생하고 있다. 또한, 기존 조건으로는 증착률이 높아 500Å 미만 두께 제어가 힘들어, 정확한 커패시턴스 값의 타겟팅(targetting)이 힘들다.In addition, as the number of devices requiring a high capacity of about 2fF / µm 2 increases, the thickness of the silicon nitride film is required to be 500 kPa or less. However, a problem occurs because the breakdown voltage sharply decreases and the leakage current increases with the existing gas ratio and the existing composition ratio. In addition, the deposition rate is high under the existing conditions, it is difficult to control the thickness less than 500Å, it is difficult to target the accurate capacitance value.

본 발명이 이루고자 하는 기술적 과제는, 신뢰성 높은 커패시터를 포함하는 반도체 소자의 형성 방법을 제공하는 것이다.An object of the present invention is to provide a method for forming a semiconductor device including a highly reliable capacitor.

본 발명의 기술적 과제들은 이상에서 언급한 기술적 과제로 제한되지 않으며, 언급되지 않은 또 다른 기술적 과제들은 아래의 기재로부터 당업자에게 명확하 게 이해될 수 있을 것이다. The technical problems of the present invention are not limited to the above-mentioned technical problems, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

상기 기술적 과제를 달성하기 위한 본 발명의 일 실시예에 따른 커패시터를 포함하는 반도체 소자의 형성 방법은 기판의 상부에 하부 전극을 형성하는 단계, 제1 플라즈마 처리로 하부 전극의 상부에 실리콘 산화막을 형성하는 단계, 제2 플라즈마 처리로 실리콘 산화막의 상부에 실리콘 질화막을 형성하는 단계 및 제3 플라즈마 처리로 제2 플라즈마 처리 후의 미세 결점을 제거하는 단계를 포함한다.According to an aspect of the present disclosure, a method of forming a semiconductor device including a capacitor includes forming a lower electrode on an upper portion of a substrate, and forming a silicon oxide layer on the lower electrode through a first plasma treatment. And forming a silicon nitride film on the silicon oxide film by a second plasma treatment, and removing a fine defect after the second plasma treatment by a third plasma treatment.

본 발명의 기타 구체적인 사항들은 상세한 설명 및 도면들에 포함되어 있다.Other specific details of the invention are included in the detailed description and drawings.

본 발명의 이점 및 특징, 그리고 그것들을 달성하는 방법은 첨부되는 도면과 함께 상세하게 후술되어 있는 실시예들을 참조하면 명확해질 것이다. 그러나 본 발명은 이하에서 개시되는 실시예들에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 것이며, 단지 본 실시예들은 본 발명의 개시가 완전하도록 하며, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이며, 본 발명은 청구항의 범주에 의해 정의될 뿐이다. 명세서 전체에 걸쳐 동일 참조 부호는 동일 구성 요소를 지칭한다.Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and the general knowledge in the art to which the present invention pertains. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

도 1 내지 5를 참조하여, 본 발명의 일 실시예에 따른 커패시터를 포함하는 반도체 소자의 형성 방법에 대하여 설명한다.1 to 5, a method of forming a semiconductor device including a capacitor according to an embodiment of the present invention will be described.

도 1을 참조하면, 먼저 하부 구조가 형성된 기판(100) 상부에 하부 전극(110)을 형성한다. 하부 전극(110)은 알루미늄, 구리로 구현될 수 있다. 하부 전극(110)은 배선 구조를 이용하여 형성될 수 있다. Referring to FIG. 1, first, a lower electrode 110 is formed on a substrate 100 on which a lower structure is formed. The lower electrode 110 may be made of aluminum or copper. The lower electrode 110 may be formed using a wiring structure.

도 2를 참조하면, 하부 전극(110)의 상부에 실리콘 산화막(120)을 형성한다.Referring to FIG. 2, a silicon oxide layer 120 is formed on the lower electrode 110.

미량의 SiH4가스와 N2O 가스를 반응 가스로 사용하고, N2를 캐리어 가스로 사용하며, RF(Radio Frequency) 전원을 인가하는 제1 플라즈마 처리로 하부 전극(110)의 상부에 수십 Å의 실리콘 산화막(120)을 형성한다. A first plasma treatment using a small amount of SiH 4 gas and N 2 O gas as a reaction gas, N 2 as a carrier gas, and applying RF (Radio Frequency) power to the upper portion of the lower electrode 110. Silicon oxide film 120 is formed.

위의 반응을 설명하는 반응식은 다음과 같다. The reaction equation describing the above reaction is as follows.

SiH4 + 2N2O -> SiO2 + 2N2 + 2H2 SiH 4 + 2N 2 O-> SiO 2 + 2N 2 + 2H 2

실리콘 산화막의 역할(120)은 하부 전극(110)의 상부에 곧바로 실리콘 질화막(130) 형성시, 실리콘 질화막(130)의 큰 스트레스로 인한 하부 알루미늄 배선의 힐록(hillock) 현상을 방지하기 위한 버퍼층(buffer layer)으로 사용된다. The role of the silicon oxide layer 120 may include a buffer layer for preventing a hillock phenomenon of the lower aluminum wiring due to a large stress of the silicon nitride layer 130 when the silicon nitride layer 130 is formed directly on the lower electrode 110. buffer layer).

힐록 현상이란, 높은 온도와 큰 스트레스로 인해서 알루미늄이 돌출되게 되는 현상으로서, 반도체 소자들 간의 오픈(open) 또는 쇼트(short)를 유발할 수 있다.The hillock phenomenon is a phenomenon in which aluminum protrudes due to high temperature and high stress, and may cause open or short between semiconductor devices.

실리콘 산화막(120) 형성시 압력 및 RF 전원은 후속 실리콘 질화막(130) 형성시 사용되는 조건과 동일한 조건으로 정하여 안정적인 상태에서 연속 공정이 이루어지도록 하는 것이 바람직하다.When the silicon oxide film 120 is formed, the pressure and the RF power supply are preferably set to the same conditions as those used when the silicon nitride film 130 is formed, so that the continuous process is performed in a stable state.

실리콘 산화막(120)의 두께는 약 50Å 미만으로 하여 유전율이 낮은 실리콘 산화막(120)에 의한 전체 커패시턴스 값의 손실을 막을 수 있도록 한다.The thickness of the silicon oxide film 120 is less than about 50 GPa so as to prevent the loss of the total capacitance value caused by the silicon oxide film 120 having a low dielectric constant.

도 3을 참조하면, 실리콘 산화막(120)의 상부에 주 커패시턴스를 결정하는 실리콘 질화막(130)을 증착한다.Referring to FIG. 3, a silicon nitride film 130 that determines a main capacitance is deposited on the silicon oxide film 120.

SiH4와 NH3를 반응 가스로 사용하고, N2를 캐리어 가스로 사용하는 제2 플라즈마 처리를 하여 실리콘 질화막(130)을 형성한다. The silicon nitride film 130 is formed by performing a second plasma treatment using SiH 4 and NH 3 as a reaction gas and using N 2 as a carrier gas.

위의 반응을 설명하는 반응식은 다음과 같다.The reaction equation describing the above reaction is as follows.

SiH4 + NH3 -> SixNyHz + H2 SiH 4 + NH 3- > Si x N y H z + H 2

이때, SiH4/NH3 가스 흐름비는 1.0~0.7이고, 실리콘 질화막(130)의 증착률은 1000Å/min 이하이며, 실리콘 질화막(130)의 굴절율 값은 1.85~1.95일 수 있다. 이를 통해, 수소량 최소화 및 낮은 증착률로 증착하여 치밀한 실리콘 질화막(130)을 형성하여 누설 전류 값을 낮추어 신뢰성 있는 커패시터를 형성할 수 있다. 또한, 500Å 미만의 두께 제어가 가능하여 정확한 커패시턴스의 값을 결정할 수 있다.In this case, the SiH 4 / NH 3 gas flow ratio may be 1.0 to 0.7, the deposition rate of the silicon nitride film 130 may be 1000 mW / min or less, and the refractive index value of the silicon nitride film 130 may be 1.85 to 1.95. Through this, it is possible to form a dense silicon nitride film 130 by minimizing the amount of hydrogen and deposition at a low deposition rate to lower the leakage current value to form a reliable capacitor. In addition, thickness control of less than 500µs is possible to determine the exact value of capacitance.

도 4를 참조하면, 도 3의 실리콘 질화막(130)에 N2를 처리가스로 하여 제3 플라즈마 처리를 하여 보다 안정적인 실리콘 질화막(140)을 형성한다. 이때, 제3 플라즈마 처리시의 N2 흐름량, RF 전원 및 압력 등은 제2 플라즈마 처리시와 동일하게 유지한 상태로 진행하여 연속적으로 공정을 진행할 수 있다. Referring to FIG. 4, a third plasma treatment is performed on the silicon nitride film 130 of FIG. 3 using N 2 as a processing gas to form a more stable silicon nitride film 140. In this case, the N 2 flow amount, the RF power supply and the pressure during the third plasma processing may be maintained in the same state as during the second plasma processing, and the process may be continuously performed.

제3 플라즈마 처리를 통해, 챔버 내의 제2 플라즈마 처리 후 잔류 가스 및 도 3의 실리콘 질화막(130) 표면의 잔류 가스를 반응시켜 표면 미세 파티클을 제거하고, 실리콘 댕글링 본드(silicon dangling bond)를 결합시켜 보다 안정적인 실리콘 질화막(140)의 형성이 이루어진다. 이러한 제3 플라즈마 처리를 통해, 표면 미세 파티클과 실리콘 댕글링 본드 등과 같은 미세 결점에 의한 항복 전압 저하 또는 누설 전류 발생 등을 방지하거나 개선할 수 있다. Through the third plasma treatment, the remaining gas after the second plasma treatment in the chamber and the residual gas on the surface of the silicon nitride film 130 of FIG. 3 are removed to remove the surface fine particles, and the silicon dangling bond is bonded. In this way, a more stable silicon nitride film 140 is formed. Through the third plasma treatment, it is possible to prevent or improve breakdown voltage degradation or leakage current caused by fine defects such as surface fine particles and silicon dangling bonds.

또한, 제2 플라즈마 처리 후의 잔류 가스와 제3 플라즈마 처리시의 N2가 반응하여 실리콘 질화막을 더 형성함에 따라서, 제3 플라즈마 처리 후의 실리콘 질화막(140)은 제2 플라즈마 처리 후의 실리콘 질화막(130)보다 미세하게 더 두꺼운 막이 될 수 있다.In addition, as the residual gas after the second plasma treatment reacts with N 2 during the third plasma treatment to further form a silicon nitride film, the silicon nitride film 140 after the third plasma treatment is formed of the silicon nitride film 130 after the second plasma treatment. It can be a finer thicker film.

도 5를 참조하면, 제3 플라즈마 처리 후의 실리콘 질화막(140)의 상부에 상부 전극(150)을 형성한다. Referring to FIG. 5, the upper electrode 150 is formed on the silicon nitride film 140 after the third plasma treatment.

이후, 후속 공정으로 상부 전극(150) 및 하부 전극(110)의 배선을 형성하기 위해 상부 전극(150) 및 하부 전극(110)의 패터닝 공정 및 후속 금속 배선 및 금속 배선간 절연막 형성 공정 등을 진행하여 소자 형성을 완성한다.Subsequently, in order to form the wirings of the upper electrode 150 and the lower electrode 110, a patterning process of the upper electrode 150 and the lower electrode 110, and a subsequent metal wiring and an insulating film forming process between the metal wirings are performed. The device formation is completed.

전술한 제1 플라즈마 처리, 제2 플라즈마 처리 및 제3 플라즈마 처리는 동일 장비 내에서 연속적으로 진행되는 것이 바람직하며, 통상의 플라즈마 증착 장비 내에서 형성되며 동일 증착 과정에서 가스 흐름량 변화를 위한 공정 스텝만을 변경하여 이루어질 수 있다.The first plasma treatment, the second plasma treatment, and the third plasma treatment described above are preferably continuously performed in the same equipment, and are formed in a conventional plasma deposition apparatus, and only process steps for changing the gas flow rate during the same deposition process are performed. It can be done by changing.

도면에서는 플래너 타입 커패시터에 대해서 도시되고 있지만, 이와는 달리 트랜치 타입 커패시터에 대해서도 마찬가지로 적용될 수 있다.Although shown in the figure for a planar type capacitor, the same applies to the trench type capacitor.

이상 첨부된 도면을 참조하여 본 발명의 실시예를 설명하였지만, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자는 본 발명이 그 기술적 사상이나 필수적인 특징을 변경하지 않고서 다른 구체적인 형태로 실시될 수 있다는 것을 이해할 수 있을 것이다. 그러므로 이상에서 기술한 실시예들은 모든 면에서 예시적인 것이며 한정적이 아닌 것으로 이해해야만 한다. Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

상기한 바와 같은 본 발명에 따르면 다음과 같은 효과가 하나 혹은 그 이상 있다. According to the present invention as described above has one or more of the following effects.

첫째, 실리콘 질화막의 하부에 실리콘 산화막을 형성하여 힐록 현상을 방지할 수 있다.First, a silicon oxide film may be formed under the silicon nitride film to prevent the hillock phenomenon.

둘째, 제2 플라즈마 처리시 반응 가스 흐름비를 조절함으로써, 실리콘 질화막 내의 수소량을 최소화하고 낮은 증착률로 증착하여 치밀한 실리콘 질화막을 형성할 수 있다.Second, by controlling the reaction gas flow rate during the second plasma treatment, it is possible to minimize the amount of hydrogen in the silicon nitride film and to deposit at a low deposition rate to form a dense silicon nitride film.

셋째, 제2 플라즈마 처리로 실리콘 질화막을 형성한 후, 제3 플라즈마 처리를 하여 미세 결점을 제거함에 따라서, 보다 안정적인 커패시터의 유전막을 형성할 수 있다.Third, after the silicon nitride film is formed by the second plasma treatment, the third plasma treatment is used to remove fine defects, thereby forming a more stable dielectric film of the capacitor.

Claims (7)

기판의 상부에 하부 전극을 형성하는 단계;Forming a lower electrode on top of the substrate; 제1 플라즈마 처리로 상기 하부 전극의 상부에 실리콘 산화막을 형성하는 단계;Forming a silicon oxide film on the lower electrode by a first plasma treatment; 제2 플라즈마 처리로 상기 실리콘 산화막의 상부에 실리콘 질화막을 형성하는 단계; 및Forming a silicon nitride film on the silicon oxide film by a second plasma treatment; And 제3 플라즈마 처리로 상기 제2 플라즈마 처리 후의 미세 결점을 제거하는 단계를 포함하는 커패시터를 포함하는 반도체 소자의 형성 방법.A method of forming a semiconductor device comprising a capacitor comprising removing a fine defect after the second plasma treatment by a third plasma treatment. 제 1항에 있어서,The method of claim 1, 상기 제1 플라즈마 처리시 SiH4 및 N2O를 반응 가스로 사용하고 N2를 캐리어 가스로 사용하는 커패시터를 포함하는 반도체 소자의 형성 방법.And a capacitor using SiH 4 and N 2 O as a reaction gas and N 2 as a carrier gas during the first plasma treatment. 제 1항에 있어서,The method of claim 1, 상기 제2 플라즈마 처리는 SiH4와 NH3를 반응 가스로 사용하고 N2를 캐리어 가스로 사용하는 커패시터를 포함하는 반도체 소자의 형성 방법.The second plasma treatment method includes a capacitor using SiH 4 and NH 3 as a reaction gas and N 2 as a carrier gas. 제 3항에 있어서,The method of claim 3, wherein 상기 제2 플라즈마 처리시 상기 SiH4/NH3 처리가스 흐름비는 1.0~0.7인 커패시터를 포함하는 반도체 소자의 형성 방법.And a SiH 4 / NH 3 process gas flow ratio during the second plasma process, the capacitor including 1.0 to 0.7. 제 1항에 있어서, The method of claim 1, 상기 실리콘 질화막의 굴절율 값은 1.85~1.95인 커패시터를 포함하는 반도체 소자의 형성 방법.The refractive index value of the silicon nitride film is a method of forming a semiconductor device comprising a capacitor of 1.85 ~ 1.95. 제 1항에 있어서,The method of claim 1, 상기 제3 플라즈마 처리시의 N2 흐름량, 압력 및 RF 전원은 상기 제2 플라즈마 처리시와 동일하게 유지하는 커패시터를 포함하는 반도체 소자의 형성 방법.And a N 2 flow amount, pressure, and RF power supply in the third plasma processing are the same as in the second plasma processing. 제 1항에 있어서,The method of claim 1, 상기 제1 플라즈마 처리 내지 제3 플라즈마 처리는 동일 장비 내에서 행해지는 커패시터를 포함하는 반도체 소자의 형성 방법.The first plasma processing to the third plasma processing comprises a capacitor that is performed in the same equipment.
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