JP3618246B2 - Manufacturing method of semiconductor device - Google Patents

Description

上記表１では、プラズマＣＶＤ装置のセラミックドーム１０５内にガスを供給している場合、プラズマを形成するためのＲＦ電力を印加している場合などを「○」印として表し、そうでないときを「×」印として表している。図５（ａ）から（ｇ）は、各工程の成膜状態を模式的に示している。図６は、各工程ごとのガス流量、プラズマの形成の有無、チャッキング電圧の有無、裏面Ｈｅ導入の有無を示している。
【００３０】
まず、図５（ａ）に示すように、公知の技術を用いて第１層間絶縁膜１上に第１配線４を形成した半導体基板１０１を用意する。次いで、半導体基板１０１をプラズマＣＶＤ装置内の静電チャック１０２上に設置する（基板設置工程Ｓ１）。
【００３１】
次に、図６（ａ）に示すように、ＡｒガスおよびＯ_２ガスをガス導入口１０８に導入することによって、ガスノズル１０４を介してセラミックドーム１０５内にＡｒガスおよびＯ_２ガスを供給する。その後、図６（ｂ）に示すように、ソースＲＦ電力供給コイル１０３にソースＲＦ電力（２ＭＨｚ）を印加してセラミックドーム１０５内にプラズマを形成する（プラズマ形成工程Ｓ２）。セラミックドーム１０５内に供給するＡｒガスの流量は例えば５０〜２００ｓｃｃｍ、好ましくは１１０ｓｃｃｍとし、Ｏ_２ガスの流量は例えば３０〜２００ｓｃｃｍ、好ましくは３０ｓｃｃｍとする。また、セラミックドーム１０５内にプラズマを形成しているときは、セラミックドーム１０５内の圧力が例えば５ｍＴｏｒｒ〜３００ｍＴｏｒｒの範囲内になるようにする。
【００３２】
次に、図６（ｃ）に示すように、静電チャック１０２にチャッキング電圧を印加して、半導体基板１０１と静電チャック１０２とを吸着状態にする（基板吸着工程Ｓ３）。チャッキング電圧の印加は、セラミックドーム１０５内に材料ガスを供給するまでに行う。材料ガスを供給した後にチャッキング電圧を印加することは、半導体基板１０１と静電チャック１０２とが吸着状態になるまでの間に半導体基板１０１の裏面などで成膜が行われてしまうため好ましくない。
【００３３】
次に、図５（ａ）から（ｂ）に示すように、第１層配線４を覆うように第１層間絶縁膜１上にライナー層６を形成する（ライナー層形成工程Ｓ４）。図６（ａ）および（ｂ）に示すように、工程４はＡｒガスおよびＯ_２ガスの供給を続けた状態でプラズマを形成させたままＳｉＨ_４ガスをセラミックドーム１０５内に供給することによって行われる。ＳｉＨ_４ガスの流量は例えば１０〜１００ｓｃｃｍ、好ましくは３６ｓｃｃｍとする。図６（ａ）に示すように、工程Ｓ４で用いるＡｒガスおよびＯ_２ガスの流量は、工程Ｓ２およびＳ３で用いた流量と比較して増加させる。工程Ｓ４でのＡｒガスの流量は１２６ｓｃｃｍ、Ｏ_２ガスの流量は１２６ｓｃｃｍとするのが好ましい。工程Ｓ４は、ライナー層６の厚さが例えば０．０１〜０．１μｍとなるまで行われる。
【００３４】
次に、図５（ｂ）から（ｃ）に示すように、ライナー層６を覆うように第１層間絶縁膜１の上にフッ素ドープシリコン酸化膜（ＳｉＯＦ膜）２を形成する（ＳｉＯＦ膜形成工程Ｓ５）。図６（ａ）および（ｂ）に示すように、コイル１０３にソースＲＦ電力を印加している状態で静電チャック１０２にバイアスＲＦ（１３．５６ＭＨｚ）を印加してセラミックドーム１０５内に高密度プラズマを形成させると共に、ＳｉＨ_４ガス、ＡｒガスおよびＯ_２ガスの供給を続けた状態でＳｉＦ_４ガスをセラミックドーム内１０５に供給することによって工程Ｓ５を行う。
【００３５】
工程Ｓ５で高密度プラズマを用いるのは、膜質のよいフッ素ドープシリコン酸化膜を形成するためである。膜質のよいフッ素ドープシリコン酸化膜とは、フッ素を解離させにくく、水分を吸着しにくい膜のことをいう。セラミックドーム１０５内のプラズマの電子密度は使用する装置、条件等によって異なるが、バイアスＲＦ電力を印加する前のプラズマの電子密度は例えば１０^１０〜１０^１１ｃｍ^−３程度であり、バイアスＲＦ電力を印加した後のプラズマ（高密度プラズマ）の電子密度は例えば１０^１２〜１０^１３ｃｍ^−３程度である。
【００３６】
工程Ｓ５では静電チャック１０２にバイアスＲＦ電力を印加しているため、フッ素ドープシリコン酸化膜２を配線と配線との間に埋め込むことができる。バイアスＲＦ電力の印加による基板温度の上昇を抑制するために、図６（ｄ）に示すように静電チャック１０２の凹部にＨｅを導入する。半導体基板１０１の温度は、例えば４００〜５００℃の範囲内になるように制御される。
【００３７】
工程Ｓ５でのＳｉＦ_４ガスの流量は、例えば１０〜５０ｓｃｃｍ、好ましくは２７．５ｓｃｃｍとする。図６（ａ）に示すように、工程Ｓ５でのＡｒガスおよびＯ_２ガスの流量は工程Ｓ４で用いた流量と比較して減少させる。工程Ｓ５でのＡｒガスの流量を５５ｓｃｃｍ、Ｏ_２ガスの流量を９２ｓｃｃｍとするのが好ましい。工程Ｓ５でのＳｉＨ_４ガスの流量は、工程Ｓ４で用いた流量と比較して増加させる。工程Ｓ５でのＳｉＨ_４ガスの流量は例えば２０〜１００ｓｃｃｍ、好ましくは５０ｓｃｃｍとする。
【００３８】
フッ素ドープシリコン酸化膜２の厚さが例えば０．３〜０．８μｍの範囲内になるまで工程Ｓ５を行う。フッ素ドープシリコン酸化膜中のフッ素濃度が０．５〜３．０原子％の範囲内になるようにフッ素ドープシリコン酸化膜２を形成するのが好ましい。
【００３９】
その後、図６（ｂ）に示すように、バイアスＲＦ電力の印加を停止することによってセラミックドーム１０５内を高密度プラズマが形成されている状態から通常のプラズマが形成されている状態すると共に、図６（ａ）に示すようにＳｉＦ_４ガスの供給を停止し、それによってフッ素ドープシリコン酸化膜２の成長を停止させる。
【００４０】
図６（ｄ）に示すように、バイアスＲＦ電力の印加を停止する際に、静電チャック１０２の凹部へのＨｅの導入を停止する。このＨｅの導入を停止した後は、静電チャック１０２の凹部内のＨｅがセラミックドーム１０５内に漏れていくため、半導体基板１０１の裏面における圧力は次第に低下する。
【００４１】
次に、図５（ｃ）から（ｄ）に示すように、キャップ層１０としてＳＲＯ膜の成長を開始させる（キャップ層成長開始工程Ｓ６）。具体的には、フッ素ドープシリコン酸化膜２上にＳＲＯ膜が成長するように流量を制御したＳｉＨ_４ガス、ＡｒガスおよびＯ_２ガスをセラミックドーム１０５に供給する。工程６でのＳｉＨ_４ガスの流量は、図６（ａ）に示すように、工程Ｓ５で用いた流量と比較して特に変化させない。工程６でのＳｉＨ_４ガスの流量は例えば２０〜１００ｓｃｃｍ、好ましくは５０ｓｃｃｍとする。工程Ｓ６でのＡｒガスおよびＯ_２ガスの流量は、工程Ｓ５で用いた流量と比較して増加させる。工程６でのＡｒガスの流量は１２６ｓｃｃｍ、Ｏ_２ガスの流量は１２６ｓｃｃｍとするのが好ましい。
【００４２】
キャップ層として成長させるＳＲＯ膜は、好ましくは屈折率１．４８以上、さらに好ましくは屈折率１．４８〜１．６０となるように成長させる。なお、ストイキオメトリー組成を持つ通常のシリコン酸化膜（ＳｉＯ_２）の屈折率は１．４６であり、ＳＲＯ膜中のシリコン（Ｓｉ）の数が多くなるほど屈折率は大きくなる。
【００４３】
次に、図５（ｄ）から（ｅ）に示すように、プラズマの形成を停止することによって、キャップ層１０の成長を停止する（キャップ層成長停止工程Ｓ７）。プラズマ形成の停止は、図６（ａ）および（ｂ）に示すように、材料ガスであるＳｉＨ_４ガスをセラミックドーム１０５内に供給しながら、ソースＲＦ電力の印加を停止することによって行う。
【００４４】
プラズマの形成を停止した後は、ＳｉＨ_４ガスをセラミックドーム１０５内に供給しても、キャップ層１０は成長しない。プラズマによってＳｉＨ_４ガスが分解されないため、ＳｉＨ_４ガスが半導体基板表面と反応しないからである。キャップ層１０の厚さは、例えば０．０２〜０．１μｍの範囲内になるように、好ましくは０．０６μｍ程度になるようにする。
【００４５】
次に、図５（ｅ）から（ｄ）に示すように、材料ガスであるＳｉＨ_４ガスの供給を停止する（材料ガス停止工程Ｓ８）。ＳｉＨ_４ガスの供給を停止した後も、ガス配管にはＳｉＨ_４ガスが残留しているため、引き続きセラミックドーム１０５内にＳｉＨ_４ガスが供給されることになる。しかし、工程Ｓ７において既にプラズマの形成を停止しているため、ガス配管に残留しているＳｉＨ_４ガスによってキャップ層１０が成長することはない。
【００４６】
次に、図６（ａ）および（ｂ）に示すように、ＡｒガスおよびＯ_２ガスを供給した状態でソースＲＦ電力をコイル１０３に印加し、セラミックドーム１０５内にプラズマを再び形成する（プラズマ再形成工程Ｓ９）。プラズマを再び形成する理由は、チャッキング電圧の印加を停止するだけでは、半導体基板１０１に蓄積された電荷を中和することができず、半導体基板１０１と静電チャック１０２との間の吸着状態を解除することができないからである。半導体基板１０１と静電チャック１０２との間の吸着状態を解除する理由は、後述するように、キャップ層１０を形成した後に半導体基板１０１を別の装置に移動させる必要があるからである。
【００４７】
次に、図６（ｄ）に示すように、半導体基板１０１の裏面に存在するＨｅを静電チャック１０２の凹部から除去する（裏面Ｈｅ除去工程Ｓ１０）。工程６を実行する前に静電チャック１０２の凹部へのＨｅの導入を停止したことによって、Ｈｅの圧力は次第に低下していくが、セラミックドーム１０５内の圧力にまでは低下しない。そのため、工程Ｓ１０において静電チャック１０２の凹部に存在するＨｅを強制的に除去することによって、半導体基板１０１の裏面とセラミックドーム１０５内との間の圧力を同じにする。
【００４８】
工程Ｓ１０は、チャッキング電圧の印加を停止する前までに行う必要がある。チャッキング電圧の印加を停止するまでにＨｅを除去しておかないと、セラミックドーム１０５内と半導体基板１０１の裏面との間の圧力差によって、半導体基板が静電チャック１０２から移動または離脱することになる。
【００４９】
次に、図６（ｂ）および（ｃ）に示すように、セラミックドーム１０５内にプラズマを形成させた状態でチャッキング電圧の印加を停止する（チャッキング電圧停止工程Ｓ１１）。この際、半導体基板１０１に蓄積されていた電荷がプラズマによって中和され、半導体基板１０１と静電チャック１０２との間の吸着状態が解除される。その後、図６（ｂ）に示すように、ソースＲＦ電力の印加を停止することによってセラミックドーム１０５内のプラズマの形成を停止する（プラズマ停止工程Ｓ１２）。
【００５０】
次に、図５（ｆ）から（ｇ）に示すように、キャップ層１０上に第２層間絶縁膜３および第２配線５を形成するために、静電チャック１０２上の半導体基板１０１をプラズマＣＶＤ装置から取り出して、別のプラズマＣＶＤ装置内に移動させる。別のプラズマＣＶＤ装置内に半導体基板１０１を移動させる理由は、別のプラズマＣＶＤ装置で第２層間絶縁膜３および第２配線５を形成する方が製造コストを低くすることができるからである。なお、ＳＲＯ膜からなるキャップ層１０は大気に曝すだけでは酸化されないため、半導体基板１０１を大気に曝してもキャップ層１０中のシリコンリッチ組成に変化は生じない。
【００５１】
その後、図５（ｇ）に示すように、別のプラズマＣＶＤ装置にて公知の技術を用いてキャップ層１０上に第２層間絶縁膜３を形成した後、第２層間絶縁膜３上に第２層配線５を形成する。
【００５２】
図７は、本実施形態における半導体装置の製造方法によって形成されたキャップ層がフッ素拡散を抑制する能力を示している。図７では、二次イオン質量分析法（ＳＩＭＳ）によって半導体基板の深さごとのフッ素濃度をキャップ層の有無で比較しており、キャップ層として厚さ０．０６μｍのＳＲＯ膜をフッ素ドープシリコン膜（ＳｉＯＦ膜）上に形成している。キャップ層を用いた場合、キャップ層を用いない場合と比較して上層に形成したＳｉＯ_２（第２層間絶縁膜）中へのフッ素の拡散量が少ないことがわかる。
【００５３】
第１の実施形態では、フッ素ドープシリコン酸化膜上にキャップ層としてＳＲＯ膜を成長させたが、ＳＲＯ膜に代えてシリコンリッチシリコン窒化膜（以下、「ＳＲＮ膜」と称する。）をキャップ層として成長させてもよい。なお、本明細書において「ＳＲＮ膜」とは、ストイキオメトリ組成を持つシリコン窒化物（Ｓｉ_３Ｎ_４）中のＳｉ原子の数よりも多くのＳｉ原子を含むシリコン窒化膜を意味する。
【００５４】
キャップ層としてＳＲＮ膜を用いた場合でも、ＳＲＮ膜中に存在している未結合手を持つシリコン原子によってフッ素を捕捉し、フッ素拡散を抑制することができる。ＳＲＮ膜を成長させた場合には、ＳＲＯ膜よりもＳＲＮ膜の密度の方が大きく（Ｓｉ_３Ｎ_４：２．７ｇ／ｃｍ^３、ＳｉＯ_２：２．３ｇ／ｃｍ^３）、膜が緻密であるため、ＳＲＯ膜よりもフッ素拡散を抑制することができる。キャップ層として成長させるＳＲＮ膜の屈折率は例えば２．０５以上、好ましくは２．０５〜２．１となるようにする。
【００５５】
なお、上記の実施形態において、第１層間絶縁膜が形成される被加工基板として半導体基板を使用しているが、他の基板（例えばガラス基板）を用いても良い。ガラス基板やその他の基板に薄膜トランジスタを形成した半導体装置も、今後、ますます集積化される可能性があり、そのような半導体装置の製造に本発明を適用することは非常に好ましい効果をもたらすと期待される。本明細書における「半導体装置」は半導体基板を不可欠の要素として有するものに限定されない。
【００５６】
また、本発明による第１の実施形態の製造方法は、均一な厚さのキャップ層を再現性よく形成する場合に用いられるだけでなく、プラズマＣＶＤ法を用いて均一な厚さの薄膜を再現性よく形成する場合にまで適用できる。すなわち、高密度プラズマを用いる等の理由から静電チャックに基板を吸着させて薄膜を形成する場合、薄膜を成長させるための材料ガスの供給をしたまま、プラズマの形成を停止すれば、均一な厚さの薄膜を再現性よく形成できる。高密度プラズマを用いて形成される膜としては、例えば、フッ素ドープシリコン酸化膜の他、フッ素が添加されていない通常のシリコン酸化膜がある。
（比較例）
材料ガスの供給を停止することによってキャップ層の成長を停止する点が第１の実施形態による半導体装置の製造方法と異なる比較例について説明する。比較例の製造方法も、第１の実施形態の製造方法と同様に、図３の装置を用いて図１に示す配線構造を製造するために使用する。以下においては、第１の実施形態と異なる工程を主に説明し、他の工程の説明は省略する。なお、比較例の製造方法は、第１の実施形態と異なり、工程途中でプラズマの形成を停止しないため、プラズマの再形成を必要としない。
【００５７】
まず、図８を参照しながら比較例による半導体装置の製造方法のプロセスフローを説明する。比較例のプロセスフローは下記表２に示す条件に従って実行される。
【００５８】
【表２】

表２では、表１と同様に、セラミックドーム１０５内にガスを供給している場合、プラズマを形成するためのＲＦ電力をコイル１０３に印加している場合などを「○」印として表し、そうでないときを「×」印として表している。
【００５９】
工程Ｓ１０１で、基板１０１を静電チャック１０２に設置する。
【００６０】
工程Ｓ１０２で、セラミックドーム１０５内にプラズマを形成させる。
【００６１】
工程Ｓ１０３で、静電チャック１０２にチャッキング電圧を印加して、半導体基板１０１と静電チャック１０２とを吸着状態にする。
【００６２】
工程Ｓ１０４で、ライナー層６を形成する。
【００６３】
工程Ｓ１０５で、フッ素ドープシリコン酸化膜（ＳｉＯＦ）２を形成する。
【００６４】
工程Ｓ１０６で、キャップ層１０の成長を開始する。
【００６５】
工程Ｓ１０７で、材料ガス（ＳｉＨ_４）の供給を停止することによって、キャップ層１０の成長を停止させる。
【００６６】
工程Ｓ１０８で、静電チャック１０２の凹部に存在するＨｅを除去する。
【００６７】
工程Ｓ１０９で、チャッキング電圧の印加を停止する。
【００６８】
工程Ｓ１１０で、セラミックドーム１０５内のプラズマの形成を停止する。
【００６９】
比較例の製造方法では、工程Ｓ１０７で材料ガスの供給を停止した後に工程Ｓ１１０でプラズマの形成を停止する順番を採用している。その理由は、第１の実施形態の製造方法のように一度プラズマの形成を停止すると静電チャック１０２から半導体基板１０１を取り外すためにプラズマを再形成させなければならず（図４の工程Ｓ９）、成膜処理の時間が長くなり、スループットが低下するからである。
【００７０】
本発明者は、スループットの高さを優先させた比較例の製造方法では、均一な厚さのキャップ層を再現性よく形成できないということを見いだした。その原因は、ガス配管に残留する材料ガス（ＳｉＨ_４ガス）によってキャップ層１０の上に膜が追加して形成されるからである。図９および図１０を参照しながら、その詳細を説明する。
【００７１】
図９（ａ）から（ｄ）は、工程Ｓ１０５からＳ１０６における成膜状態を模式的に示している。まず、図９（ａ）から（ｂ）に示すように、セラミックドーム１０５内に材料ガスであるＳｉＨ_４ガスを供給しながら、フッ素ドープシリコン酸化膜２上にキャップ層１０を成長させる。
【００７２】
次いで、図９（ｂ）から（ｃ）に示すように、キャップ層１０の成長を停止させる目的で、ガス導入口１０８に導入するＳｉＨ_４ガスの供給を停止する。しかし、ＳｉＨ_４ガスの供給を停止した後も、ガス配管にはＳｉＨ_４ガスが残留している。このガス配管に残留したＳｉＨ_４ガス２０は、ＳｉＨ_４ガスの供給を停止した後も引き続きセラミックドーム１０５内に拡散することになる。
【００７３】
ＳｉＨ_４ガスの供給を停止した時点では、セラミックドーム１０５内にプラズマが形成されているため、図９（ｃ）に示すように、ガス配管に残留していたＳｉＨ_４ガス２０はプラズマで分解されて、半導体基板１０１の表面であるキャップ層１０と反応する。その結果、図９（ｄ）に示すように、ＳＲＯ膜２１が追加して形成されるため、比較例の製造方法では均一なキャップ層を再現性よく形成させることができない。
【００７４】
また、比較例の製造方法では、使用するプラズマＣＶＤ装置に基づく問題も発生する。図１０（ａ）から（ｃ）を参照しながらこの問題を説明する。図１０（ａ）は、半導体基板１０１の左下付近に材料ガス（ＳｉＨ_４ガス）のガス導入口１０８を備えたプラズマＣＶＤ装置を模式的に示している。この装置ではガス導入口１０８が半導体基板１０１に対して非対称の位置に１カ所だけ設けられているため、工程Ｓ１０６で材料ガスの供給を停止すると、時間の経過とともにセラミックドーム１０５内でＳｉＨ_４ガスの分圧に偏りが生じることになる。図１０（ａ）に示すように、半導体基板１０１の左下部（Ｉ）（ガス導入口付近）では右上部（ＩＩ）よりもＳｉＨ_４の分圧が時間の経過と共に早く低くなる。
【００７５】
このようにＳｉＨ_４の分圧に偏りが生じるために、図１０（ｂ）および（ｃ）に示すように左下部（Ｉ）よりも右上部（ＩＩ）の方がキャップ層１０の厚さが厚く形成されてしまう。そのため、比較例の製造方法では均一な厚さのキャップ層１０を形成することが困難になる。このＳｉＨ_４ガスの分圧に偏りが生じる問題は、１つのプラズマＣＶＤ装置においてガス配管の長さが異なるときにも発生するおそれがある。
【００７６】
量産時に複数のプラズマＣＶＤ装置を用いる場合には、工程Ｓ１０６で材料ガスの供給を停止した際、各装置間でＳｉＨ_４ガスの分圧に差異が生じるおそれがある。具体的には、各装置に接続されている材料ガスのガス配管の長さが異なるとき、真空ポンプの排気配管の長さや配管抵抗が異なるために各装置の排気能力に違いが生じているとき、または各装置内のガス排気能力に変動を生じたときなどが挙げられる。このようなときに比較例の製造方法では形成されるキャップ層の膜厚が各装置ごとに異なるという問題が生じ得る。
【００７７】
第１の実施形態による半導体装置の製造方法では、プラズマの形成を停止した後にＳｉＨ_４ガスがセラミックドーム１０５内に供給されてもキャップ層１０は成長しない。そのため、プラズマの形成を停止した後に、基板表面内でＳｉＨ_４の分圧に偏りが生じても、キャップ層の厚さに変化が生じることはない。
【００７８】
また、第１の実施形態の製造方法では、複数のプラズマＣＶＤ装置における真空ポンプの排気能力等が各装置ごとに異なる場合でも、キャップ層を成長させている時にはマスフローコントローラまたは圧力計でガス量が制御されているため各装置間のＳｉＨ_４の分圧の差異という問題は生じない。プラズマの形成を停止した後に各装置内の排気能力の違いによって各装置間にＳｉＨ_４ガスの分圧の差異が生じても、キャップ層の膜厚に影響を及ぼすことはない。そのため、第１の実施形態の製造方法では、比較例の製造方法の場合のような問題が生じない。
【００７９】
【発明の効果】
本発明の半導体装置の製造方法によれば、均一な厚さのフッ素拡散抑制膜を再現性よく形成することができる。フッ素ドープシリコン酸化膜の上方に配線がある場合には、フッ素ドープシリコン酸化膜からのフッ素拡散をフッ素拡散抑制膜によって抑制することができるため、配線に含まれるＴｉバリヤメタル等と層間絶縁膜との間の密着性の劣化を再現性よく防止することが可能となる。その結果、半導体装置の信頼性を向上させることができる。
【００８０】
フッ素拡散抑制膜の厚さが０．０２〜０．１μｍの範囲内となるようにフッ素拡散抑制膜の成長させた場合、フッ素拡散抑制膜によってフッ素ドープシリコン酸化膜からのフッ素拡散を抑制できるとともに、バイアホールの形状を劣化させずにバイアホールを形成することができる。フッ素拡散抑制膜としてＳＲＯ膜を成長させた場合には、ＳＲＯ膜中に存在している未結合手を持つシリコン原子でフッ素を捕捉し、フッ素拡散を抑制することができる。また、フッ素拡散抑制膜としてＳＲＮ膜を成長させた場合には、ＳＲＯ膜よりもＳＲＮ膜の密度の方が大きいため、ＳＲＯ膜よりもフッ素拡散を抑制することができる。
【００８１】
本発明の薄膜形成方法によれば、均一な厚さの薄膜を再現性よく形成することができる。
【図面の簡単な説明】
【図１】フッ素ドープシリコン酸化膜上にキャップ層（ＳＲＯ膜）を備えた半導体装置の配線構造を説明するための断面図である。
【図２】フッ素ドープシリコン酸化膜を備えた従来の半導体装置の配線構造を説明するための断面図である。
【図３】（ａ）プラズマＣＶＤ装置の断面図である。（ｂ）プラズマＣＶＤ装置の平面図である。
【図４】第１の実施形態による半導体の製造方法を説明するためのプロセスフローである。
【図５】（ａ）から（ｇ）は、第１の実施形態による半導体装置の製造方法における主な工程の成膜状態を説明するための図である。
【図６】（ａ）セラミックドーム内に供給されるガス流量の変化を説明するための図である。（ｂ）プラズマ形成の有無を説明するための図である。（ｃ）チャッキング電圧の有無を説明するための図である。（ｄ）半導体基板の裏面に導入されたＨｅの圧力を説明するための図である。
【図７】層間絶縁膜の深さとフッ素濃度との関係をキャップ層（ＳＲＯ膜）の有無で比較した図である。
【図８】比較例による半導体装置の製造方法を説明するためのプロセスフローである。
【図９】（ａ）から（ｄ）は、比較例による半導体装置の製造方法を説明するための図である。
【図１０】（ａ）から（ｃ）は、キャップ層（ＳＲＯ膜）の厚さが不均一となることを説明するための図である。
【符号の説明】
１ 第１層間絶縁膜
２ フッ素ドープシリコン酸化膜（ＳｉＯＦ）
３ 第２層間絶縁膜
４ 第１層配線
４ａ 第１層配線（ＴｉＮ／Ｔｉ）
４ｂ 第１層配線（ＴｉＮ／Ａｌ）
５ 第２層配線
５ａ 第２層配線（ＴｉＮ／Ｔｉ）
５ｂ 第２層配線（ＴｉＮ／Ａｌ）
６ ライナー層（シリコン酸化膜）
１０ キャップ層（ＳＲＯ膜）
１１ 第１層間絶縁膜
１２ フッ素ドープシリコン酸化膜
１３ 第２層間絶縁膜
１４ 第１層配線
１５ 第２層配線
１４ａ、１５ａ ＴｉＮ／Ｔｉ層
１４ｂ、１５ｂ Ａｌ合金層
２０ 残留ＳｉＨ_４ガス
２１ 追加形成された膜
１０１ 半導体基板
１０２ 静電チャック
１０３ ソースＲＦコイル
１０４ ガスノズル
１０５ セラミックドーム
１０６ スロットルバルブ
１０７ ターボポンプ
１０８ ガス導入口（ＳｉＨ_４、Ａｒ）[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device provided with a fluorine diffusion suppression film that suppresses fluorine diffusion.
[0002]
[Prior art]
In order to speed up the operation of a semiconductor integrated circuit designed with a design rule of 0.35 microns or less, it is required to reduce the capacitance of the interlayer insulating film. If the capacitance of the interlayer insulating film is reduced, an electric signal with a higher frequency can be handled, and the operation of the semiconductor integrated circuit can be speeded up.
[0003]
In order to reduce the capacitance of the interlayer insulating film, the interlayer insulating film has been conventionally formed thick, but recently, an insulating material having a lower dielectric constant than that of a normal silicon oxide film having a stoichiometric composition is used. Formation of an insulating film is being studied. A typical example of such an interlayer insulating film is a fluorine-doped silicon oxide film.
[0004]
FIG. 2 schematically shows a conventional wiring structure in a semiconductor device provided with a fluorine-doped silicon oxide film. This wiring structure is formed on a silicon substrate (not shown) on which semiconductor elements and the like are formed. More specifically, a first interlayer insulating film 11 made of a normal silicon oxide film is formed on a silicon substrate (not shown), and a first layer wiring 14 is formed on the first interlayer insulating film 11. ing. The first layer wiring 14 is composed of a TiN / Ti layer 14a and an Al alloy layer 14b for improving the reliability of the wiring. A fluorine-doped silicon oxide film 12 is formed on the first interlayer insulating film 11 so as to cover the first layer wiring 14. Since the fluorine-doped silicon oxide film has a defect that the adhesion to the metal material is poor, after the second interlayer insulating film 13 made of a normal silicon oxide film is formed on the fluorine-doped silicon oxide film 12, Second layer wiring 15 is formed. The upper surface of the second interlayer insulating film 13 is flattened. Similar to the first layer wiring 14, the second layer wiring 15 is composed of a Ti layer 15a and an Al alloy layer 15b.
[0005]
In the conventional wiring structure shown in FIG. 2, fluorine is diffused from the fluorine-doped silicon oxide film 12 and taken into the second interlayer insulating film 13 by the heat treatment performed after the formation of the fluorine-doped silicon oxide film 12. A phenomenon occurs. The fluorine taken into the second interlayer insulating film 13 reacts with the TiN / Ti layer 15a of the second layer wiring to form a TiF layer. When the TiF layer is formed, the adhesion between the second wiring 15 and the second interlayer insulating film 13 is deteriorated, and as a result, the reliability of the semiconductor device is lowered.
[0006]
In order to suppress fluorine diffusion from the fluorine-doped silicon oxide film, a wiring structure of a semiconductor device provided with a silicon-rich silicon oxide film on the fluorine-doped silicon oxide film has been developed, and is disclosed in Japanese Patent Application No. 10-35152. Has been. A silicon-rich silicon oxide film (hereinafter referred to as “SRO film”) has a smaller fluorine diffusion constant than a normal silicon oxide film, and thus plays a role of suppressing fluorine diffusion. It is considered that the SRO film plays such a role in order to trap fluorine diffused by silicon atoms having dangling bonds existing in the SRO film.
[0007]
[Problems to be solved by the invention]
Since the SRO film is not suitable for fine processing, it is desirable to form the SRO film on the fluorine-doped silicon oxide film as thin as possible. When the SRO film is formed thick, it becomes difficult to form a via hole by etching the SRO film, resulting in inconveniences such as deterioration of the shape of the via hole and an increase in wiring electrical resistance in the via hole. .
[0008]
The inventor has found that when an SRO film is formed on a fluorine-doped silicon oxide film, the thickness of the SRO film differs depending on the film forming apparatus, and the SRO film cannot be formed with good reproducibility. Further, it has been found that the thickness of the SRO film is not uniform within the substrate surface. When the SRO film is thinly formed, a thin portion is generated due to the unevenness of the film thickness, and the ability to suppress fluorine diffusion is significantly reduced in that portion. In addition, the silicon concentration in the SRO film varies, and a region that does not partially have a silicon-rich composition occurs. As a result, there is a possibility that fluorine diffusion cannot be suppressed. If the ability to suppress fluorine diffusion varies, ultimately it becomes difficult to stably manufacture a reliable semiconductor device.
[0009]
The present invention has been made in view of such various points, and a main object thereof is to provide a method of manufacturing a semiconductor device capable of forming a film having a uniform thickness that suppresses fluorine diffusion with high reproducibility. It is in.
[0011]
Another method of manufacturing a semiconductor device according to the present invention includes a step of installing a substrate in a plasma vapor deposition apparatus, a step of forming a fluorine-doped silicon oxide film on the substrate using high-density plasma, and the plasma gas While supplying the material gas for growing a fluorine diffusion suppression film for suppressing fluorine diffusion into the plasma vapor phase growth apparatus while the substrate is installed in the phase growth apparatus, the fluorine diffusion suppression film is formed using plasma. A step of starting growth, and a step of stopping the growth of the fluorine diffusion suppression film by stopping the formation of the plasma while supplying the material gas, and the fluorine diffusion suppression film is formed of silicon-rich silicon oxide. It is a membrane. In this specification, “silicon-rich silicon oxide film” means SiO having a stoichiometric composition. ₂ It means a silicon oxide film containing more Si atoms than the number of Si atoms in it.
[0012]
Another method of manufacturing a semiconductor device according to the present invention includes a step of installing a substrate in a plasma vapor deposition apparatus, a step of forming a fluorine-doped silicon oxide film on the substrate using high-density plasma, and the plasma Fluorine diffusion suppression film using plasma while supplying a material gas for growing a fluorine diffusion suppression film for suppressing fluorine diffusion into the plasma vapor phase growth apparatus while the substrate is installed in the vapor phase growth apparatus And the step of stopping the growth of the fluorine diffusion suppression film by stopping the formation of the plasma while supplying the material gas, and the fluorine diffusion suppression film is silicon-rich. It is a silicon nitride film.
[0013]
It is preferable that the fluorine diffusion suppression film is grown so that the thickness of the fluorine diffusion suppression film is within a range of 0.02 to 0.1 μm.
[0014]
In the present specification, a fluorine diffusion suppressing film that suppresses fluorine diffusion is referred to as a “cap layer”. In this specification, “material gas” refers to a reactive gas that contributes to film growth among gases used for plasma vapor deposition (plasma CVD), and includes, for example, a silicon oxide film and an SRO film. When forming, monosilane (SiH₄) When the gas becomes a material gas and a fluorine-doped silicon oxide film is formed, SiH₄Gas and silicon tetrafluoride (SiF₄) Gas becomes the material gas.
[0015]
Further, in this specification, “high density plasma” means plasma in which the bias RF is applied to the stage (electrode) to increase the electron density of the plasma after the bias RF is applied before the bias RF is applied. .
[0017]
DETAILED DESCRIPTION OF THE INVENTION
As a result of various studies, the present inventor has made SiH, which is a material gas, in the plasma CVD apparatus.₄It was found that a cap layer having a uniform thickness can be formed with good reproducibility by stopping the formation of plasma while the gas is supplied. Embodiments of a semiconductor device manufacturing method according to the present invention will be described below.
(First embodiment)
First, the wiring structure of the semiconductor device formed in this embodiment will be described with reference to FIG.
[0018]
The wiring structure shown in FIG. 1 is formed on a semiconductor substrate (not shown) on which semiconductor elements and the like are formed. More specifically, a first interlayer insulating film 1 is formed on a semiconductor substrate (not shown), and a second interlayer insulating film 3 is formed thereon. The first interlayer insulating film 1 and the second interlayer insulating film 3 are composed of ordinary silicon oxide films, and are formed by plasma CVD using tetraethylorthosilicate (TEOS) as a raw material.
[0019]
A first layer wiring 4 is formed on the first interlayer insulating film 1, and a second layer wiring 5 is formed on the second interlayer insulating film 3. The first layer wiring 4 and the second layer wiring 5 have a structure in which Al alloy layers 4b and 5b are formed on barrier metals 4a and 5a made of Ti / TiN.
[0020]
Between the first interlayer insulating film 1 and the second interlayer insulating film 3, a liner layer 6, a fluorine-doped silicon oxide film 2, and a cap layer 10 are formed. The liner layer 6 is made of a normal silicon oxide film, and is formed on the first interlayer insulating film 1 so as to cover the first layer wiring 4. A fluorine-doped silicon oxide film 2 is formed on the liner layer 6. On the fluorine-doped silicon oxide film 2, an SRO film functioning as the cap layer 10 is formed.
[0021]
FIG. 1 shows a semiconductor device having a two-layer wiring structure composed of a first layer wiring and a second layer wiring. However, the method for manufacturing a semiconductor device according to the present invention has a multilayer structure of three or more layers. It can also be applied to the manufacture of semiconductor devices.
[0022]
Next, a plasma vapor phase growth apparatus (plasma CVD apparatus) used for carrying out this embodiment will be described with reference to FIGS. 3 (a) and 3 (b). 3 (a) and 3 (b) are a cross-sectional view and a plan view of the device, respectively.
[0023]
This plasma CVD apparatus includes a ceramic dome 105 in the upper part and a throttle valve 106 and a turbo pump 107 in the lower part. A source radio frequency (RF) power supply coil 103 is wound around the outside of the ceramic dome 105. An electrostatic chuck 102 is provided in the ceramic dome 105, and a gas nozzle 104 is disposed so as to surround the electrostatic chuck 102. The gas nozzle 104 is made of SiH₄It is connected to a gas inlet 108 for introducing gas and argon (Ar) gas.
[0024]
The electrostatic chuck 102 is a stage (electrode) having a function of attracting the substrate by Coulomb force. After the semiconductor substrate 101 is installed on the electrostatic chuck 102, when a voltage is applied to the electrostatic chuck 102 (hereinafter, this voltage is referred to as “chucking voltage”), the semiconductor substrate 101 is opposite to the electrostatic chuck 102. Charge to charge. This charging causes a Coulomb force between the semiconductor substrate 101 and the electrostatic chuck 102, and the semiconductor substrate 101 is attracted to the electrostatic chuck 102.
[0025]
Since bias RF power can be applied to the electrostatic chuck 102, the electrostatic chuck also functions as a lower electrode. The electrostatic chuck 102 has a function of cooling the semiconductor substrate with helium (He). The electrostatic chuck 102 is provided with a recess (not shown), and an external pipe (not shown) for introducing He is connected to the recess. The semiconductor substrate 101 can be cooled by spraying He introduced into the recess from the opening (not shown) on the upper surface of the electrostatic chuck 102 onto the back surface of the semiconductor substrate 101. With this cooling function, the temperature rise of the semiconductor substrate 101 that occurs when bias RF power is applied to the electrostatic chuck 102 can be suppressed.
[0026]
When source RF power (2 MHz) is applied to the coil 103 from the outside of the ceramic dome 105, plasma can be formed in the ceramic dome 105. When source RF power is applied to the coil 103 and bias RF power (13.56 Mz) is applied to the electrostatic chuck 102, high-density plasma is formed in the ceramic dome 105. Sputter etching can be performed by applying bias RF power to the electrostatic chuck 102. By performing sputter etching, the corner portion of the fluorine-doped silicon oxide film 2 that is formed in an uneven shape reflecting the shape of the first layer wiring 4 can be embedded between the wirings.
[0027]
The throttle valve 106 and the turbo pump 107 control conditions such as gas pressure in the ceramic dome 105. The gas nozzle 104 is a SiH introduced from the gas inlet 108.₄Gas and Ar gas are distributed and supplied into the ceramic dome 105. SiF₄Gas and oxygen (O₂) Gas is supplied from another gas inlet, but is omitted in FIG.
[0028]
Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS. 4 to 6 in addition to FIGS. FIG. 4 is a process flow of this embodiment. The conditions for each step of the process flow shown in FIG.
[0029]
[Table 1]

In Table 1 above, a case where gas is supplied into the ceramic dome 105 of the plasma CVD apparatus, a case where RF power for forming plasma is applied, and the like are represented by “◯” marks, and other cases are expressed as “ It is represented as “×”. FIGS. 5A to 5G schematically show the film formation state in each step. FIG. 6 shows the gas flow rate for each step, the presence or absence of plasma formation, the presence or absence of a chucking voltage, and the presence or absence of backside He.
[0030]
First, as shown in FIG. 5A, a semiconductor substrate 101 in which a first wiring 4 is formed on a first interlayer insulating film 1 using a known technique is prepared. Next, the semiconductor substrate 101 is set on the electrostatic chuck 102 in the plasma CVD apparatus (substrate setting step S1).
[0031]
Next, as shown in FIG. 6A, Ar gas and O₂By introducing gas into the gas inlet 108, Ar gas and O are introduced into the ceramic dome 105 through the gas nozzle 104.₂Supply gas. Thereafter, as shown in FIG. 6B, the source RF power (2 MHz) is applied to the source RF power supply coil 103 to form plasma in the ceramic dome 105 (plasma formation step S2). The flow rate of Ar gas supplied into the ceramic dome 105 is, for example, 50 to 200 sccm, preferably 110 sccm.₂The gas flow rate is, for example, 30 to 200 sccm, preferably 30 sccm. Further, when plasma is formed in the ceramic dome 105, the pressure in the ceramic dome 105 is set within a range of 5 mTorr to 300 mTorr, for example.
[0032]
Next, as shown in FIG. 6C, a chucking voltage is applied to the electrostatic chuck 102 to bring the semiconductor substrate 101 and the electrostatic chuck 102 into an attracting state (substrate attracting step S3). The chucking voltage is applied until the material gas is supplied into the ceramic dome 105. It is not preferable to apply a chucking voltage after supplying the material gas, because film formation is performed on the back surface of the semiconductor substrate 101 and the like until the semiconductor substrate 101 and the electrostatic chuck 102 are in an attracted state. .
[0033]
Next, as shown in FIGS. 5A to 5B, a liner layer 6 is formed on the first interlayer insulating film 1 so as to cover the first layer wiring 4 (liner layer forming step S4). As shown in FIGS. 6 (a) and 6 (b), step 4 includes Ar gas and O₂SiH with plasma formed while gas supply continues₄This is done by supplying gas into the ceramic dome 105. SiH₄The gas flow rate is, for example, 10 to 100 sccm, preferably 36 sccm. As shown in FIG. 6A, Ar gas and O used in step S4.₂The gas flow rate is increased compared to the flow rates used in steps S2 and S3. The flow rate of Ar gas in step S4 is 126 sccm, O₂The gas flow rate is preferably 126 sccm. Step S4 is performed until the thickness of the liner layer 6 becomes 0.01 to 0.1 μm, for example.
[0034]
Next, as shown in FIGS. 5B to 5C, a fluorine-doped silicon oxide film (SiOF film) 2 is formed on the first interlayer insulating film 1 so as to cover the liner layer 6 (SiOF film formation). Step S5). As shown in FIGS. 6A and 6B, a bias RF (13.56 MHz) is applied to the electrostatic chuck 102 in a state where the source RF power is applied to the coil 103, and the ceramic dome 105 has a high density. While forming plasma, SiH₄Gas, Ar gas and O₂SiF with the gas supplied₄Step S5 is performed by supplying gas into the ceramic dome 105.
[0035]
The reason why high-density plasma is used in step S5 is to form a fluorine-doped silicon oxide film with good film quality. A fluorine-doped silicon oxide film with good film quality refers to a film that hardly dissociates fluorine and hardly adsorbs moisture. The electron density of the plasma in the ceramic dome 105 varies depending on the apparatus and conditions used, but the electron density of the plasma before applying the bias RF power is, for example, 10¹⁰-10¹¹cm^-3The electron density of the plasma (high density plasma) after applying the bias RF power is, for example, 10¹²-10¹³cm^-3Degree.
[0036]
In step S5, since the bias RF power is applied to the electrostatic chuck 102, the fluorine-doped silicon oxide film 2 can be embedded between the wirings. In order to suppress an increase in the substrate temperature due to the application of the bias RF power, He is introduced into the concave portion of the electrostatic chuck 102 as shown in FIG. The temperature of the semiconductor substrate 101 is controlled to be in the range of 400 to 500 ° C., for example.
[0037]
SiF in step S5₄The gas flow rate is, for example, 10 to 50 sccm, preferably 27.5 sccm. As shown in FIG. 6A, Ar gas and O in step S5₂The gas flow rate is decreased compared to the flow rate used in step S4. The flow rate of Ar gas in step S5 is 55 sccm, O₂The gas flow rate is preferably 92 sccm. SiH in step S5₄The gas flow rate is increased compared to the flow rate used in step S4. SiH in step S5₄The gas flow rate is, for example, 20 to 100 sccm, preferably 50 sccm.
[0038]
Step S5 is performed until the thickness of the fluorine-doped silicon oxide film 2 falls within the range of, for example, 0.3 to 0.8 μm. The fluorine-doped silicon oxide film 2 is preferably formed so that the fluorine concentration in the fluorine-doped silicon oxide film is in the range of 0.5 to 3.0 atomic%.
[0039]
Thereafter, as shown in FIG. 6B, the application of the bias RF power is stopped to change the state in which the normal plasma is formed from the state in which the high-density plasma is formed in the ceramic dome 105. SiF as shown in 6 (a)₄The supply of gas is stopped, whereby the growth of the fluorine-doped silicon oxide film 2 is stopped.
[0040]
As shown in FIG. 6D, when the application of the bias RF power is stopped, the introduction of He into the concave portion of the electrostatic chuck 102 is stopped. After the introduction of He is stopped, He in the concave portion of the electrostatic chuck 102 leaks into the ceramic dome 105, so that the pressure on the back surface of the semiconductor substrate 101 gradually decreases.
[0041]
Next, as shown in FIGS. 5C to 5D, the growth of the SRO film as the cap layer 10 is started (cap layer growth start step S6). Specifically, the flow rate is controlled so that an SRO film grows on the fluorine-doped silicon oxide film 2.₄Gas, Ar gas and O₂Gas is supplied to the ceramic dome 105. SiH in step 6₄As shown in FIG. 6A, the gas flow rate is not particularly changed compared to the flow rate used in step S5. SiH in step 6₄The gas flow rate is, for example, 20 to 100 sccm, preferably 50 sccm. Ar gas and O in step S6₂The gas flow rate is increased compared to the flow rate used in step S5. The flow rate of Ar gas in step 6 is 126 sccm, O₂The gas flow rate is preferably 126 sccm.
[0042]
The SRO film grown as a cap layer is preferably grown to have a refractive index of 1.48 or more, more preferably a refractive index of 1.48 to 1.60. Note that a normal silicon oxide film having a stoichiometric composition (SiO₂) Is 1.46, and the refractive index increases as the number of silicon (Si) in the SRO film increases.
[0043]
Next, as shown in FIGS. 5D to 5E, the growth of the cap layer 10 is stopped by stopping the formation of plasma (cap layer growth stop step S7). As shown in FIGS. 6A and 6B, the plasma formation is stopped by using SiH, which is a material gas.₄While supplying gas into the ceramic dome 105, the application of the source RF power is stopped.
[0044]
After stopping the formation of plasma, SiH₄Even if gas is supplied into the ceramic dome 105, the cap layer 10 does not grow. SiH by plasma₄Because the gas is not decomposed, SiH₄This is because the gas does not react with the surface of the semiconductor substrate. The thickness of the cap layer 10 is, for example, in the range of 0.02 to 0.1 μm, preferably about 0.06 μm.
[0045]
Next, as shown in FIGS. 5E to 5D, the material gas, SiH₄The gas supply is stopped (material gas stop step S8). SiH₄Even after the gas supply is stopped, the₄Since the gas remains, the SiH in the ceramic dome 105 continues.₄Gas will be supplied. However, since the formation of plasma has already been stopped in step S7, the SiH remaining in the gas pipe₄The cap layer 10 is not grown by the gas.
[0046]
Next, as shown in FIGS. 6A and 6B, Ar gas and O₂With the gas supplied, source RF power is applied to the coil 103 to form plasma again in the ceramic dome 105 (plasma re-forming step S9). The reason why the plasma is formed again is that the charge accumulated in the semiconductor substrate 101 cannot be neutralized only by stopping the application of the chucking voltage, and the adsorption state between the semiconductor substrate 101 and the electrostatic chuck 102 is not achieved. It is because it cannot be canceled. The reason for releasing the attracted state between the semiconductor substrate 101 and the electrostatic chuck 102 is that the semiconductor substrate 101 needs to be moved to another apparatus after the cap layer 10 is formed, as will be described later.
[0047]
Next, as shown in FIG. 6D, He existing on the back surface of the semiconductor substrate 101 is removed from the concave portion of the electrostatic chuck 102 (back surface He removing step S10). By stopping the introduction of He into the concave portion of the electrostatic chuck 102 before performing step 6, the pressure of He gradually decreases, but does not decrease to the pressure in the ceramic dome 105. Therefore, the pressure between the back surface of the semiconductor substrate 101 and the inside of the ceramic dome 105 is made the same by forcibly removing He existing in the concave portion of the electrostatic chuck 102 in step S10.
[0048]
Step S10 needs to be performed before the application of the chucking voltage is stopped. Unless He is removed before the application of the chucking voltage is stopped, the semiconductor substrate moves or detaches from the electrostatic chuck 102 due to a pressure difference between the ceramic dome 105 and the back surface of the semiconductor substrate 101. become.
[0049]
Next, as shown in FIGS. 6B and 6C, application of the chucking voltage is stopped in a state where plasma is formed in the ceramic dome 105 (chucking voltage stopping step S11). At this time, the charges accumulated in the semiconductor substrate 101 are neutralized by the plasma, and the adsorption state between the semiconductor substrate 101 and the electrostatic chuck 102 is released. Thereafter, as shown in FIG. 6B, the formation of plasma in the ceramic dome 105 is stopped by stopping the application of the source RF power (plasma stop step S12).
[0050]
Next, as shown in FIGS. 5F to 5G, in order to form the second interlayer insulating film 3 and the second wiring 5 on the cap layer 10, the semiconductor substrate 101 on the electrostatic chuck 102 is subjected to plasma. It is removed from the CVD apparatus and moved into another plasma CVD apparatus. The reason why the semiconductor substrate 101 is moved into another plasma CVD apparatus is that the manufacturing cost can be reduced by forming the second interlayer insulating film 3 and the second wiring 5 with another plasma CVD apparatus. Note that since the cap layer 10 made of the SRO film is not oxidized only by exposure to the atmosphere, the silicon-rich composition in the cap layer 10 does not change even when the semiconductor substrate 101 is exposed to the atmosphere.
[0051]
Thereafter, as shown in FIG. 5G, after the second interlayer insulating film 3 is formed on the cap layer 10 using a known technique in another plasma CVD apparatus, the second interlayer insulating film 3 is formed on the second interlayer insulating film 3. A two-layer wiring 5 is formed.
[0052]
FIG. 7 shows the ability of the cap layer formed by the semiconductor device manufacturing method of this embodiment to suppress fluorine diffusion. In FIG. 7, the fluorine concentration at each depth of the semiconductor substrate is compared by the presence or absence of a cap layer by secondary ion mass spectrometry (SIMS), and an SRO film having a thickness of 0.06 μm is used as the cap layer. It is formed on (SiOF film). When a cap layer is used, SiO formed in the upper layer compared to the case where no cap layer is used₂It can be seen that the amount of fluorine diffused into the (second interlayer insulating film) is small.
[0053]
In the first embodiment, the SRO film is grown as a cap layer on the fluorine-doped silicon oxide film. However, instead of the SRO film, a silicon-rich silicon nitride film (hereinafter referred to as “SRN film”) is used as the cap layer. It may be grown. In this specification, the “SRN film” is a silicon nitride (Si) having a stoichiometric composition.₃N₄) Means a silicon nitride film containing more Si atoms than the number of Si atoms in it.
[0054]
Even when an SRN film is used as the cap layer, fluorine can be captured by silicon atoms having dangling bonds present in the SRN film, and fluorine diffusion can be suppressed. When the SRN film is grown, the density of the SRN film is larger than that of the SRO film (Si₃N₄: 2.7 g / cm³, SiO₂: 2.3 g / cm³) Since the film is dense, fluorine diffusion can be suppressed more than the SRO film. The refractive index of the SRN film grown as the cap layer is, for example, 2.05 or more, preferably 2.05 to 2.1.
[0055]
In the above embodiment, the semiconductor substrate is used as the substrate to be processed on which the first interlayer insulating film is formed, but another substrate (for example, a glass substrate) may be used. Semiconductor devices in which thin film transistors are formed on a glass substrate or other substrates may be increasingly integrated in the future, and the application of the present invention to the manufacture of such semiconductor devices has a very favorable effect. Be expected. The “semiconductor device” in this specification is not limited to one having a semiconductor substrate as an indispensable element.
[0056]
In addition, the manufacturing method according to the first embodiment of the present invention is used not only when a cap layer having a uniform thickness is formed with good reproducibility, but also by reproducing a thin film having a uniform thickness using a plasma CVD method. It can be applied to the case of forming well. That is, when a thin film is formed by adsorbing a substrate to an electrostatic chuck for reasons such as using high-density plasma, if the formation of plasma is stopped while supplying a material gas for growing the thin film, a uniform film is obtained. A thin film can be formed with good reproducibility. As a film formed using high-density plasma, for example, there is a normal silicon oxide film to which fluorine is not added, in addition to a fluorine-doped silicon oxide film.
(Comparative example)
A comparative example different from the method for manufacturing the semiconductor device according to the first embodiment in that the growth of the cap layer is stopped by stopping the supply of the material gas will be described. Similar to the manufacturing method of the first embodiment, the manufacturing method of the comparative example is also used to manufacture the wiring structure shown in FIG. 1 using the apparatus of FIG. In the following, processes different from those of the first embodiment will be mainly described, and description of other processes will be omitted. Note that, unlike the first embodiment, the manufacturing method of the comparative example does not require plasma re-formation because plasma formation is not stopped during the process.
[0057]
First, a process flow of a semiconductor device manufacturing method according to a comparative example will be described with reference to FIG. The process flow of the comparative example is executed according to the conditions shown in Table 2 below.
[0058]
[Table 2]

In Table 2, as in Table 1, the case where gas is supplied into the ceramic dome 105, the case where RF power for forming plasma is applied to the coil 103, etc. are represented as “O” marks, so When it is not, it is represented as an “x” mark.
[0059]
In step S <b> 101, the substrate 101 is set on the electrostatic chuck 102.
[0060]
In step S102, plasma is formed in the ceramic dome 105.
[0061]
In step S103, a chucking voltage is applied to the electrostatic chuck 102 to bring the semiconductor substrate 101 and the electrostatic chuck 102 into an attracting state.
[0062]
In step S104, the liner layer 6 is formed.
[0063]
In step S105, a fluorine-doped silicon oxide film (SiOF) 2 is formed.
[0064]
In step S106, growth of the cap layer 10 is started.
[0065]
In step S107, the material gas (SiH₄) Is stopped, the growth of the cap layer 10 is stopped.
[0066]
In step S108, He existing in the concave portion of the electrostatic chuck 102 is removed.
[0067]
In step S109, application of the chucking voltage is stopped.
[0068]
In step S110, the formation of plasma in the ceramic dome 105 is stopped.
[0069]
In the manufacturing method of the comparative example, the order in which the formation of plasma is stopped in step S110 after the supply of the material gas is stopped in step S107 is adopted. The reason is that once the plasma formation is stopped as in the manufacturing method of the first embodiment, the plasma must be re-formed in order to remove the semiconductor substrate 101 from the electrostatic chuck 102 (step S9 in FIG. 4). This is because the film forming process takes a long time and the throughput decreases.
[0070]
The present inventor has found that a cap layer having a uniform thickness cannot be formed with good reproducibility by the manufacturing method of the comparative example in which high throughput is prioritized. The cause is the material gas remaining in the gas pipe (SiH₄This is because a film is additionally formed on the cap layer 10 by the gas). Details will be described with reference to FIGS.
[0071]
FIGS. 9A to 9D schematically show film formation states in steps S105 to S106. First, as shown in FIGS. 9A to 9B, SiH, which is a material gas, in the ceramic dome 105.₄The cap layer 10 is grown on the fluorine-doped silicon oxide film 2 while supplying the gas.
[0072]
Next, as shown in FIGS. 9B to 9C, SiH introduced into the gas inlet 108 for the purpose of stopping the growth of the cap layer 10.₄Stop supplying gas. However, SiH₄Even after the gas supply is stopped, the₄Gas remains. SiH remaining in this gas pipe₄Gas 20 is SiH₄Even after the gas supply is stopped, the gas continues to diffuse into the ceramic dome 105.
[0073]
SiH₄Since the plasma is formed in the ceramic dome 105 when the gas supply is stopped, the SiH remaining in the gas pipe as shown in FIG.₄The gas 20 is decomposed by plasma and reacts with the cap layer 10 which is the surface of the semiconductor substrate 101. As a result, as shown in FIG. 9D, since the SRO film 21 is additionally formed, the manufacturing method of the comparative example cannot form a uniform cap layer with good reproducibility.
[0074]
Moreover, in the manufacturing method of a comparative example, the problem based on the plasma CVD apparatus to be used also occurs. This problem will be described with reference to FIGS. 10 (a) to 10 (c). FIG. 10A shows a material gas (SiH) near the lower left of the semiconductor substrate 101.₄1 schematically shows a plasma CVD apparatus provided with a gas inlet 108 of gas. In this apparatus, only one gas inlet 108 is provided at an asymmetrical position with respect to the semiconductor substrate 101. Therefore, when the supply of the material gas is stopped in step S106, the SiH in the ceramic dome 105 with time elapses.₄The partial pressure of gas will be biased. As shown in FIG. 10A, the lower left portion (I) (near the gas inlet) of the semiconductor substrate 101 is more SiH than the upper right portion (II).₄The partial pressure of the pressure decreases as time passes.
[0075]
Thus SiH₄10 (b) and (c), the upper right part (II) is formed thicker in the upper right part (II) than the lower left part (I), as shown in FIGS. . Therefore, it becomes difficult to form the cap layer 10 having a uniform thickness by the manufacturing method of the comparative example. This SiH₄The problem that the partial pressure of the gas is uneven may occur even when the length of the gas pipe is different in one plasma CVD apparatus.
[0076]
In the case of using a plurality of plasma CVD apparatuses at the time of mass production, when the supply of the material gas is stopped in step S106, the SiH between each apparatus₄There may be a difference in the partial pressure of the gas. Specifically, when the length of the gas piping of the material gas connected to each device is different, or when the length of the exhaust piping of the vacuum pump and the piping resistance are different, there is a difference in the exhaust capacity of each device Or when the gas exhaust capacity in each device fluctuates. In such a case, the manufacturing method of the comparative example may cause a problem that the thickness of the cap layer formed is different for each device.
[0077]
In the method of manufacturing a semiconductor device according to the first embodiment, after the formation of plasma is stopped, SiH₄Even when gas is supplied into the ceramic dome 105, the cap layer 10 does not grow. Therefore, after the formation of plasma is stopped, SiH in the substrate surface₄Even if the partial pressure is uneven, the thickness of the cap layer does not change.
[0078]
In the manufacturing method according to the first embodiment, even when the evacuation capability of the vacuum pumps in the plurality of plasma CVD apparatuses is different for each apparatus, when the cap layer is grown, the gas amount is increased by the mass flow controller or the pressure gauge. SiH between each device because it is controlled₄The problem of difference in partial pressure does not occur. After the plasma formation is stopped, the SiH between the devices is different due to the difference in exhaust capability in each device.₄Even if a difference in gas partial pressure occurs, the thickness of the cap layer is not affected. Therefore, the manufacturing method of the first embodiment does not cause a problem as in the manufacturing method of the comparative example.
[0079]
【The invention's effect】
According to the method for manufacturing a semiconductor device of the present invention, a fluorine diffusion suppressing film having a uniform thickness can be formed with good reproducibility. When there is a wiring above the fluorine-doped silicon oxide film, fluorine diffusion from the fluorine-doped silicon oxide film can be suppressed by the fluorine diffusion suppression film, so that the Ti barrier metal etc. contained in the wiring and the interlayer insulating film It is possible to prevent the deterioration of the adhesion between them with good reproducibility. As a result, the reliability of the semiconductor device can be improved.
[0080]
When the fluorine diffusion suppression film is grown so that the thickness of the fluorine diffusion suppression film is in the range of 0.02 to 0.1 μm, the fluorine diffusion suppression film can suppress fluorine diffusion from the fluorine-doped silicon oxide film. The via hole can be formed without deteriorating the shape of the via hole. When an SRO film is grown as a fluorine diffusion suppression film, fluorine can be captured by silicon atoms having dangling bonds present in the SRO film, and fluorine diffusion can be suppressed. Further, when the SRN film is grown as the fluorine diffusion suppressing film, the density of the SRN film is larger than that of the SRO film, and therefore, fluorine diffusion can be suppressed as compared with the SRO film.
[0081]
According to the thin film forming method of the present invention, a thin film having a uniform thickness can be formed with good reproducibility.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view for explaining a wiring structure of a semiconductor device having a cap layer (SRO film) on a fluorine-doped silicon oxide film.
FIG. 2 is a cross-sectional view for explaining a wiring structure of a conventional semiconductor device provided with a fluorine-doped silicon oxide film.
FIG. 3A is a cross-sectional view of a plasma CVD apparatus. (B) It is a top view of a plasma CVD apparatus.
FIG. 4 is a process flow for explaining a semiconductor manufacturing method according to the first embodiment;
FIGS. 5A to 5G are views for explaining film forming states in main steps in the semiconductor device manufacturing method according to the first embodiment; FIGS.
6A is a diagram for explaining a change in the flow rate of gas supplied into a ceramic dome. FIG. (B) It is a figure for demonstrating the presence or absence of plasma formation. (C) It is a figure for demonstrating the presence or absence of a chucking voltage. (D) It is a figure for demonstrating the pressure of He introduced into the back surface of a semiconductor substrate.
FIG. 7 is a diagram comparing the relationship between the depth of an interlayer insulating film and the fluorine concentration with and without a cap layer (SRO film).
FIG. 8 is a process flow for explaining a method for manufacturing a semiconductor device according to a comparative example;
FIGS. 9A to 9D are views for explaining a method for manufacturing a semiconductor device according to a comparative example; FIGS.
FIGS. 10A to 10C are views for explaining that a cap layer (SRO film) has a non-uniform thickness. FIG.
[Explanation of symbols]
1 First interlayer insulating film
2 Fluorine-doped silicon oxide film (SiOF)
3 Second interlayer insulating film
4 First layer wiring
4a First layer wiring (TiN / Ti)
4b First layer wiring (TiN / Al)
5 Second layer wiring
5a Second layer wiring (TiN / Ti)
5b Second layer wiring (TiN / Al)
6 Liner layer (silicon oxide film)
10 Cap layer (SRO membrane)
11 First interlayer insulating film
12 Fluorine-doped silicon oxide film
13 Second interlayer insulating film
14 First layer wiring
15 Second layer wiring
14a, 15a TiN / Ti layer
14b, 15b Al alloy layer
20 Residual SiH₄gas
21 Additional formed films
101 Semiconductor substrate
102 Electrostatic chuck
103 source RF coil
104 gas nozzle
105 ceramic dome
106 Throttle valve
107 turbo pump
108 Gas inlet (SiH₄, Ar)

Claims (3)

Installing a substrate in a plasma vapor deposition apparatus;
Forming a fluorine-doped silicon oxide film on the substrate using high-density plasma;
Fluorine diffusion using plasma while supplying a material gas for growing a fluorine diffusion suppressing film that suppresses fluorine diffusion into the plasma vapor deposition apparatus while the substrate is installed in the plasma vapor deposition apparatus. Starting the growth of the suppression film;
Stopping the growth of the fluorine diffusion suppression film by stopping the formation of the plasma while supplying the material gas;
Including
The method for manufacturing a semiconductor device, wherein the fluorine diffusion suppression film is a silicon-rich silicon oxide film. Installing a substrate in a plasma vapor deposition apparatus;
Forming a fluorine-doped silicon oxide film on the substrate using high-density plasma;
Fluorine diffusion using plasma while supplying a material gas for growing a fluorine diffusion suppressing film that suppresses fluorine diffusion into the plasma vapor deposition apparatus while the substrate is installed in the plasma vapor deposition apparatus. Starting the growth of the suppression film;
Stopping the growth of the fluorine diffusion suppression film by stopping the formation of the plasma while supplying the material gas;
Including
The method for manufacturing a semiconductor device, wherein the fluorine diffusion suppression film is a silicon-rich silicon nitride film. The method of manufacturing a semiconductor device according to claim 1 or 2 thickness of the fluorine diffusion suppression film growing said fluorine diffusion suppression film to be within a range of 0.02 to 0.1 [mu] m.

Images