KR20070038332A - Liquid crystal display - Google Patents

Abstract

A liquid crystal display device is provided which improves the aperture ratio while widening the reference viewing angle. The liquid crystal display device includes a gate line and a first coupling electrode formed on an insulating substrate, a data line formed on the insulating substrate and insulated from the gate line and the first coupling electrode, a thin film transistor, a thin film transistor connected to the gate line and the data line and formed for each pixel; A first subpixel electrode electrically connected to the first coupling electrode, a second coupling electrode formed between the first coupling electrode and the first subpixel electrode and capacitively coupled to the first coupling electrode and the first subpixel electrode, respectively. And a second subpixel electrode formed to be spaced apart from the first subpixel electrode and electrically connected to the second coupling electrode.

LCD, Opening Ratio, Coupling Electrode

Description

Liquid crystal display

1A is a layout view of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 1B is a cross-sectional view taken along the line Ib-Ib ′ of the thin film transistor substrate of FIG. 1A.

FIG. 1C is a cross-sectional view of the thin film transistor substrate of FIG. 1A taken along the line Ic-Ic ′.

2 is a layout view of a common electrode substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a layout view of a liquid crystal display according to an exemplary embodiment of the present invention including a thin film transistor substrate and a common electrode substrate.

4 is an equivalent circuit diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

5A is a layout view of a thin film transistor substrate for a liquid crystal display according to another exemplary embodiment of the present invention.

5B is a cross-sectional view of the thin film transistor substrate of FIG. 5A taken along the line Vb-Vb ′.

6 is a layout view of a liquid crystal display according to another exemplary embodiment including a thin film transistor substrate and a common electrode substrate.

7 is an equivalent circuit diagram of a liquid crystal display according to another exemplary embodiment of the present invention.

8A is a layout view of a thin film transistor substrate for a liquid crystal display according to another exemplary embodiment of the present invention.

FIG. 8B is a cross-sectional view of the thin film transistor substrate of FIG. 8A taken along the line VIIIb-VIIIb ′.

9 is a layout view of a liquid crystal display according to another exemplary embodiment including a thin film transistor substrate and a common electrode substrate.

10 is an equivalent circuit diagram of a liquid crystal display according to another exemplary embodiment of the present invention.

(Explanation of symbols about main parts of drawing)

22: gate line 24: gate pad

25: first coupling electrode 26: gate electrode

28: sustain electrode line 29: sustain electrode

40: semiconductor layer 62: data line

63: second coupling electrode 65: source electrode

66: drain electrode 67: coupling electrode

68: data pad 73, 75, 76, 78: contact hole

82: pixel electrode 82a: first subpixel electrode

82b: second subpixel electrode 83: gap

84: incision 86: auxiliary gate pad

88: auxiliary data line pad

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device for improving aperture ratio while widening a reference viewing angle.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two substrates on which a field generating electrode such as a pixel electrode and a common electrode are formed, and a liquid crystal layer interposed therebetween. Is applied to generate an electric field in the liquid crystal layer, thereby determining the orientation of liquid crystal molecules in the liquid crystal layer and controlling the polarization of incident light to display an image.

Among them, the vertical alignment mode liquid crystal display in which the long axes of the liquid crystal molecules are arranged perpendicular to the upper and lower substrates without an electric field applied thereto, has gained much attention due to its large contrast ratio and easy implementation of a wide reference viewing angle. Here, the reference viewing angle refers to a viewing angle having a contrast ratio of 1:10 or a luminance inversion limit angle between gray levels.

Means for implementing a wide viewing angle in a vertical alignment mode liquid crystal display include a method of forming a cutout in the field generating electrode and a method of forming a protrusion on the field generating electrode. As described above, since one pixel is divided into a plurality of domains by using cutouts or protrusions, a direction in which the liquid crystal molecules are inclined by the cutouts or protrusions may be used to disperse the inclination directions of the liquid crystal molecules in various directions. The reference viewing angle can be widened.

In addition, a liquid crystal display of a domain division method for grouping such domains and applying different data voltages to each domain group has been developed. In particular, liquid crystal displays have been developed in which one pixel is divided into two or more domain groups to apply different data voltages using coupling of coupling electrodes between each domain group.

However, since the coupling electrode is formed on the pixel, the aperture ratio of the liquid crystal display is reduced, thereby causing a problem of decreasing luminance.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a liquid crystal display device which prevents a decrease in aperture ratio while widening a reference viewing angle.

The technical problem of the present invention is not limited to the technical problem mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

In order to achieve the above technical problem, a liquid crystal display according to an exemplary embodiment includes a gate line and a first coupling electrode formed on an insulating substrate, and a data line insulated from the gate line and the first coupling electrode on the insulating substrate. And a first subpixel electrode electrically connected to the thin film transistor, the thin film transistor, and the first coupling electrode connected to the gate line and the data line, respectively, the first coupling electrode and the first subpixel electrode. A second coupling electrode and a second coupling electrode spaced apart from each other and capacitively coupled to the first coupling electrode and the first subpixel electrode, respectively, and electrically connected to the second coupling electrode. And a second subpixel electrode.

In order to achieve the above technical problem, a liquid crystal display according to another exemplary embodiment of the present invention includes a gate line and a first coupling electrode formed on an insulating substrate, and data formed by being insulated from the gate line and the first coupling electrode on the insulating substrate. A thin film transistor connected to a line, the gate line and the data line and formed for each pixel, a first subpixel electrode electrically connected to the thin film transistor, between the first coupling electrode and the first subpixel electrode, A second coupling electrode electrically connected to the thin film transistor, the second coupling electrode coupled capacitively to the first subpixel electrode, and the first subpixel electrode, and spaced apart from each other; And a second subpixel electrode that is electrically connected.

Specific details of other embodiments are included in the detailed description and the drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings.

However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the present embodiments make the disclosure of the present invention complete, and those skilled in the art to which the present invention pertains. It is provided to fully inform the person having the scope of the invention, which is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

Hereinafter, a liquid crystal display and a manufacturing method thereof according to a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

First, a thin film transistor substrate will be described in detail with reference to FIGS. 1A to 1C.

1A is a layout view of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment. FIG. 1B is a cross-sectional view of the thin film transistor substrate of FIG. 1A taken along line Ib-Ib ′, and FIG. 1C is a cross-sectional view of FIG. 1A. It is sectional drawing which cut | disconnected the thin film transistor substrate along the line Ic-Ic '.

The gate line 22 is formed in the horizontal direction on the insulating substrate 10, and the gate electrode 26 formed in the form of a protrusion is formed on the gate line 22. At the end of the gate line 22, a gate pad 24 is formed to receive a gate signal from another layer or the outside and transmit the gate signal to the gate line 22, and the gate pad 24 is connected to an external circuit. The width is extended. The gate line 22, the gate electrode 26, and the gate pad 24 are referred to as gate wirings.

In addition, on the insulating substrate 10, a storage electrode line 28 extending in the horizontal direction substantially in parallel with the gate line 22 is formed. The sustain electrodes 29a and 29b branched from the sustain electrode lines 28 are formed along the edges of the pixels in the pixels. The sustain electrodes 29a and 29b may extend from the sustain electrode line 28 along the data line 62 to overlap the first and second subpixel electrodes 82a and 82b. The sustain electrode lines 28 and the sustain electrodes 29a and 29b are referred to as sustain electrode wirings.

In order to increase the aperture ratio of the liquid crystal display, the sustain electrode wirings 28, 29a, and 29b are formed along the edge of the pixel. However, the present invention is not limited thereto, and the first subpixel electrode 82a and the second subpixel electrode are not limited thereto. The shape and arrangement of the sustain electrode wirings 28, 29a, 29b can be modified in various forms within a range that satisfies 82b and the condition for forming a constant holding capacitor.

The first coupling electrode 25 is an electrode which forms a coupling capacitance Ca with the second coupling electrode 63, which will be described later, and the sustain electrode 29b to secure the opening ratio in the same layer as the gate wirings 22, 24, and 26. It can be formed side by side adjacent to). The first coupling electrode 25 may be formed of the same material as the gate lines 22, 24, and 26 and the storage electrode lines 28, 29a, and 29b to simplify the manufacturing process. In the exemplary embodiment of FIG. 1A, the first coupling electrode may be formed adjacent to the sustain electrode wiring, but the present invention is not limited thereto. The shape and arrangement of the first coupling electrode may vary in a range that satisfies a condition for forming a constant coupling capacitance with the second coupling electrode. It can be changed to form.

The gate wirings 22, 24, 26, the sustain electrode wirings 28, 29a, and 29b and the first coupling electrode 25 may be made of aluminum-based metals such as aluminum (Al) and aluminum alloys, silver (Ag), and silver alloys. It may be made of a silver-based metal, copper-based metals such as copper (Cu) and copper alloys, molybdenum-based metals such as molybdenum (Mo) and molybdenum alloys, chromium (Cr), titanium (Ti), tantalum (Ta), and the like. . In addition, the gate wirings 22, 24, 26, sustain electrode wirings 28, 29a, and 29b and the first coupling electrode 25 may have a multi-layer structure including two conductive films (not shown) having different physical properties. Can have One of the conductive films has a low resistivity metal so as to reduce signal delay or voltage drop of the gate wirings 22, 24, 26, sustain electrode wirings 28, 29a, and 29b, and the first coupling electrode 25. For example, it consists of an aluminum type metal, a silver type metal, a copper type metal. In contrast, the other conductive film is made of another material, in particular, a material having excellent contact properties with the above-described metal, such as molybdenum-based metal, chromium, titanium, tantalum and the like. A good example of such a combination is a chromium bottom film and an aluminum top film and an aluminum bottom film and a molybdenum top film. However, the present invention is not limited thereto, and the gate wirings 22, 24, 26, the sustain electrode wirings 28, 29a, and 29b, and the first coupling electrode 25 may be made of various metals and conductors. .

A gate insulating film 30 is formed on the gate wirings 22, 24, 26, sustain electrode wirings 28, 29a, and 29b and the first coupling electrode 25.

On the gate insulating film 30, a semiconductor layer 40 made of hydrogenated amorphous silicon, polycrystalline silicon, or the like is formed. The semiconductor layer 40 may have various shapes such as an island shape and a linear shape. For example, the semiconductor layer 40 may be formed in an island shape on the gate electrode 26 as in the present embodiment. In addition, when the semiconductor layer 40 is linearly formed, the semiconductor layer 40 may be positioned below the data line 62 and extend to the upper portion of the gate electrode 26.

Resistive contact layers 55 and 56 made of a material such as n + hydrogenated amorphous silicon doped with silicide or n-type impurities at a high concentration are formed on the semiconductor layer 40. The ohmic contacts 55 and 56 may have various shapes such as islands and linear shapes. For example, in the case of the islands of ohmic contact layers 55 and 56, the drain electrode 66 and the source electrode may have different shapes. Located below 65, the linear ohmic contact layer may extend below the data line 62.

The data line 62 and the drain electrode 66 are formed on the ohmic contacts 55 and 56 and the gate insulating layer 30. The data line 62 extends long and crosses the gate line 22 to define a pixel. The source electrode 65 extending from the data line 62 to the top of the semiconductor layer 40 in the form of a branch is formed. A data pad 68 is formed at the end of the data line 62 to receive a data signal from another layer or the outside and transmit the data signal to the data line 62. The data pad 68 is connected to an external circuit. The width is extended. The drain electrode 66 is separated from the source electrode 65 and positioned above the semiconductor layer 40 so as to face the source electrode 65 with respect to the gate electrode 26.

The data line 62, the data pad 68, the source electrode 65, and the drain electrode 66 are referred to as data wirings.

The second coupling electrode 63 is formed to overlap a portion of the first coupling electrode 25 separately in the same layer as the data lines 62, 65, 66, 67, and 68. The second coupling electrode 63 is not only an electrode forming the coupling capacitor Ca with the first coupling electrode 25 but also an electrode forming the coupling capacitor Cb with the first subpixel electrode 82a described later. . A detailed description of this binding capacity will be given later. The second coupling electrode 63 may be formed of the same material as the data lines 62, 65, 66, 67, and 68 to simplify the manufacturing process.

The data wires 62, 65, 66, 67, 68 and the second coupling electrode 63 are preferably made of refractory metals such as chromium, molybdenum-based metals, tantalum and titanium, and a lower layer such as refractory metals (not shown). ) And a low resistance material upper layer (not shown) disposed thereon. Examples of the multilayer film structure include a triple film of molybdenum film, aluminum film, and molybdenum film in addition to the above-described double film of chromium lower film and aluminum upper film or aluminum lower film and molybdenum upper film.

The source electrode 65 overlaps at least a portion of the semiconductor layer 40, and the drain electrode 66 faces the source electrode 65 around the gate electrode 26 and at least partially overlaps the semiconductor layer 40. do. Here, the ohmic contacts 55 and 56 are interposed between the semiconductor layer 40 and the source electrode 65, and the semiconductor layer 40 and the drain electrode 66 to lower the contact resistance therebetween.

A passivation layer 70 made of an insulating layer is formed on the data line 62, the drain electrode 66, the second coupling electrode 63, and the exposed semiconductor layer 40. The protective film 70 is made of an inorganic material made of silicon nitride or silicon oxide. In addition, the passivation layer 70 may have a double layer structure of the lower inorganic layer and the upper organic layer in order to protect the exposed portion of the semiconductor layer 40 while maintaining excellent characteristics of the organic layer.

In the passivation layer 70, contact holes 73, 76, and 78 exposing the second coupling electrode 63, the drain electrode 66, and the data pad 68, respectively, are formed, and the passivation layer 70 and the gate insulating layer 30 are formed. ), Contact holes 75 and 74 exposing the first coupling electrode 25 and the gate pad 24 are formed.

In addition, an auxiliary gate pad 86 and an auxiliary data pad 88 connected to the gate pad 24 and the data pad 68 are formed on the passivation layer 70 through the contact holes 74 and 78, respectively. In addition, a contact hole 77 exposing the sustain electrode wirings 28, 29a, and 29b is formed in the passivation layer 70, and is disposed in the pixel region adjacent to each other through the contact hole 77 on the passivation layer 70. The connection member 84 which connects the sustain electrode wirings 28, 29a, and 29b is formed. The auxiliary gate line and the data pads 86 and 88 serve to bond the gate pad 24 and the data pad 68 to an external device.

The pixel electrode 82 is formed on the passivation layer 70 along the shape of the pixel. The pixel electrode 82 is formed of a first subpixel electrode 82a and a second subpixel electrode separated by a predetermined gap 83 that forms about 45 degrees or -45 degrees with the transmission axis 1 of the polarizing plate. (82b). Here, the gap 83 includes a portion that is substantially 45 degrees with the transmission axis 1 of the polarizing plate and a portion that is -45 degrees. Here, the second subpixel electrode 82b has a substantially rotated V shape and is disposed in the center of the pixel area, and overlaps a portion of the first coupling electrode 25. The first subpixel electrode 82a is formed at a portion of the pixel region except for the second subpixel electrode 82b and overlaps the portion of the first coupling electrode 25 and the second coupling electrode 63. Here, a plurality of cutouts (not shown) or protrusions (not shown) are formed in the gap 83 and the first and second subpixel electrodes 82a and 82b in an oblique direction, and before the first and second subpixels. The poles 82a and 82b may be formed with a plurality of cutouts (not shown) or protrusions (not shown) shown in the drawing in an oblique direction. The display area of the pixel electrode 82 is divided into a plurality of domains according to a direction in which the main directors of the liquid crystal molecules included in the liquid crystal layer are arranged when an electric field is applied, and such domain division means such as cutouts or protrusions are arranged in the pixel electrode 82. ) Split into more domains. In the embodiment of FIG. 1A, the second subpixel electrode 82b is formed by overlapping only the first coupling electrode 25, but the second subpixel electrode 82b is contacted on the first coupling electrode 25. The second coupling electrode 63 may overlap except the portion where the hole 73 is to be formed.

The first subpixel electrode 82a is not only electrically connected to the drain electrode 66 through the contact hole 76 but also electrically connected to the first coupling electrode 25 through the contact hole 73. The second subpixel electrode 82b is electrically connected to the second coupling electrode 63 through the contact hole 75. In the exemplary embodiment of the present invention, the contact hole 73 and the contact hole 76 are separated from each other, but the contact hole 76 is replaced with the contact hole 73 exposing a part of the drain electrode 66. The gate insulating layer 30 on the first coupling electrode 82a may be removed to be electrically connected.

Here, the respective coupling capacitances Ca and Cb of the second coupling electrode 63 and the first coupling electrode 25 and the first subpixel electrode 82a will be described. As shown in FIG. 1C, since the first coupling electrode 25 and the first subpixel electrode 82a are electrically connected through the contact hole 73, the first coupling electrode 25 is disposed below the first coupling electrode 63. The first subpixel electrode 82a on the coupling electrode 25 and the second coupling electrode 63 surrounds the second coupling electrode 63 with a letter “C”. That is, the coupling between the second coupling electrode 63 and the first coupling electrode 25 and between the second coupling electrode 63 and the first subpixel electrode 82a, respectively, with the second coupling electrode 63 as the center. Capacities Ca and Cb are formed, and since the first coupling electrode 25 and the first subpixel electrode 82a are electrically connected, their coupling capacitances Ca and Cb are connected in parallel. That is, in the second subpixel electrode 82b, two coupling capacitors Ca and Cb are connected in parallel to form a capacitive coupling Ccp1 with the first pixel electrode 82a. Since their coupling capacities Ccp1 are connected in parallel, the total coupling capacities Ccp1 become the sum of their coupling capacities Ca and Cb, so that one coupling electrode is used at the same coupling capacities Ccp1. In this case, the areas of the first and second coupling electrodes 25 and 63, which are the respective electrodes forming the coupling capacitors Ca and Cb, may be reduced. Therefore, the aperture ratio of the liquid crystal display device can be improved, and the luminance can be increased. A detailed description thereof will be described later with reference to FIG. 4. In addition, the second coupling electrode 63 is electrically connected to the second subpixel electrode 82b, and the second subpixel electrode 82b is connected to the first subpixel electrode 82a and the first subpixel electrode through the drain electrode 66. The predetermined voltage different from the voltage applied to the drain electrode 66 is formed by the second coupling electrode 63 in which the voltage applied to the first coupling electrode 25 is capacitively coupled.

The first subpixel electrode 82a is physically and electrically connected to the drain electrode 66 through the contact hole 76 to receive a data voltage from the drain electrode 66. In addition, the first coupling electrode 25 receives a voltage applied to the first subpixel electrode 82a through the contact hole 73. The second subpixel electrode 82b is in an electrically floating state, but the first subpixel electrode 82a and the first coupling connected to the first subpixel electrode 82a are electrically connected to the drain electrode 66. As described above, the electrode 25 overlaps the first subpixel electrode 82a and the first coupling electrode 25 in capacitive coupling in parallel. That is, the voltage of the second subpixel electrode 82b is changed by the voltage applied to the first subpixel electrode 82a and the first coupling electrode 25 connected thereto. At this time, the voltage of the second subpixel electrode 82b is always lower than the voltage of the first subpixel electrode 82a. The voltages applied to the first subpixel electrode 82a and the second subpixel electrode 82b are not limited thereto, and a data voltage is applied to the second subpixel electrode 82b from the drain electrode 66. The subpixel electrode 82a may be capacitively coupled to the second subpixel electrode 82b. Here, the coupling relationship between the first subpixel electrode 82a and the second subpixel electrode 82b will be described in detail later with reference to FIG. 4.

As such, when two subpixel electrodes 82a and 82b having different data voltages are disposed in one pixel, the two subpixel electrodes 82a and 82b compensate for each other to reduce the distortion of the gamma curve, thereby widening the reference viewing angle. .

The pixel electrode 82, the auxiliary gate pad 86, the auxiliary data pad 88, and the connection member 84 may be formed of a transparent conductor such as ITO or IZO or a reflective conductor such as aluminum.

An alignment layer (not shown) may be coated on the pixel electrode 82, the auxiliary gate line, the data pads 86 and 88, and the passivation layer 70.

Hereinafter, a common electrode substrate for a liquid crystal display according to an exemplary embodiment and a liquid crystal display including the same will be described with reference to FIGS. 2 to 3B. 2 is a layout view of a common electrode substrate for a liquid crystal display according to an exemplary embodiment of the present invention. 3A is a layout view of a liquid crystal display including the thin film transistor substrate of FIG. 1A and the common electrode substrate of FIG. 2. 3B is a cross-sectional view of the liquid crystal display of FIG. 3A taken along line IIIb-IIIb '.

2 to 3B, a black matrix 94 for preventing light leakage and an red, green, and blue color filter sequentially arranged on a pixel on an insulating substrate 96 made of a transparent insulating material such as glass ( 98 is formed, and a common electrode 90 having a cutout 92 is formed on the color filter 98 and is made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). . Here, the cutout 92 has a notch 91 having a concave chamfer shape. The notch 91 may have a triangular or square shape or a trapezoidal shape or a semicircular shape, and the liquid crystal is arranged at the boundary of the domain. Molecules can be arranged stably and regularly through the notch 91 to prevent staining or afterimage at the domain boundary.

The common electrode 90 faces the pixel electrode 82 and has a cutout 92 that is inclined at about 45 degrees or -45 degrees with respect to the transmission axis 1 of the polarizing plate. A protrusion may be formed at the position of the cutout 92, and the cutout 92 or the protrusion is called a domain dividing means.

An anti-corrosion film (not shown) may be coated on the common electrode 90 to align the liquid crystal molecules.

As illustrated in FIG. 3, the cutout 92 of the common electrode 90 may be alternately arranged with a gap 83 that divides the pixel electrode 82.

When the thin film transistor substrate 200 and the common electrode substrate 100 having such a structure are aligned and combined, and a liquid crystal layer (not shown) is formed therebetween to form a vertical alignment, the liquid crystal display according to the exemplary embodiment of the present invention is a basic element. The structure is made.

The liquid crystal molecules included in the liquid crystal layer (not shown) have a director on the thin film transistor substrate 100 and the common electrode substrate 200 when no electric field is applied between the pixel electrode 82 and the common electrode 90. It is oriented perpendicular to and has negative dielectric anisotropy. The thin film transistor substrate 100 and the common electrode substrate 200 are aligned such that the pixel electrode 82 accurately overlaps the color filter 98. In this way, the pixel is divided into a plurality of domains by the cutout 92 of the common electrode 90 and the cutout 84 of the pixel electrode 82. In this case, the pixels are divided left and right by the cutout 84, but the vertically divided liquid crystals are divided into domains in the vertical direction because the alignment directions of the liquid crystals are different from each other. That is, the pixel is divided into a plurality of domains according to the direction in which the main directors of the liquid crystal molecules included in the liquid crystal layer are arranged when the electric field is applied.

The liquid crystal display device is formed by disposing elements such as a polarizing plate and a backlight on the basic structure.

At this time, the polarizing plate (not shown) is disposed one each on both sides of the basic structure and the transmission axis 1 is arranged to be parallel to the gate line 22 and the other one is perpendicular to it.

When the liquid crystal display device is formed as described above, when an electric field is applied to the liquid crystal, the liquid crystal in each domain is inclined in a direction perpendicular to the gap 83 or the cutout 92 dividing the domain. Therefore, the liquid crystal of each domain is inclined approximately 45 degrees or -45 degrees with respect to the transmission axis 1 of the polarizing plate.

A coupling relationship between the first subpixel electrode 82a and the second subpixel electrode 82b will be described with reference to FIG. 4. 4 is a circuit diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

When the same coupling capacitance is obtained through the following equation, it is an expression showing the relationship between the area when one coupling electrode is provided and the area where the first and second coupling electrodes overlap with the second subpixel electrode.

도 1c 및 도 4에서 Ca는 제2 결합 전극(63)과 제1 결합 전극(25) 사이에 생기는 결합 용량을 나타내고, Cb는 제2 결합 전극(63)과 제1 부화소 전극(82a) 사이에 생기는 결합 용량을 나타내고, ε1,ε2는 각각 게이트 절연막(30)과 보호막(70)의 각각 유전율을 나타내고, d1, d2는 각각 게이트 절연막(30) 및 보호막(70)의 두께를 나타내고, A1는 각각 제2 결합 전극(63), 제1 결합 전극(25) 및 제1 부화소 전극(82a)이 동시에 중첩하는 면적을 나타낸다. 또한 게이트 절연막(30) 상에 드레인 전극(66)과 연결되는 하나의 결합 전극으로 제2 부화소 전극(82b)이 제1 부화소 전극(82a)과 용량성으로 결합하는 경우, Ccp는 상기의 결합 전극과 제2 부화소 전극(82b) 사이의 결합 용량을 나타내고, 상기의 결합 전극과 제2 부화소 전극(82b)이 중첩하는 면적을 A을 나타낸다고 할 때, Ccp와 Ca와 Cb의 합성 결합 용량(Ccp1)이 같게 되는 면적 A1을 구해보면, 우선 각각의 결합 용량(Ca, Cb)이 도 4에서 도시된 바와 같이 병렬로 연결되어 있으므로, 합성 결합 용량(Ccp1)은 Ca+Cb이며 이 값은 Ccp과 같게 된다.

In FIGS. 1C and 4, Ca represents a coupling capacitance generated between the second coupling electrode 63 and the first coupling electrode 25, and Cb represents between the second coupling electrode 63 and the first subpixel electrode 82a. Denotes the coupling capacitance generated by the capacitor, and ε1 and ε2 represent the dielectric constants of the gate insulating film 30 and the protective film 70, respectively, and d1 and d2 represent the thicknesses of the gate insulating film 30 and the protective film 70, respectively. Respectively, the area where the second coupling electrode 63, the first coupling electrode 25, and the first subpixel electrode 82a overlap each other is shown. In addition, when the second subpixel electrode 82b is capacitively coupled to the first subpixel electrode 82a by one coupling electrode connected to the drain electrode 66 on the gate insulating layer 30, Ccp is described above. Assuming that the coupling capacitance between the coupling electrode and the second subpixel electrode 82b is represented, and that the area where the coupling electrode and the second subpixel electrode 82b overlap is A, a composite coupling of Ccp, Ca, and Cb When the area A1 where the capacitance Ccp1 is equal is obtained, first, since each coupling capacitance Ca and Cb are connected in parallel as shown in Fig. 4, the synthetic coupling capacitance Ccp1 is Ca + Cb, which is a value. Is equivalent to Ccp.

In the above formula, it is assumed that ε1 and ε2 are the same. (In the embodiment of the present invention, it is assumed that the protective film is an inorganic film made of silicon nitride or the like.)

Therefore, A1 has a smaller value than A. Therefore, when the first subpixel electrode 82a and the second subpixel electrode 82b are coupled in parallel capacitively, the overlapping area A of the first and second coupling electrodes is the first subpixel electrode. Even when the pixel electrode 82a and the second subpixel electrode 82b are capacitively coupled to each other, the same coupling capacitance can be obtained even if the bonding electrode area is smaller than A, and the aperture ratio of the liquid crystal display device can be improved, and the liquid crystal can be improved. The luminance of the display device can be improved.

In addition, Clca represents the liquid crystal capacitance formed between the first subpixel electrode 82a and the common electrode 90, and Cst represents between the first subpixel electrode 82a and the sustain electrode wirings 28, 29a, and 29b. Retention capacity formed. Clcb represents the liquid crystal capacitance formed between the second subpixel electrode 82b and the common electrode 90.

Referring to FIG. 4, the thin film transistor Q of each pixel includes a control terminal (or gate electrode) connected to the gate line G, an input terminal (or source electrode) connected to the data line D, and a liquid crystal capacitor. It is a three-terminal element having an output terminal (or a drain electrode) connected to (Clca, Clcb) and a storage capacitor (Cst).

If the voltage of the first subpixel electrode 82a with respect to the voltage of the common electrode 90 is Va and the voltage of the second subpixel electrode 82b is Vb, according to the voltage division law,

Vb = Va * [Ccp / (Ccp1 + Clcb)]

Since Ccp / (Ccp1 + Clcb) is always less than 1, Vb is always smaller than Va. The ratio of Vb to Va can be adjusted by adjusting Ccp. Adjustment of Ccp1 is possible by adjusting the overlapping area or distance with the 1st coupling electrode 25, the 2nd coupling electrode 63, and the 2nd subpixel electrode 82b. As such, the arrangement of the first and second coupling electrodes 63 and 75 may be variously modified.

Hereinafter, a liquid crystal display according to another exemplary embodiment of the present invention will be described with reference to FIGS. 5A to 7.

5A is a layout view of a thin film transistor substrate for a liquid crystal display according to another exemplary embodiment. FIG. 5B is a cross-sectional view of the thin film transistor substrate of FIG. 5A taken along a line Vb-Vb ′, and FIG. 6 is a thin film transistor substrate. And a layout view of a liquid crystal display according to another exemplary embodiment of the present invention including a common electrode substrate, and FIG. 7 is an equivalent circuit diagram of a liquid crystal display according to another exemplary embodiment of the present invention. For convenience of description, members having the same functions as the members shown in the drawings of the embodiments described with reference to FIGS. 1A to 4 are denoted by the same reference numerals, and therefore description thereof is omitted. As shown in Figs. 5A to 5C, the liquid crystal display of this embodiment has the same structure as the liquid crystal display of the previous embodiment except for the following.

The first coupling electrode 23 may be formed separately and side by side adjacent to the sustain electrode 29b to secure the opening ratio in the same layer as the gate wirings 22, 24, and 26. Its shape and arrangement is not limited thereto.

The second coupling electrode 61 is formed to extend from the drain electrode 66, for example, one terminal of the thin film transistor, and the second coupling electrode 61 is formed to overlap a portion of the first coupling electrode 23. do.

The first subpixel electrode 82a is electrically connected to the second coupling electrode 61 through the contact hole 76, and the second subpixel electrode 82b is connected to the first coupling electrode 72 through the contact hole 72. 23) is electrically connected. Unlike in the exemplary embodiment of the present invention, as illustrated in FIG. 5B, the first coupling electrode 23 and the second subpixel electrode 82b electrically connected to the first coupling electrode 23 are inverted from the left and right of the second coupling electrode 61. It has a form of enclosing it. This is the coupling capacitance Ccp2 formed between the second coupling electrode 61 and the first coupling electrode, and the coupling capacitance Cd formed between the second coupling electrode 61 and the second subpixel electrode 82b. Combined capacities are connected in parallel. That is, the second subpixel electrode 82b is capacitively coupled to the first subpixel electrode 82a by two coupling capacitors Cc and Cd connected in parallel.

As shown in FIG. 7, since their coupling capacities Cc and Cd are connected in parallel, the total coupling capacities Ccp2 become larger than the sum of their coupling capacities Ccp2, and therefore, the same coupling capacities are to be made. In this case, the areas of the first and second coupling electrodes 23 and 61 which are the respective electrodes forming the coupling capacitors Ca and Cb may be reduced. Therefore, the aperture ratio of the liquid crystal display device can be improved, and the luminance can be increased.

Hereinafter, a liquid crystal display according to another exemplary embodiment of the present invention will be described with reference to FIGS. 8A to 10.

8A is a layout view of a thin film transistor substrate for a liquid crystal display according to another exemplary embodiment. FIG. 8B is a cross-sectional view of the thin film transistor substrate of FIG. 8A taken along a line VIIIb-VIIIb ′, and FIG. 9 is a thin film transistor. FIG. 10 is a layout view of a liquid crystal display according to another exemplary embodiment including a substrate and a common electrode substrate, and FIG. 10 is an equivalent circuit diagram of a liquid crystal display according to another exemplary embodiment of the present invention. For convenience of description, members having the same functions as the members shown in the drawings of the embodiments described with reference to FIGS. 5A to 7 are denoted by the same reference numerals, and thus description thereof is omitted. 8A to 10, the liquid crystal display of the present embodiment has the same structure as the liquid crystal display of the previous embodiment except for the following.

The second coupling electrode 67 not only overlaps the first coupling electrode 23, but also overlaps the storage electrode wirings 28, 29a and 29b, and thus the second coupling electrode 67 and the storage electrode wirings 28 and 29a. , 29b). Here, in order to prevent generation of parasitic capacitance between the sustain electrode wirings 28, 29a and 29b and the first and second subpixel electrodes 82a and 82b, the second bonding electrode 67 may include the sustain electrode wiring 28. 29a, 29b) is preferably superimposed entirely. Therefore, unlike other embodiments of the present invention, the distance between the second coupling electrode 67 and the sustain electrode wirings 28, 29a, and 29b can be shortened to form a larger storage capacitance.

As shown in FIGS. 5B and 7, the coupling capacitance Cc between the second coupling electrode 67 and the first coupling electrode 23 and between the second coupling electrode 67 and the second subpixel electrode 82b. , Cd is formed, and a coupling capacitor Ce is formed between the second coupling electrode 67 and the second subpixel electrode 82b on the sustain electrodes 29a and 29b, and the coupling capacitor Cc, The binding relationship of Cd and Ce) is connected in parallel. Therefore, since the total synthetic coupling capacitance Ccp3 becomes the sum of these coupling capacitances Cc, Cd, and Ce, the first and second coupling electrodes, which are respective electrodes forming the coupling capacitances Cc, Cd, and Ce, are increased. The area of (23, 67) can be further reduced. Therefore, the aperture ratio of the liquid crystal display device can be improved, and the luminance can be increased.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

According to the liquid crystal display of the present invention as described above has the following advantages.

The capacitance is increased by connecting two capacitors in parallel to the coupling capacitance formed under the second subpixel electrode. Therefore, when the capacitance value when two capacitors are connected in parallel has the same capacitance as when forming a capacitance with one capacitor, even if the area of the coupling electrode is reduced, the coupling capacity does not decrease so that the aperture ratio increases and the liquid crystal display The brightness of the device is further improved. In addition, since the aperture ratio of the pixel is increased by forming the coupling electrode overlapping with the sustain electrode, the luminance of the liquid crystal display is further improved.

Claims (16)

A gate line and a first coupling electrode formed on the insulating substrate; A data line insulated from the gate line and the first coupling electrode on the insulating substrate; A thin film transistor connected to the gate line and the data line and formed for each pixel; A first subpixel electrode electrically connected to the thin film transistor and the first coupling electrode; A second coupling electrode formed between the first coupling electrode and the first subpixel electrode and capacitively coupled to the first coupling electrode and the first subpixel electrode, respectively; And And a second subpixel electrode formed to be spaced apart from the first subpixel electrode and electrically connected to the second coupling electrode. According to claim 1, And an insulating film between the first and second subpixel electrodes and the second coupling electrode. The method of claim 2, And the insulating film is an inorganic film. The method of claim 2, And a gate insulating layer between the first coupling electrode and the second coupling electrode. The method of claim 4, wherein And a first contact hole interposed in the insulating film and the gate insulating film so that a portion of the first coupling electrode is exposed, and the first subpixel electrode is connected by the first contact hole. The method of claim 4, wherein A second contact hole is interposed in the insulating layer so that a portion of the second coupling electrode is exposed, and the second subpixel electrode is connected by the second contact hole. According to claim 1, And the second coupling electrode is formed on the same layer as the data line. A gate line and a first coupling electrode formed on the insulating substrate; A data line insulated from the gate line and the first coupling electrode on the insulating substrate; A thin film transistor connected to the gate line and the data line and formed for each pixel; A first subpixel electrode electrically connected to the thin film transistor; A second coupling electrode formed between the first coupling electrode and the first subpixel electrode, electrically connected to the thin film transistor, and capacitively coupled to the first coupling electrode and the first subpixel electrode; And And a second subpixel electrode formed to be spaced apart from the first subpixel electrode and electrically connected to the first coupling electrode. The method of claim 8, And a passivation layer between the first and second subpixel electrodes and the second coupling electrode. The method of claim 9, The protective film is an LCD. The method of claim 9, And a gate insulating layer between the first coupling electrode and the second coupling electrode. The method of claim 11, wherein And a first contact hole interposed in the insulating film and the gate insulating film so that a portion of the first coupling electrode is exposed, and the second subpixel electrode is connected by the first contact hole. The method of claim 11, wherein A second contact hole is interposed in the insulating layer so that a portion of the second coupling electrode is exposed, and the first subpixel electrode is connected by the second contact hole. The method of claim 11, wherein And a sustain electrode formed on the same layer as the first coupling electrode, wherein the second coupling electrode covers the sustain electrode. The method of claim 13, The first coupling electrode is formed adjacent to the sustain electrode. The method of claim 8, And the second coupling electrode is formed on the same layer as the data line.

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