KR20070016026A - Plasma display device - Google Patents

Abstract

The present invention relates to a plasma display device. More specifically, a driving waveform is applied only to a second electrode (scan electrode or Y electrode) while the first electrode (hold electrode or X electrode) is biased at a constant voltage (0 V). The present invention relates to a plasma display device for electrically connecting one edge of the first electrode or an FPC connected thereto to a circuit board assembly such as a power board on a chassis base. In particular, the one edge of the first electrode is grounded by using the power board or other circuit board assembly, or the circuit board assembly for driving it is characterized in that it is integrated with the power board or other circuit board assembly.

PDP, integrated board, scan electrode, sustain electrode, ground board

Description

Plasma Display Device {PLASMA DISPLAY DEVICE}

1 is an exploded perspective view showing a plasma display device according to the present invention.

2 is a conceptual diagram schematically showing a plasma display panel according to the present invention.

3 is a plan view schematically showing a chassis base according to the present invention.

4 is a driving waveform diagram of a plasma display panel according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display device, and more particularly, to reducing the number of circuit board assemblies by improving the arrangement of other circuit board assemblies on a chassis base without using the circuit board assembly for driving the sustain electrodes, and thus the ground of the sustain electrodes. The present invention relates to a plasma display device capable of ensuring a sufficient amount.

In general, a plasma display panel (hereinafter referred to as a "PDP") is a display panel that displays characters or images using a plasma generated by gas discharge. Discharge cells) are arranged in a matrix form. These PDPs are classified into a direct current type and an alternating current type according to the driving applied thereto.

Since the DC-type PDP is exposed to the discharge space as it is, the current flows in the discharge space while the voltage is applied, and has a disadvantage in that a resistance for current limitation must be made for this purpose. On the other hand, the AC-type PDP has an advantage that the current is limited by the formation of a natural capacitance component because the dielectric layer covers the electrode, and the life is longer than the direct current type because the electrode is protected from the impact of ions during discharge.

The AC plasma display panel includes two first and second substrates spaced apart from each other. On the first substrate, a plurality of scan electrodes and sustain electrodes are formed in pairs and in parallel, and the scan electrodes and sustain electrodes are covered with a dielectric layer and a protective film. A plurality of address electrodes are formed on the second substrate, and the address electrodes are covered with a dielectric layer. A barrier rib is formed on the dielectric layer between the two address electrodes. In addition, phosphor layers are formed on the surface of the dielectric layer and on both side surfaces of the partition wall. The first and second substrates are disposed to face each other with a discharge space therebetween so that the scan electrodes, the address electrodes, the sustain electrodes, and the address electrodes intersect. The discharge space at the intersection of the address electrode and the paired scan electrode and sustain electrode forms a discharge cell.

Generally, in this AC PDP, one frame is divided into a plurality of subfields, and each subfield is composed of a reset period, an address period, and a sustain period.

The reset period is a period for initializing the state of each discharge cell in order to smoothly perform the addressing operation on the discharge cells, and the address period is a discharge cell that is turned on by selecting a discharge cell that is turned on and a discharge cell that is not turned on (the addressed discharge). Is a period of time to accumulate wall charges). The sustain period is a period in which discharge for actually displaying an image is performed on the discharge cells to be turned on.

In order to perform such driving, sustain discharge pulses are alternately applied to the scan electrodes and sustain electrodes in the sustain period, and reset waveforms and scan waveforms are applied to the scan electrodes in the reset period and the address period. Therefore, the circuit board assembly for driving the scan electrode and the circuit board assembly for driving the sustain electrode should be present separately. If the circuit board assembly is separately present, a pulse signal for driving the circuit board assembly must be applied separately, thereby limiting the freedom of design of the circuit board assembly and increasing the footprint of mounting the circuit board assembly on the chassis base. There is a problem, and the unit cost is increased due to a separate circuit board assembly.

Therefore, a method of integrating two circuit board assemblies into one to form one end of the scan electrode and extending one end of the sustain electrode to connect to the integrated board has been proposed. However, when the two circuit board assemblies are integrated in this way, there is a problem that the connection between the circuit board assembly and the sustain electrode is extended and the impedance component formed at the sustain electrode becomes large.

SUMMARY OF THE INVENTION An object of the present invention is to provide a plasma display apparatus which grounds a sustain electrode to a power board without requiring application of a pulse signal for driving the sustain electrode.

In addition, the present invention is to provide a plasma display device that can improve the design freedom of the circuit board assemblies on the chassis base, simplify the manufacturing process and reduce the manufacturing cost by simplifying the wiring between the circuit board assemblies. .

In addition, the present invention is to provide a plasma display device that can secure the space of the chassis base in the module formed by the combination of the PDP and the chassis base.

In order to solve this problem, the plasma display device of the present invention is configured to apply a driving waveform to the scan electrode while biasing the sustain electrode at a constant voltage.

Plasma display device of the present invention,

A plasma display panel including a plurality of first electrodes, a plurality of second electrodes, and a plurality of address electrodes formed in a direction crossing the first electrode and the second electrode, and a chassis base to which the plasma display panel is attached and supported. And circuit board assemblies installed opposite the plasma display panel of the chassis base,

The first electrode,

The adjacent circuit board assembly of the circuit board assemblies on the chassis base is grounded.

The circuit board assemblies,

An image processing and control board for receiving an image signal from an external source and generating a control signal for driving an address electrode and a control signal for driving a first electrode and a second electrode, and receiving an address driving control signal from the image processing and control board An address buffer board for applying a voltage for selecting a discharge cell to be displayed to an address electrode, and a scanning circuit board for receiving a driving signal from the image processing and control board and applying a second electrode driving voltage through a scanning buffer board. An assembly and a power board for supplying power for driving the plasma display panel.

The first electrode is grounded to the circuit board assembly via a flexible circuit, the first electrode is connected to the power board, the power board may include a ground board or a small sustain electrode circuit board assembly,

The first electrode may be grounded to the ground board or the small sustain electrode circuit board assembly.

The scan circuit board assembly and the power board are mounted on left and right sides of the chassis base, and the image processing and control board is mounted in the center space of the chassis base in the space between the scan drive board and the power board, and the address A buffer board may be mounted to the chassis base below the boards.

The power board may be electrically connected to the scan driving board by a first straight line, and may be electrically connected to the address buffer board by a second straight line, and the address buffer board may be a third line that is straight. It may be electrically connected to the image processing and control board by the.

Meanwhile, the plasma display apparatus of the present invention includes a plurality of first electrodes, a plurality of second electrodes, and a plurality of address electrodes formed in a direction crossing the first electrode and the second electrode.

Drive by dividing a frame into a plurality of subfields,

At least one subfield,

A reset period for gradually increasing the voltage of the second electrode from the second voltage to the third voltage after biasing the first electrode to the first voltage, and then gradually decreasing the voltage from the fourth voltage to the fifth voltage. An address period for selecting a discharge cell, and applying a pulse alternately having a sixth voltage and a seventh voltage lower than the sixth voltage to the second electrode while biasing the first electrode to the first voltage; And a sustain period for sustain discharge of the selected discharge cells,

In a first period during which the voltage of the second electrode is at least part of a period in which the voltage of the second electrode increases from the second voltage to the third voltage, the voltage of the address electrode decreases to the fifth voltage. A plasma display panel higher than an eighth voltage applied to the third electrode;

A chassis base to which the plasma display panel is attached and supported and circuit board assemblies installed opposite the plasma display panel of the chassis base, wherein the first electrode is grounded to an adjacent circuit board assembly among the circuit board assemblies on the chassis base. .

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification.

In addition, the wall charge referred to in the present invention refers to a charge formed close to each electrode on the wall (eg, the dielectric layer) of the discharge cell 12. And the wall charge is not actually in contact with the electrode itself, but is described here as "formed", "accumulated" or "stacked" on the electrode. In addition, a wall voltage refers to the potential difference formed in the wall of a discharge cell by wall charge.

A plasma display device according to an embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

1 is an exploded perspective view of a plasma display device according to the present invention, Figure 2 is a schematic conceptual diagram of a plasma display panel according to the present invention.

Referring to these drawings, the plasma display device includes a PDP 10, a chassis base 20, a front case 30, and a rear case 40. The chassis base 20 is disposed on the side opposite to the surface on which the image is displayed on the PDP 10 and is coupled to the PDP 10. The front and rear cases 30 and 40 are disposed on the front of the PDP 10 and the rear of the chassis base 20, respectively, and are combined with the PDP 10 and the chassis base 20 to form a plasma display device.

The PDP 10 includes a plurality of address electrodes (referred to as A electrodes) (A1 to Am) extending in the vertical direction (hereinafter, omitted) and a plurality of agents extending in the transverse direction (hereinafter, omitted). One electrode (hereinafter referred to as sustain electrode or X electrode) (X1 to Xn) and second electrode (hereinafter referred to as scan electrode or Y electrode) (Y1 to Yn) are included. The sustain electrodes X1 to Xn are formed corresponding to the scan electrodes Y1 to Yn, and generally have one end connected to each other in common. The PDP 10 includes a first substrate 1 on which sustain and scan electrodes X1 to Xn and Y1 to Yn are arranged, and a second substrate 2 on which address electrodes A1 to Am are arranged. The first and second substrates 1 and 2 have a discharge space such that the scan electrodes Y1 to Yn and the address electrodes A1 to Am, the sustain electrodes X1 to Xn, and the address electrodes A1 to Am are orthogonal to each other. It is arrange | positioned opposingly between (11). At this time, the discharge space 11 at the intersection of the address electrodes A1 to Am and the sustain and scan electrodes X1 to Xn and Y1 to Yn forms the discharge cells 12.

3 is a schematic plan view of a chassis base in accordance with the present invention.

Referring to this figure, the chassis base 20 will be described. The chassis base 20 is supported by attaching and supporting the PDP 10 on one side thereof, and a plurality of circuits necessary for driving the PDP 10 on the other side thereof. Board assemblies 100 to 500 are provided.

First, the address buffer board 100 is formed in the lower portion (not shown below) of the chassis base 20, and may be formed of a single board or a plurality of boards (not shown) as shown. In FIG. 3, the plasma display apparatus for single driving is described as an example, but in the case of dual driving, the address buffer board 100 may be disposed on both the upper and lower portions of the chassis base 20. The address buffer board 100 is electrically connected to the image processing and control board 400 by a straight line and discharge cells 12 to receive and display an address driving control signal from the image processing and control board 400. Is applied to each of the address electrodes A1-Am.

The scan circuit board assembly 200 is disposed on the left side (not shown below) of the chassis base 20, and the scan circuit board assembly 200 passes through the scan buffer board 300 to scan electrodes Y1 to Yn. Is electrically connected to The scan buffer board 300 applies a voltage to the scan electrodes Y1 to Yn to sequentially select the scan electrodes Y1 to Yn in the address period. The scan circuit board assembly 200 receives a drive signal from the image processing and control board 400 and applies a drive voltage to the scan electrodes Y1 to Yn. 3 illustrates that the scan circuit board assembly 200 and the scan buffer board 300 are disposed on the left side of the chassis base 20, but may be disposed on the right side of the chassis base 20. In addition, the scan buffer board 300 may be formed integrally with the scan circuit board assembly 200.

The image processing and control board 400 receives an image signal from the outside to generate a control signal for driving the address electrodes A1 to Am and a control signal for driving the scan and sustain electrodes Y1 to Yn and X1 to Xn. To the address buffer board 100 and the scanning circuit board assembly 200, respectively. The image processing and control board 400 is located above the address buffer board 100 below the center of the chassis base 20 in a space between the scanning circuit board assembly 200 and the power board 500 described below. Assembled in close proximity.

The power board 500 supplies power for driving the PDP 10. That is, the power board 500 is disposed on the right side of the chassis base 20 so as to face the scanning circuit board assembly 200, and is electrically connected to each other by a straight line and above the address buffer board 100. It is electrically connected by the straight wiring in close proximity.

Therefore, since the wiring between the power board 500, the address buffer board 100, the scanning circuit board assembly 200, and the image processing and control board 400 is simplified, the manufacturing process is efficient and the manufacturing cost can be reduced. have.

In addition, the power board 500 is positioned at the shortest distance from one side edge of the sustain electrodes X1 to Xn or the FPC 5c connected to one side edge, and one side edge or one side of the sustain electrodes X1 to Xn. Since the FPC 5c connected to the edge is grounded, the impedance component of the sustain electrode can be reduced. At this time, the FPC 5c connected to one side edge or one side edge of the sustain electrodes X1 to Xn is fixed by a ground board or a small sustain electrode circuit board assembly 600 which may be embedded in the power board. For example, by biasing to 0V, it is not necessary to apply an independent pulse signal for driving the sustain electrodes X1 to Xn, and accordingly, a sustain electrode circuit board assembly for driving the sustain electrodes X1 to Xn is not provided separately. You may not.

 When the ground structure of the sustain electrodes X1 to Xn is described, the sustain electrodes X1 to Xn are grounded to the power board 500 through the flexible printed circuit (FPC) 5c. That is, the sustain electrodes X1 to Xn formed as described above in the PDP 10 are led out of the PDP 10 through the FPC 5c. The FPC 5c may also be grounded through a ground board 600 embedded in the power board 500.

The sustain electrodes X1 to Xn are grounded to the chassis base 20 as described above, and the scan electrodes Y1 to Yn are provided to the scan circuit board assembly 200 via the scan buffer board 300 as described above. The address electrodes A1 to Am are connected to the address buffer board 100, and the scan buffer board 300 and the address buffer board 100 are connected to and applied to the image processing and control board 400. It is operated by various control signals.

4 is a driving waveform diagram of a plasma display panel according to the present invention. Referring to this figure, the driving waveform of the PDP controlled by the circuit board assemblies 100 to 500 of FIG. 3 will be described.

For convenience, only the driving waveforms applied to the Y electrode, the X electrode, and the A electrode forming one discharge cell 12 will be described. In the driving waveform of FIG. 4, the voltage applied to the Y electrode is supplied from the scan circuit board assembly 200 and the scan buffer board 300, and the voltage applied to the A electrode is supplied from the address buffer board 100. In addition, since the X electrode is biased by the reference voltage (ground voltage in FIG. 4, 0 V), the description of the voltage applied to the X electrode is omitted. The X electrode is grounded to the power board 500 or the ground board 600 embedded in the power board 500 through the FPC 5c.

4, one subfield includes a reset period, an address period, and a sustain period, and the reset period includes a rising period and a falling period.

In the rising period of the reset period, the voltage of the Y electrode is changed from the second voltage (hereinafter referred to as Vs voltage) to the third voltage while the A electrode is maintained at the first voltage (hereinafter referred to as reference voltage) (0V in FIG. 4). Incrementally increases to (hereinafter referred to as Vset voltage). In FIG. 4, the voltage of the Y electrode is shown to increase in the form of a lamp. A weak discharge (hereinafter referred to as "weak discharge") occurs between the Y electrode and the X electrode and between the Y electrode and the A electrode while the voltage of the Y electrode is increased, and a negative (-) wall charge is formed on the Y electrode. Positive wall charges are formed on the X and A electrodes. When the voltage of the electrode is gradually changed as shown in FIG. 4, a weak discharge occurs in the discharge cell, and wall charge is formed so that the sum of the voltage applied from the outside and the wall voltage of the discharge cell maintains the discharge start voltage state. This principle is disclosed in US Pat. No. 5,745,086 to Weber. In the reset period, since the states of all the discharge cells must be initialized, the voltage Vset is high enough to cause discharge in the discharge cells under all conditions. Also, the Vs voltage is generally higher than the voltage applied to the Y electrode in the sustain period, and lower than the discharge start voltage between the Y and X electrodes.

Subsequently, in the falling period of the reset period, the voltage of the Y electrode is gradually decreased from the fourth voltage (hereinafter referred to as Vs voltage) to the fifth voltage (hereinafter referred to as Vnf voltage) while the A electrode is held at the reference voltage. . Then, a slight discharge occurs between the Y electrode and the X electrode and between the Y electrode and the A electrode while the voltage of the Y electrode decreases, so that the negative wall charge formed on the Y electrode and the positive wall formed on the X electrode and the A electrode The charge is erased. In general, the magnitude of the Vnf voltage is set near the discharge start voltage between the Y electrode and the X electrode. Then, the wall voltage between the Y electrode and the X electrode becomes almost 0 V, whereby the discharge cells 12 in which the address discharge has not occurred in the address period can be prevented from being erroneously discharged in the sustain period. Since the A electrode is maintained at the reference voltage, the wall voltage between the Y electrode and the A electrode is determined by the level of the Vnf voltage.

Next, to select the discharge cells to be turned on in the address period, a scan pulse having a VscL voltage and an address pulse having an eighth voltage (hereinafter referred to as Va voltage) are applied to the Y and A electrodes, respectively. The unselected Y electrode biases the VscH voltage higher than the VscL voltage, and applies a reference voltage to the A electrode of the discharge cell that will not be turned on. In order to perform this operation, the scan buffer board 300 (refer to FIG. 3) selects the Y electrode to which the scan pulse of VscL is to be applied among the Y electrodes Y1 to Yn, for example, in the vertical direction in a single drive. The Y electrodes can be selected in the order in which they are arranged. When the one Y electrode is selected, the address buffer board 100 discharges a discharge cell to which an address pulse of Va voltage is applied among the A electrodes A1 to? M passing through the discharge cell 12 formed by the corresponding Y electrode. Select (12).

As described above, in the present invention, the reset operation, the address operation, and the sustain discharge operation can be performed only by the driving waveform applied to the Y electrode while the X electrode is biased to the reference voltage. Thus, the circuit board assembly that drives the X electrode can be removed, simply biasing the X electrode to the reference voltage.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, in a state where the sustain electrode is biased at a constant voltage (0 V), a sustain pulse is applied to the scan electrode to generate a sustain discharge, thereby realizing an image, and grounding the sustain electrode to a power board. The effect is to simplify the configuration of the circuit board assemblies on the chassis base.

In addition, grounding the sustain electrode to the power board increases the design freedom of the circuit board assemblies on the chassis base, simplifies the wiring between the circuit board assemblies, and maintains the impedance of the sustain electrode by grounding the sustain electrode to the power board at the shortest distance. It has a reducing effect.

In addition, in the module formed by the combination of the PDP and the chassis base, space can be secured behind the chassis base, and the manufacturing cost can be reduced by reducing the number of circuit board assemblies on the chassis base.

Claims (11)

A plasma display panel including a plurality of first electrodes, a plurality of second electrodes, and a plurality of address electrodes formed in a direction crossing the first electrode and the second electrode. A chassis base supported by attaching the plasma display panel; Circuit board assemblies installed opposite the plasma display panel of the chassis base, The first electrode, A plasma display device grounded to an adjacent circuit board assembly among the circuit board assemblies on the chassis base. According to claim 1, The circuit board assemblies, An image processing and control board that receives an image signal from the outside and generates a control signal for driving the address electrode and a control signal for driving the first electrode and the second electrode. An address buffer board that receives an address driving control signal from the image processing and control board and applies a voltage to an address electrode for selecting a discharge cell to display. A scan circuit board assembly receiving a drive signal from the image processing and control board and applying a second electrode driving voltage through a scan buffer board; And a power board for supplying power for driving the plasma display panel. According to claim 1, And the first electrode is grounded to the circuit board assembly via a flexible circuit. The method of claim 2, And the first electrode is connected to the power board. The method of claim 4, wherein The power board, Built-in ground board or small sustain electrode circuit board assembly, The first electrode, And a plasma display device which is grounded to the ground board or the small sustain electrode circuit board assembly. The method of claim 2, The scan circuit board assembly and the power board, Mounted on both left and right sides of the chassis base, The image processing and control board is mounted in the central space of the chassis base in the space between the scan drive board and the power board, And the address buffer board is mounted to the chassis base under the boards. The method of claim 6, The power board, Electrically connected to the scan drive board by a first straight line; A plasma display device electrically connected to an address buffer board by a second straight line. The method of claim 7, wherein And the address buffer board is electrically connected to the image processing and control board by a third straight line. A plurality of first electrodes and a plurality of second electrodes and a plurality of address electrodes formed in a direction crossing the first electrode and the second electrode, Drive by dividing a frame into a plurality of subfields, At least one subfield, A reset period in which the voltage of the second electrode is gradually increased from the second voltage to the third voltage while the first electrode is biased to the first voltage, and then gradually decreases from the fourth voltage to the fifth voltage, An address period for selecting a discharge cell to be turned on, and A sustain period in which the selected discharge cell is sustained and discharged by applying a pulse having a sixth voltage and a seventh voltage lower than the sixth voltage to the second electrode while biasing the first electrode to the first voltage. Including; In a first period during which the voltage of the second electrode is at least part of a period in which the voltage of the second electrode increases from the second voltage to the third voltage, the voltage of the address electrode decreases to the fifth voltage. To be higher than an eighth voltage applied to the third electrode Plasma display panel A chassis base to which the plasma display panel is attached and supported; Circuit board assemblies installed opposite the plasma display panel of the chassis base, And the first electrode is grounded to an adjacent circuit board assembly among circuit board assemblies on the chassis base. The method of claim 9, And the first electrode is connected to a power board. The method of claim 10, The power board, With a ground board or small sustain electrode circuit board assembly, The first electrode, And a plasma display device which is grounded to the ground board or the small sustain electrode circuit board assembly.

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