KR100749515B1 - Plasma Display Panel - Google Patents

Abstract

A plasma display panel according to the present invention includes a panel having a discharge cell formed by a data electrode, a scan electrode, and a sustain electrode on a substrate, a first circuit board having a circuit for driving the data electrode, and a drive of the scan electrode. A second circuit board having a circuit formed thereon, a third circuit board formed with a circuit for driving the sustain electrode, and a rear surface of the panel, supporting the first circuit board, A first frame for providing a base voltage to the board, and coupled to the first frame to support the second circuit board and the third circuit board, and to at least one of the second and third circuit boards. A second frame for providing a base voltage and an insulation between the first frame and the second frame between the first frame and the second frame And an insulating layer for group.

Description

Plasma Display Panel             

1 is a view showing a conventional PDP.

2 shows a cross section of FIG. 1;

3 is a diagram illustrating a frame configuration for implementing 256 gradations.

4 is a diagram illustrating a driving waveform of a PDP supplied to two subfields.

5 illustrates a PDP according to the present invention.

Figure 6 is a view showing a fastening state of the frame and the PCB.

7 is a perspective view showing a discharge cell of the panel;

8 is a view showing a PDP rear structure of the present invention.

FIG. 9 is a sectional view of the PDP shown in FIG. 4; FIG.

10 is a view showing a PDP rear structure according to the second embodiment of the present invention;

<Explanation of symbols for the main parts of the drawings>

2: data driver IC 3: scan driver IC

10, 42: panel 12: pad

14: FPC 18, 49, 89: printed circuit board

20: heat sink 30, 40: case

44: heat dissipation sheet 46, 86: first frame

48, 88: second frame 50: back cover

52: data drive board 53: scan drive board

54: Pampnut 56: Controller Board

57: Z sustainer board 59, 60, 69, 70: challenge path

61, 62: sustain electrode pair 63: upper dielectric layer

64: protective film 66: data electrode

68: lower dielectric layer 65: partition wall

67 phosphor layer 90 power supply

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a plasma display panel which enables stable driving.

Recently, various flat panel displays have been developed to reduce weight and volume, which are disadvantages of cathode ray tubes. Flat display devices include Liquid Crystal Display (LCD), Field Emission Display (FED), Plasma Display Panel (hereinafter referred to as "PDP") and Electroluminescence (Electro). -Luminescence (EL) display.

Among them, PDP is a flat panel display device that displays images by using plasma discharge. The PDP is used for high resolution televisions, monitors, and indoor / outdoor advertising because it has fast response speed and is suitable for displaying large area images.

1 and 2, a conventional PDP includes a panel 10, a printed circuit board (“PCB”) 18 for driving the panel 10, and the panel 10. The heat sink 20 is provided in the back surface.

The panel 10 includes an upper substrate 10a having a plurality of scan electrodes and sustain electrodes formed thereon, a plurality of address electrodes formed in a direction crossing the scan electrodes and the sustain electrodes, and a phosphor layer formed on the front surface of the substrate. It consists of the lower substrate 10b. The phosphor generates visible light by discharge between the scan electrodes and the sustain electrodes and the address electrodes, and adjusts the transmittance of the visible light to display a predetermined image.

The heat sink (or frame) 20 installed on the rear surface of the panel 10 supports the panel 10 and serves to dissipate heat generated when the panel 10 is driven. The heat sink 20 is formed of a metal material having a good thermal conductivity, for example, aluminum (Al) or the like so as to radiate heat well.

The panel 10 requires a plurality of driving integrated circuits (hereinafter referred to as “driver ICs”) connected to the scan electrodes and the address electrodes to supply data signals and scan signals, respectively. The driver ICs consist of a scan driver IC 3 and a data driver IC 2, each of which is installed between the PCB 18 and the panel 10 in response to a control signal supplied from the PCB 18. Supply a driving signal. To this end, the PCB 18 and the panel 10 are connected by a flexible printed circuit (FPC, 14). When ICs are packaged in a chip on film (COF) method, one side of the FPC 14 is connected to the IC chip 16 of the scan and data driver ICs 2 and 3, and the FPC 14 The other side is connected to the pads 12 connected to the driving electrodes of the panel 10.

The case 30 is installed to protect the PDP from external shock when the above-described PDP is shipped. To this end, the case includes a front case for protecting the front panel of the panel and a back cover for protecting the back of the PDP.

Such a PDP is time-divided and driven by dividing one frame into several subfields having different numbers of light emission in order to realize gray levels of an image. Each subfield is divided into an initialization period for initializing the full screen, an address period for selecting a scan line and selecting a cell in the selected scan line, and a sustain period for implementing gray levels according to the number of discharges.

Here, the initialization period is divided into a plurality of setup periods in which a rising ramp waveform Ramp-up is supplied and a set-down period in which a falling ramp waveform Ramp-down is supplied. For example, when the image is to be displayed in 256 gray levels, as shown in FIG. 3, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8. As described above, each of the eight subfields SF1 to SF8 is divided into an initialization period, an address period, and a sustain period. The initialization period and the address period of each subfield are the same for each subfield, while the sustain period is increased at a rate of 2 ⁿ (n = 0, 1, 2, 3, 4, 5, 6, 7) in each subfield. .

4 shows driving waveforms of a PDP supplied to two subfields, Y denotes a scan electrode, Z denotes a sustain electrode, and X denotes an address electrode.

Referring to FIG. 4, the PDP is driven by being divided into an initialization period for initializing the full screen, an address period for selecting a cell, and a sustain period for maintaining discharge of the selected cell.

In the initialization period, the rising ramp waveform is applied to all the scan electrodes Y simultaneously. This rising ramp waveform causes a slight discharge in the cells of the full screen to generate wall charges in the cells. During the set down period, the rising ramp waveform is supplied, and then a falling ramp waveform Ramp-down falling at a positive voltage lower than the peak voltage of the rising ramp waveform is simultaneously applied to the scan electrodes Y. The falling ramp waveform generates weak erase discharges in the cells, thereby eliminating unnecessary charges during wall charges and space charges generated by the setup discharges, and uniformly retaining the wall charges required for the address discharges in the full screen cells.

In the address period, the negative scan pulse scan is sequentially applied to the scan electrodes Y, and the positive data pulse data is applied to the address electrodes X. As the voltage difference between the scan pulse and the data pulse and the wall voltage generated during the initialization period are added, address discharge is generated in the cell to which the data pulse is applied. Wall charges are generated in the cells selected by the address discharge.

Meanwhile, the positive polarity DC voltage of the sustain voltage level Vs is supplied to the sustain electrodes Z during the set down period and the address period.

In the sustain period, sustain pulses sus are alternately applied to the scan electrodes Y and the sustain electrodes Z. FIG. Then, the cell selected by the address discharge is sustained in the form of surface discharge between the scan electrode (Y) and the sustain electrode (Z) whenever the sustain pulse (sus) is applied while the wall voltage and the sustain pulse (sus) in the cell are added. Discharge occurs. Finally, after the sustain discharge is completed, an erase ramp waveform (erase) having a small pulse width is supplied to the sustain electrode (Z) to erase wall charges in the cell.

In such a PDP, the voltage of the ground voltage source (Vss or GND) must be kept constant in order to supply the above-described driving waveform to the panel 10.

In the conventional PDP, the heat sink 20 is used as such a base voltage source. On the heat sink, a PCB 18 having a plurality of driving circuit units, for example, a scan driver, a sustain driver, a data controller, and data drivers, is fixed. Therefore, since it becomes easy to unify the base voltage source of the circuit using the same base voltage source, the heat sink 20 is used as the base voltage source of each circuit.

However, in the PDP, the operating voltages of the circuit parts and the power supply part supplying power to the circuit parts are different, and the signal voltages generated in the respective circuit parts are different. In particular, the voltage between the scan driver and the sustain driver and the data controller and the data driver is large. The signal voltages from the scan driver and the sustain driver use 150 [V] to 500 [V], while the signal voltages of the data controller and the data driver use voltages in the tens of volts. In addition, the peak voltage of the rising ramp waveform or the falling ramp waveform has a larger voltage difference from the signal voltage of the data controller and the data driver.

For this reason, the base voltage cannot be maintained uniformly, or rises or falls larger than the voltage value to be actually maintained. In addition, the signal voltages of the scan driver and the address driver constantly change during the driving of the PDP. As a result, the base voltage of the base voltage source also continuously fluctuates, and noise is generated in the driving signals. Due to this noise, there is a problem that the PDP does not operate stably due to mis-discharge, heating, and damage to the driving circuit part.

Accordingly, an object of the present invention relates to a plasma display panel which enables stable driving.

In order to achieve the above object, a plasma display panel according to the present invention comprises a panel having a discharge cell formed by a data electrode, a scan electrode and a sustain electrode on a substrate; A first circuit board on which a circuit for driving the data electrode is formed; A second circuit board on which a circuit for driving the scan electrode is formed; A third circuit board having a circuit for driving the sustain electrode; A first frame installed at a rear surface of the panel to support the first circuit board and to provide a base voltage to the first circuit board; A second frame coupled to the first frame, supporting the second circuit board and the third circuit board, and providing a base voltage to at least one of the second and third circuit boards; An insulating layer is provided between the first frame and the second frame to insulate between the first frame and the second frame.

The second frame provides a base voltage to both the second circuit board and the third circuit board.

The apparatus may further include a power supply unit for supplying power to the first to third circuit boards, wherein the power supply unit provides a base voltage by the second frame.

Spacers are formed between the first frame and the second frame such that the first frame and the second frame do not contact each other.

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The first frame or the second frame is a conductive plastic.

The second frame is integrally formed to supply the base voltage to at least one of the second circuit board, the third circuit board, and the power supply unit.

A plurality of second frames are formed separately to supply the base voltage to each of the second circuit board, the third circuit board, and the power supply unit.

Other objects and features of the present invention other than the above object will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 5 to 10.

5 illustrates a PDP according to the present invention.

Referring to FIG. 5, a PDP according to an embodiment of the present invention may include a front case 40, a panel 42, a heat dissipation sheet 44, a first frame 46, a second frame 48, and a PCB 49. And a back cover 50.

The front case 40 is installed on the front of the panel 42 to protect the panel 42 from external impact and contaminants, and is composed of a glass, front filter. The front filter includes an optical characteristic film, an EMI (Electro Magnetic Interference: EMI) shielding film, an infrared shielding film, and the like. The glass protects the front filter from damage from external impact. The optical characteristic film improves the optical characteristics of the PDP by lowering the luminance of red (R) and green (G) and increasing the luminance of blue (B) among the light incident from the panel 42. The electromagnetic shielding film shields electromagnetic waves and prevents electromagnetic waves incident from the panel 42 from being emitted to the outside. The infrared shielding film shields the infrared rays emitted from the panel 42 to prevent the infrared rays above the reference from being emitted to the outside so that the signals transmitted using the infrared rays such as a remote controller can be normally transmitted.

The panel 42 is formed of an upper substrate 42a on which a plurality of scan electrodes are formed, a lower substrate 42b including a plurality of address electrodes formed in a direction crossing the scan electrodes, and a phosphor layer formed on the front surface of the substrate. . The phosphor generates visible light by the discharge between the scan electrodes and the address electrodes, and adjusts the transmittance of the visible light to display a predetermined image. In addition, pads are connected to the electrodes of the IC chip by FPC.

The heat dissipation sheet 44 is positioned between the panel 42 and the first frame 46, and transfers heat generated from the panel 42 to the first frame 46 when the PDP is driven. The heat dissipation sheet 44 prevents the temperature of the panel 42 from rising rapidly due to heat generation during PDP driving.

The first frame 46 dissipates heat from the heat dissipation sheet 44 and the second frame 48 to the outside, and supports the second frame 48, the controller board, and the data driving board, and their bases. Used as voltage source (Vss or GND). To this end, the first frame 46 is provided with fastening means for fixing the controller board and the data driver.

The second frame 48 fixes and supports the scan drive board and the sustainer board, and is used as a base voltage source of the scan drive board and the sustainer board. In addition, the heat generated in the scan driving board and the sustainer board is discharged together with the first frame 46 to prevent the temperature of the boards from rising rapidly. To this end, the second frame 48 has fastening means for fixing the scan drive board and the sustainer board.

Here, the first frame 46 and the second frame 48 must be insulated or separated to be used as the base voltage source of the respective boards. To this end, an insulator such as a urethane pad is inserted between the first frame 46 and the second frame 48, or a spacer for maintaining a gap between the first frame 46 and the second frame 48 is inserted. Should be.

The PCB 49 includes a scan drive board for driving scan electrode lines formed in the panel 42, a sustainer board for driving sustain electrode lines, a data drive board and scan drive board for driving data electrode lines, and a sustainer. A control board for controlling the board and the data driver board is provided. The scan drive board and the sustain drive board are supported and fixed by the second frame 48, and use the second frame 48 as the base voltage source. In addition, the data drive board and the controller board are supported and fixed by the first frame 46, and use the first frame 46 as the base voltage source.

The back cover 50 is fastened together with the front case 40 at the rear of the PDP to protect the PDP from external shocks, contaminants, and the like.

6 is a view showing a fastening state of the frame and the PCB.

Referring to FIG. 6, the first frame 46 is fixed to the panel 42 with the heat dissipation sheet 44 interposed therebetween. An insulator 51 such as urethane is attached to the first frame 46. The second frame 48 is again assembled on the insulator 51.

The first frame 46 secures the data driving board 52 or the controller board by fastening means 55 such as a pampnut, a screw, and the like, and the pampnut, the screw, and the like used using a conductive material. The data driving board 52 or the controller board fixed to the first frame 46 is electrically connected to the first frame 46 by the fastening means 55 to use the first frame 46 as a base voltage source. Done. The fastening means 55 extending from the first frame 46 in the direction of the second frame 48 penetrates the first frame 46 at a portion where the second frame 48 and the first frame 46 overlap. By stretching. At this time, an insulator is inserted into the through portion so that the fastening means 55 of the first frame does not come into contact with the second frame 48, or the through-hole diameter of the second frame 48 is determined by the fastening means of the first frame 46. It is made larger than the diameter so that the fastening means 55 of the 2nd frame 48 and the 1st frame 46 may not contact.

Similarly to the first frame 46, the second frame 48 also fixes and supports the scan drive board 53 or the sustainer board by fastening means 54 such as pampnuts and screws. The fastening means 54 of the second frame 48 also uses a conductive material similarly to the fastening means 55 of the first frame 46. The fastening means 55 electrically connects the second frame 48 and the scan drive board 53 or the sustainer board, and by this connection, the scan drive board 53 or the sustainer board is connected to the second frame ( 48) is used as the base voltage source.

7 is a perspective view showing a discharge cell of the panel.

Referring to FIG. 7, the discharge cell illustrated in FIG. 7 includes an upper plate having sustain electrode pairs 61 and 62, an upper dielectric layer 63, and a protective layer 64 sequentially formed on the upper substrate 42a, and a lower substrate. A lower plate having a data electrode 66, a lower dielectric layer 68, a partition wall 65, and a phosphor layer 67 formed sequentially on 42b is provided.

Each of the sustain electrode pairs 61 and 62 is composed of a transparent electrode and a metal electrode for compensating for the high resistance of the transparent electrode. The sustain electrode pairs 61 and 62 are separated into the scan electrode 61 and the sustain electrode 62. The scan electrode 61 supplies a scan signal for address discharge and a sustain signal for sustain discharge, and the sustain electrode 62 mainly supplies a sustain signal. The data electrode 66 supplies a data signal for address discharge.

Charges generated by discharge are accumulated in the upper dielectric layer 63 and the lower dielectric layer 68. The protective film 64 prevents damage to the upper dielectric layer 14 due to sputtering during discharge and increases the emission efficiency of secondary electrons. The dielectric layers 63 and 68 and the passivation layer 64 can lower the discharge voltage applied from the outside.

The partition wall 65 is formed in parallel with the data electrode 66 to prevent ultraviolet rays generated by the gas discharge from leaking into adjacent cells. The phosphor layer 67 is applied to the surfaces of the lower dielectric layer 68 and the partition wall 65 to generate red, green or blue visible light. The discharge space is filled with an inert gas such as He, Ne, Ar, Xe, or Kr for gas discharge, a discharge gas having a combination thereof, or an excimer gas capable of generating ultraviolet rays by discharge.

The discharge cell of this structure is selected as the counter discharge by the data electrode 66 and the scan electrode 61 and then sustains the discharge by the surface discharge by the pair of sustain electrodes 61 and 62. Accordingly, in the discharge cell, the visible light is emitted by the phosphor 67 emitting light by ultraviolet rays generated during the sustain discharge.

FIG. 8 is a view showing a PDP back structure of the present invention, and FIG. 9 is a sectional view of the PDP shown in FIG.

8 and 9, the PDP of the present invention drives the scan driving board 53 and the sustain electrode lines Z1 to Zm for driving the scan electrode lines Y1 to Ym of the panel 42. Z sustainer board 57, data drive board 52 and scan drive board 53 for driving data electrode lines X1 to Xn, Z sustainer board 57 and data drive board 52 Controller board 56 for controlling &lt; RTI ID = 0.0 &gt;

The scan drive board 53 includes a scan board 53a for generating reset pulses and scan pulses and a scan sustainer board 53b for generating scan sustain pulses on the panel 42. The scan board 53a supplies a scan pulse to the scan electrode lines Y1 to Ym of the panel 42 via the scan conductive path 58. The scan sustainer board 53b supplies the scan sustain pulses to the scan electrode lines Y1 to Ym via the scan board 53a and the scan conductive path 58.

The Z sustainer board 57 generates bias pulses and sustain pulses, and supplies them to the sustain electrode lines Z1 to Zm of the panel 42 via the sustain conductive path 59.

The data driving board 52 generates data pulses and supplies them to the data electrode lines X1 to Xn of the panel 42 via the data conductive path 60.

The controller board 56 generates each of data, scan, and sustain timing control signals. The controller board 56 transmits the scan timing control signal to the scan driving board 53 via the first conductive path 69, and the sustain timing control signal via the second conductive path 70 to the Z sustainer board. At 57, a data timing control signal is supplied to the data driving board 52 via the third conductive path 71.

In this case, it is preferable that a flexible flat cable (hereinafter referred to as "FFC") or an FPC is used as each conductive path.

As shown in FIG. 5, the data driving board 52 and the controller board 56 are fixed to the first frame 46, and the scan driving board 53 and the Z sustainer board 57 are different from those of FIGS. 5 and 6. It is fixed to the second frame 48 as well.

Therefore, in the first embodiment of the present invention, the scan driving board 53 and the Z sustainer board 57 may use a base voltage source different from that of the data driving board 52 and the controller board 56. This makes it possible to keep the base voltages of the respective boards relatively uniform, which makes it possible to operate more stably.

Since the second embodiment of the present invention is the same as the first embodiment except that the power supply unit (PSU) uses the second frame as the base voltage source together with the scan drive board and the Z sustainer board, the first embodiment is implemented. Description of the same configuration and operation as the example will be omitted.

Referring to FIG. 5, in the PDP according to the second embodiment of the present invention, the PDP includes a front case 40, a panel 42, a heat dissipation sheet 44, a first frame 86, a second frame 88, and a PCB. 89 and a back cover 50 are provided.

The first frame 86 dissipates heat from the heat dissipation sheet 44 and the second frame 88 to the outside, and supports the second frame 88, the controller board, and the data driving board, and their bases. Used as a voltage source. To this end, the first frame 86 is provided with fastening means for fixing the controller board and the data driving board.

The second frame 88 fixes and supports the scan drive board and the sustainer board, and is used as the base voltage source of the power supply, the scan drive board, and the Z sustainer board. In addition, heat generated from the power supply unit, the scan drive board, and the Z sustainer board is discharged together with the first frame 86 to prevent the temperature of the board from rising rapidly. To this end, the second frame 88 is provided with fastening means for fixing the power supply unit, the scan drive board and the Z sustainer board.

Here, the first frame 86 and the second frame 88 must be insulated or separated to be used as the base voltage source of the respective boards. To this end, a heat-reducing body such as a urethane pad is inserted between the first frame 86 and the second frame 88, or a spacer for maintaining a gap between the first frame 86 and the second frame 88 is inserted. Should be.

The PCB 89 includes a scan drive board for driving scan electrode lines formed in the panel 42, a Z sustainer board for driving sustain electrode lines, a data drive board for driving data electrode lines, a scan drive board, A controller board for controlling the Z sustainer board and the data driving board and a power supply unit for supplying power for operating each board. The scan drive board, the Z sustainer board, and the power supply are supported and fixed by the second frame 88, and use the second frame 88 as the base voltage source. In addition, the data driving board and the controller board are supported and fixed by the first frame 86, and the first frame 86 is used as the base voltage source.

10 is a view showing a PDP rear structure according to the second embodiment of the present invention.

Referring to FIG. 10, the PDP according to the second embodiment of the present invention may include a scan driving board 53 and sustain electrode lines Z1 to Zm for driving the scan electrode lines Y1 to Ym of the panel 42. Z sustainer board 57 for driving), data driving board 52 and scan driving board 53 for driving data electrode lines X1 to Xm, Z sustainer board 57 and data driving A controller board 56 for controlling the board 52 is provided. In addition, a power supply 90 for supplying power to these boards is fixed to the second frame 88.

As shown in FIG. 10, the second frame 88 bypasses the controller board 56 to connect and support the scan driving board 53, the power supply unit 90, and the Z sustainer board 57. The scan driving board 53, the power supply unit 90, and the Z sustainer board 57 share the base voltage source by the second frame 88 connected as shown in FIG. 10.

The second embodiment described above can maintain the base voltage more stably than the first embodiment. When only the scan driving board 53 and the Z sustainer board 57 use the base voltage source, because the two driving boards 53 and 57 supply driving voltages for driving the electrodes, the base voltage is shaken. In addition, since the drive voltages generated by the scan drive board 53 and the Z sustainer board 57 are high, the potential becomes high even if the base voltage is kept stable.

In the second embodiment, the base voltage source is shared with the power supply unit 90 which maintains the voltage relatively stably, and thus the potential of the base voltage of the scan driving board 53 and the Z sustainer board 57 is more stably maintained. It is possible to lower the potential of the ground voltage.

For this reason, in the second embodiment of the present invention, the scan driving board 53 and the Z sustainer board 57 may use a base voltage source different from that of the data driving board 52 and the controller board 56. This makes it possible to keep the base voltages of the respective boards relatively uniform, which makes it possible to operate more stably.

According to the first and second embodiments of the present invention described above, the shapes of the second frames 48 and 88 used in the scan driving board 53, the Z sustainer board 57, and the power supply unit 90 may be integral. It can be manufactured detachably. When the integrated second frames 48 and 88 are used, the scan driving board 53, the Z sustainer board 57, and the power supply unit 90 may use the same base voltage source, which is called the second frame 48 and 88. will be. In addition, when the separate second frames 48 and 88 are used, the scan driving board 53, the Z sustainer board 57, and the power supply unit 90 may use respective base voltage sources.

As described above, the PDP according to the present invention separates the frame supporting the scan driving board and the Z sustainer board or the scan driving board, the Z sustainer board and the power supply from the frame supporting the data driving board. Thereby, it is possible to lower the potential of the base voltage of each circuit and to reduce vibration. In addition, it is possible to maintain stable operation of the PDP due to the base voltage that is stably maintained.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (8)

A panel having discharge cells formed on the substrate by data electrodes, scan electrodes, and sustain electrodes; A first circuit board on which a circuit for driving the data electrode is formed; A second circuit board on which a circuit for driving the scan electrode is formed; A third circuit board having a circuit for driving the sustain electrode; A first frame installed at a rear surface of the panel to support the first circuit board and to provide a base voltage to the first circuit board; A second frame coupled to the first frame, supporting the second circuit board and the third circuit board, and providing a base voltage to at least one of the second and third circuit boards; And an insulating layer between the first frame and the second frame to insulate the first frame from the second frame. The method of claim 1, And the second frame provides a base voltage to both the second circuit board and the third circuit board. The method of claim 1, Further provided with a power supply for supplying power to the first to third circuit board, And the power supply unit receives a base voltage by the second frame. delete The method of claim 1, And a spacer formed between the first frame and the second frame such that the first frame and the second frame do not contact each other. The method of claim 1, And the first frame or the second frame is a conductive plastic. The method of claim 3, wherein And the second frame is integrally formed to supply the base voltage to at least one of the second circuit board, the third circuit board, and the power supply unit. The method of claim 3, wherein And a plurality of second frames are formed separately and supply the base voltage to each of the second circuit board, the third circuit board, and the power supply unit separately.

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