KR20040108416A - Plasma Display Panel And Module thereof - Google Patents

Abstract

PURPOSE: A plasma display panel and a plasma display module are provided to simplify the configuration of the circuit board of the plasma display panel by integrating a Y sustain circuit and a Z sustain circuit into one circuit board and to reduce electromagnetic interference. CONSTITUTION: A plasma display module includes a plasma display panel(170), an integrated driving board(175), the first conductive path(176), and the second conductive path(178). The plasma display panel includes scan electrode lines, sustain electrode lines, data electrode lines and common electrode lines commonly connected to the sustain electrode lines. The plasma display panel further includes the first pad connected to the scan electrode lines and the second pad(197) connected to the common electrode lines. The first and second pads are formed at one side of the plasma display panel. The integrated driving board drives the scan electrode lines and the sustain electrode lines. The first conductive path is connected between one side of the integrated driving board and the first pad. The second conductive path is connected to one side of the integrated driving board and the second pad.

Description

Plasma display panel and module thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel and a module thereof, and more particularly, to a plasma display panel and a module thereof for simplifying an assembly process and reducing electromagnetic interference in an integrated sustainer board.

Recently, plasma display panels (hereinafter referred to as PDPs), which are easy to manufacture large panels, have attracted attention as flat panel display devices. The PDP typically displays an image by adjusting the gas discharge period of each of the pixels in accordance with digital video data. As such a PDP, an AC type PDP having three electrodes and driven by an AC voltage is typical.

1 is an enlarged view of one discharge cell constituting a conventional AC PDP.

The discharge cell 30 shown in FIG. 1 includes an upper plate having sustain electrode pairs 12A and 12B, an upper dielectric layer 14 and a protective film 16 sequentially formed on the upper substrate 10, and a lower substrate 18. A lower plate having a data electrode 20, a lower dielectric layer 22, a partition wall 24, and a phosphor layer 26 sequentially formed thereon is provided.

Each of the sustain electrode pairs 12A and 12B is composed of a transparent electrode and a metal electrode for compensating for the high resistance of the transparent electrode. The sustain electrode pairs 12A and 12B are separated into the scan electrode 12A and the sustain electrode 12B. The scan electrode 12A mainly supplies a scan signal for address discharge and a sustain signal for sustain discharge, and the sustain electrode 12B mainly supplies a sustain signal. The data electrode 20 is formed to cross the sustain electrode pairs 12A and 12B. This data electrode 20 supplies a data signal for address discharge.

Charges generated by discharge are accumulated in the upper dielectric layer 14 and the lower dielectric layer 22. The protective film 16 prevents damage to the upper dielectric layer 14 due to sputtering during discharge and increases the emission efficiency of secondary electrons. The dielectric layers 14 and 22 and the protective layer 16 may lower the discharge voltage applied from the outside.

The partition wall 24 provides a discharge space together with the upper and lower substrates 10 and 18. The partition wall 24 is formed in parallel with the data electrode 20 to prevent ultraviolet rays generated by the gas discharge from leaking into adjacent cells. The phosphor layer 26 is applied to the surfaces of the lower dielectric layer 22 and the partition wall 24 to generate red, green or blue visible light. The discharge space is filled with an inert gas such as He, Ne, Ar, Xe, Kr for gas discharge, a discharge gas having a combination thereof, or an excimer gas capable of generating ultraviolet rays by discharge.

The discharge cell 30 having such a structure is selected as the counter discharge by the data electrode 20 and the scan electrode 12A, and then maintains the discharge by surface discharge by the sustain electrode pairs 12A and 12B. Accordingly, in the discharge cell 30, visible light is emitted by the phosphor 26 emitting light by ultraviolet rays generated during sustain discharge. In this case, the discharge cell 30 adjusts the sustain discharge period, that is, the number of sustain discharges according to the video data, thereby implementing gray scale required for displaying an image. In addition, a color of one pixel is realized by a combination of three discharge cells coated with red, green, and blue phosphors 26, respectively.

FIG. 2 illustrates the overall electrode arrangement structure of the PDP including the discharge cells 30 shown in FIG. 1. In FIG. 2, it can be seen that the discharge cells 30 are configured at the intersections of the scan electrode lines Y1 to Ym, the sustain electrode lines Z1 to Zm, and the data electrode lines X1 to Xn.

The scan electrode lines Y1 to Ym supply the scan pulses and the sustain pulses so that the discharge cells 30 are scanned in units of lines, and the discharges are maintained in the discharge cells 30. The sustain electrode lines Z1 to Zm commonly supply a sustain pulse to maintain the discharge in the discharge cells 30 together with the scan electrode lines Y1 to Ym. The data electrode lines X1 to Xn supply data pulses synchronized with the scan pulse in line units so that the discharge cells 30 in which discharge is to be maintained are selected according to the logic value of the data pulses.

The PDP driving method is typically an ADS (Address and Display Separation) driving method which is driven by being separated into an address period and a display period, that is, a sustain period. In the ADS driving method, one frame is divided into a plurality of subfields corresponding to each bit of video data, and each of the subfields is divided into a reset period, an address period, and a sustain period. Each of these subfields has the same reset period (RPD) and address period (APD) and gives different weights to the sustain period (SPD). Accordingly, the PDP expresses a gray level corresponding to the video data in a combination of sustain periods in which discharge is maintained in accordance with the video data.

FIG. 3 illustrates a general driving waveform supplied to the PDP shown in FIG. 2 in one subfield SF1 among a plurality of subfields.

As shown in FIG. 3, the PDP initializes all of the discharge cells 30 to an off state in which wall charge remains by erasing wall charges after the front writing discharge is generated using the reset pulse RP in the reset period RPD. Let's do it. To this end, the scan electrode lines Y1 to Ym have a reset pulse RP, which gradually decreases to a rising ramp pulse and a base voltage 0V that gradually increase to the peak voltage Vr based on the step voltage Vs. A falling ramp pulse is supplied. The first dark discharge occurs in all the discharge cells 30 by the rising ramp pulse. Then, secondary dark discharge occurs in all the discharge cells 30 by the falling ramp pulse and the bias pulse BP supplied to the sustain electrode lines Z1 through Zm. Subsequently, the wall charges formed in the scan electrode lines Y1 to Ym and the sustain electrode lines Z1 to Zm decrease according to the falling ramp pulse, and thus all the discharge cells 30 are initialized to the off state where the wall charges remain. do. In this reset period RPD, the voltages of the data electrode lines X1 to Xn are fixed to the base voltage 0V.

In the address period APD, the scan pulse SP is supplied to the scan electrode lines Y1 to Ym on a line basis, and a data pulse is applied to each of the data electrode lines X1 to Xn in synchronization with the scan pulse SP. (DP) is optionally supplied. As a result, address discharge is generated in the discharge cells supplied with the data pulse DP together with the scan pulse SP, so that the wall charge for the next sustain discharge is sufficiently formed. On the other hand, in the discharge cells to which the data pulse DP is not supplied together with the scan pulse SP, the address discharge does not occur, thereby maintaining the off state.

In the sustain period SPD, Y and Z sustain pulses SUSPy and SUSPz are alternately supplied to the scan electrode lines Y1 to Ym and the sustain electrode lines Z1 to Zm to determine the address period APD. The state of the discharge cell is maintained. Specifically, the discharge cells in the on state in which the wall charges are sufficiently formed in the address period APD remain in the on state by the discharge by the Y and Z sustain pulses SUSPy and SUSPz, and the discharge cells in the off state are in the off state without discharge. Keep it.

The wall charges present in all the discharge cells 30 are generated by supplying the erase pulse EP to the sustain electrode lines Z1 to Zm in the erase period EPD subsequent to the sustain period SPD. To be cleared.

In order to supply these driving waveforms to the PDP shown in FIG. 2, the driving device is provided on the rear surface of the heat sink 64 located on the back side of the PDP 40 as shown in FIGS. 4 and 5.

4 and 5 illustrate a Y driving board 45 for driving the scan electrode lines Y1 to Ym of the PDP 40, and a sustain electrode lines Z1 to Zm for driving the scan electrode lines Y1 to Ym of the PDP 40. A Z sustainer board 48, a data driver board 50 for driving the data electrode lines X1 to Xm, the Y drive board 45, the Z sustainer board 48, and a data driver board ( Control board 42 for controlling 50, and a power board (not shown) for supplying power to each of the boards (42, 45, 48, 50).

The Y drive board 45 includes a scan driver board 44 for generating the reset pulse RP and the scan pulse SP shown in FIG. 3 of the PDP 40, and a Y suspend for generating the Y sustain pulse SUSPy. A retainer board 46 is provided. The scan driver board 44 supplies the scan pulse SP to the scan electrode lines Y1 to Ym of the PDP 40 via the Y conductive path 51. The Y sustainer board 46 supplies the Y sustain pulse SUSPy to the scan electrode lines Y1 to Ym via the scan driver board 44 and the Y conductive path 51.

The Z sustainer board 48 generates the bias pulse BP and the Z sustain pulse SUSz shown in FIG. 3, and the sustain electrode lines Z1 to Zm of the PDP 40 via the Z conductive path 52. Supplies).

The data driver board 50 generates the data pulse DP shown in FIG. 3 and supplies it to the data electrode lines X1 to Xn of the PDP 40 via the X conductive path 54.

The control board 42 generates each of the X, Y, and Z timing control signals. The control board 42 transmits the Z timing control signal to the Y driving board 45 via the first conductive path 56 and the Z timing control signal via the second conductive path 58 to the Z sustainer board. At 48, the X timing control signal is supplied to the data driver board 50 via the third conductive path 60.

At this time, each conductive path is any one of a flexible flat cable and a flexible printed cable.

When driving the PDP module having such a configuration, the current path in the sustain period SPD is as follows. First, when the Y sustain pulse SUSPy is supplied to the scan electrode lines Y1 to Ym from the Y drive board 45, the first current path is Y drive board 45-> scan electrode lines Y1 to Ym. -> Panel capacitor-> sustain electrode line (Z1 to Zm)-> Z sustainer board 48-> heat sink 64-> Y drive board 45. When the Z sustain pulse SUSPz is supplied to the sustain electrode lines Z1 to Zm in the Z sustainer board 48, the second current path is Z sustainer board 48-> sustain electrode line Z1 to Zm. Zm)-> panel capacitor-> scan electrode line (Y1 to Ym)-> Y drive board 45-> heat sink 64-> Z sustain board 48.

However, the PDP module shown in FIGS. 4 and 5 is installed separately from the Y sustainer board 46 and the Z sustainer board 48 which perform similar functions in the same driving cycle, thereby providing a large number of circuit components (switching elements). Etc.) and power consumption increases. Accordingly, the conventional PDP module has a problem in that its configuration is complicated and manufacturing cost is high. In order to solve such a problem, a PDP module (published number 2003-0012696) as shown in FIG. 6 in which a Y sustainer board and a Z sustainer board are integrated has been proposed.

FIG. 6 is a PDP module incorporating a conventional Y and Z sustainer board, and FIG. 7 is a cross-sectional view of the PDP module shown in FIG.

The PDP module shown in FIGS. 6 and 7 includes a PDP 70, a heat sink 86 provided on the rear surface of the PDP 70, a YZ integrated board 75 and a data driver board provided on the back surface of the heat sink 86. 80 and a control board 72 and a power board (not shown) for supplying power to each of the boards 75, 80, and 72.

The PDP 70 has a structure in which the upper plate 90 and the lower plate 92 are joined while providing a gas discharge space. Here, scan electrode lines Y1 to Ym and sustain electrode lines Z1 to Zm are formed in parallel on the upper plate 90, and data electrode lines X1 to Xn on the lower plate 92. Is formed. In addition, a Y pad region 94 is provided at one side of the upper plate 90 to provide Y pads (not shown) connected to the scan electrode lines, and a Z pad region 96 is provided at the other side of the upper plate 90 to sustain electrode lines ( Z pads (not shown) connected to the not shown are formed. In addition, an X pad area (not shown) is formed at one side of the lower plate 92 to form X pads (not shown) connected to data lines. The upper plate 90 and the lower plate 92 are bonded to expose the Y pad region 94, the Z pad region 96, and the X pad region (not shown).

The heat sink 86 allows heat generated in the PDP 70 to be easily released to the outside. To this end, the heat sink 86 is installed so as to entirely overlap the rear surface of the PDP (70).

The control board 72 generates each of the X, Y, and Z timing control signals. The control board 72 transfers the Y and Z timing control signals to the YZ integrated board 100 via the first conductive path 76 and the X timing control signal via the second conductive path 78. Supply to board 80.

The data driver board 80 generates a data pulse DP using the X timing control signal from the control board 72 as shown in FIG. 3, and the data electrode line of the PDP 70 via the X conductive path 88. Feed the fields. Here, the X conductive path 88 is connected to an X pad region (not shown) provided in the data driver board 80 and the PDP 70.

The Y-Z integrated board 100 is composed of a scan driver board 73 and a Y-Z sustainer board 74 and a connector 75 for connecting the two boards 73 and 74.

The scan driver board 73 uses the Y timing control signal from the control board 72 to reset the pulse RP to be supplied to the scan electrode lines in the reset period APD as shown in FIG. 3, and the address period APD. Generates a scan pulse SP to be supplied at. The scan driver board 73 supplies the reset pulse RP and the scan pulse SP to the scan electrode lines of the PDP 70 via the Y conductive path 82.

Here, the Y conductive path 82 is connected to the scan driver board 73 and the Y pad region 94 of the PDP 70 as shown in FIG. 7.

The YZ sustainer board 74 uses the Y and Z timing control signals from the control board 72 to generate the Y sustain pulse SUSPy to be supplied to the scan electrode lines in the sustain period SPD as shown in FIG. Alternating with the Y sustain pulse SUSPy, a Z sustain pulse SUSPz to be supplied to the sustain electrode lines is generated. The Y-Z sustainer board 74 generates a bias pulse BP to be supplied to the sustain electrode lines in the reset period RPD and the address period APD as shown in FIG. 3. To this end, the YZ sustainer board 100 includes a Y sustain circuit (not shown) for generating a Y sustain pulse (SUSPy), and a Z sustain circuit (not shown) for generating a bias pulse (BP) and a Z sustain pulse (SUSPz). ). The YZ sustainer board 74 supplies the Y sustain pulse SUSPy to the scan electrode lines of the PDP 70 via the connector 75-> scan driver board 73-> Y conductive path 82. do. The Y-Z sustainer board 74 supplies the bias pulse BP and the Z sustain pulse SUSPz to the sustain electrode lines of the PDP 70 via the Z conductive path 84.

Here, the Z conductive path 84 is connected to the Y-Z sustainer board 74 and the Z pad region 96 of the PDP 70 as shown in FIG.

In this way, the Y conductive path 82 is connected to the scan driver board 73, and the Z conductive path 84 is connected to the Y-Z sustainer board 74. Here, the Y conductive path 82 is connected to the front side (reference to the PDP 70) or the back side of the scan driver board 73, and the Z conductive path 82 is connected to the front side or the rear side of the YZ sustainer board 74. do.

When driving the PDP module having such a configuration, the current path in the sustain period SPD is as follows. First, when the YZ sustainer board 74 supplies the Y sustain pulse SUSPy to the scan electrode lines of the PDP 70, the first current path is YZ sustainer board 74-> connector-> scan driver board. (73)-> Y conductive path (82)-> scan electrode line-> panel capacitor-> sustain electrode line-> Z conductive path (84)-> YZ sustainer board (74). In addition, the second current path through which the YZ sustainer board 74 supplies the Z sustain pulse SUSPz to the sustain electrode lines of the PDP 70 is YZ sustainer board 74-> Z conductive path 84-. > Sustain electrode line-> panel capacitor-> scan electrode line-> Y conductive path 82-> scan driver board 73-> connector 75-> YZ sustainer board 74.

At this time, each of the conductive paths is any one of a flexible flat cable and a flexible printed cable.

In this PDP module, the Z conductive path 84 is susceptible to or subject to electromagnetic interference (EMI) on the control board 72 or a power board (not shown), resulting in an inductance of the Z conductive path 84. There is a possibility to increase. Therefore, when the YZ sustainer board 74 and the sustain electrode lines are connected by using the long Z conductive path 84, electromagnetic shielding must be performed to reduce noise or inductance. There is a problem that is easy to tear.

Accordingly, it is an object of the present invention to provide a plasma display panel and a module thereof that simplify the assembly process and reduce electromagnetic interference in an integrated sustainer board.

1 is a perspective view showing a discharge cell of a conventional three-electrode alternating current plasma display panel.

2 is an overall electrode layout of a typical plasma display panel.

FIG. 3 is a driving waveform diagram of the plasma display panel shown in FIG. 2.

4 is a diagram illustrating a rear structure of a conventional plasma display panel module.

FIG. 5 is a cross-sectional view of the plasma display panel module shown in FIG. 4. FIG.

FIG. 6 illustrates a rear structure of a plasma display panel module incorporating a conventional Y and Z sustainer board. FIG.

FIG. 7 is a sectional view of the plasma display panel module shown in FIG. 6; FIG.

8 illustrates a rear structure of the plasma display panel module according to the first embodiment of the present invention.

FIG. 9 is a sectional view of the plasma display panel module shown in FIG. 8; FIG.

FIG. 10 is a view illustrating in detail a plasma display panel of the plasma display panel module shown in FIG. 8; FIG.

FIG. 11 illustrates a rear structure of a plasma display panel module according to a second embodiment of the present invention; FIG.

12 is a cross-sectional view of the plasma display panel module shown in FIG.

FIG. 13 is a view illustrating in detail a plasma display panel of the plasma display panel module illustrated in FIG. 11.

<Brief description of symbols for the main parts of the drawings>

10: upper substrate 18: lower substrate

12A: Scanning electrode 12B: Sustaining electrode

14 upper dielectric layer 16 protective film

20: data electrode 22: lower dielectric layer

24: partition 26: phosphor

30: discharge cell 40, 70, 170, 270: PDP

42,72,172,272: Control Board 44,73,173,273: Scan Driver Board

45: Y drive board 46: Y sustainer board

48: Z sustainer board 50,80,180,280: data driver board

51,52,54,56,58,60,76,78,82,84,88,176,178,182,184,188,276,278,282,284,288,297a, 297b

61,90,190,290: Upper panel 62,92,192,292: Lower panel

64,86,186,286: Heat Sink 74,174,274: Y-Z Sustainer Board

75,175,275: Connector 100,200,300: Y-Z Integrated Board

191a, 191b, 191c: First to third common electrode lines

94, 96: Y and Z pad areas 194, 294: first area

196,296 Second area 195,295 Y pad

197,297: Z Pad

In order to achieve the above object, a plasma display panel module according to an embodiment of the present invention includes scan electrode lines, sustain electrode lines, data electrode lines, and common electrode lines commonly connected to the sustain electrode lines. A plasma display panel having a first pad connected to scan electrode lines and a second pad connected to the common electrode line; An integrated driving board for driving the scan electrode lines and the sustain electrode lines; A first conductive path connected between one side of the integrated driving board and the first pad; And a second conductive path connected between one side of the integrated drive board and the second pad.

In the plasma display panel module according to an exemplary embodiment of the present invention, the common electrode lines are formed in a non-display area.

In the plasma display panel module according to an embodiment of the present invention, the common electrode lines are formed on the other side of the plasma display panel and are connected to the sustain electrode lines in common; A second common electrode line formed on an upper side of the plasma display panel and connected to one side of the first common electrode line; And a third common electrode line formed at a lower side of the plasma display panel and connected to the other side of the first common electrode line.

In the plasma display panel module according to an embodiment of the present invention, the first common electrode line and the second and third common electrode lines may be formed on the same substrate.

In the plasma display panel module according to an embodiment of the present invention, at least one common electrode line of the first to third common electrode lines may be formed on another substrate.

In the plasma display panel module according to an exemplary embodiment of the present invention, the first common electrode line and the second and third common electrode lines may be formed on different substrates.

In the plasma display panel module according to an exemplary embodiment of the present invention, the second and third common electrode lines may be formed on the same substrate as the sustain electrode lines.

In the plasma display panel module according to an exemplary embodiment of the present invention, the plasma display panel further includes a connection part for connecting the first common electrode line and the second and third common electrode lines.

In the plasma display panel module according to the embodiment of the present invention, the connection part may be any one of a flexible flat cable and a flexible printed cable.

In the plasma display panel module according to the embodiment of the present invention, the first pad and the second pad may be formed on the same substrate.

In the plasma display panel module according to an exemplary embodiment of the present invention, the first pad and the second pad may be formed on different substrates.

In the plasma display panel module according to an embodiment of the present invention, the first and second conductive paths may be any one of a flexible flat cable and a flexible printed cable.

In the plasma display panel module according to an embodiment of the present invention, the integrated driving board includes: a scan driver board generating a scan pulse to be supplied to the scan electrode lines; An integrated sustainer board for generating a first sustain pulse to be supplied to scan electrode lines and a second sustain pulse to be supplied to the sustain electrode lines; And a connector for connecting the scan driver board and the integrated sustainer board.

A plasma display panel module according to an embodiment of the present invention includes a heat sink for dissipating heat from the plasma display panel; A data driver and a board for generating a data pulse to be supplied to the data electrode lines; A control board for supplying a corresponding control signal to each of the scan driver board and the integrated board and the data driver board; It further includes a power board for supplying power to each of the boards.

According to an exemplary embodiment of the present invention, a plasma display panel includes scan electrode lines, sustain electrode lines, and data electrode lines; Common electrode lines commonly connected to the sustain electrode lines; A first pad connected to the scan electrode lines; A second pad connected to the common electrode lines; The first and second pads may be formed at one side of the plasma display panel.

In the plasma display panel according to an exemplary embodiment of the present invention, the common electrode lines are formed in a non-display area.

In the plasma display panel according to the embodiment of the present invention, the common electrode lines are formed on the other side of the plasma display panel and are connected to the sustain electrode lines in common; A second common electrode line formed on an upper side of the plasma display panel and connected to one side of the first common electrode line; And a third common electrode line formed at a lower side of the plasma display panel and connected to the other side of the first common electrode line.

In the plasma display panel according to an exemplary embodiment of the present invention, the first common electrode line and the second and third common electrode lines may be formed on the same substrate.

In the plasma display panel according to an exemplary embodiment of the present invention, at least one common electrode line among the first to third common electrode lines may be formed on another substrate.

In the plasma display panel according to an exemplary embodiment of the present invention, the first common electrode line and the second and third common electrode lines may be formed on different substrates.

In the plasma display panel according to an exemplary embodiment of the present invention, the second and third common electrode lines may be formed on the same substrate as the sustain electrode lines.

In the plasma display panel according to the embodiment of the present invention, the plasma display panel further includes a connection part for connecting the first common electrode line and the second and third common electrode lines.

In the plasma display panel according to the embodiment of the present invention, the connection part may be any one of a flexible flat cable and a flexible printed cable.

In the plasma display panel according to an exemplary embodiment of the present invention, the first pad and the second pad may be formed on the same substrate.

In the plasma display panel according to an exemplary embodiment of the present invention, the first pad and the second pad may be formed on different substrates.

Other objects and advantages of the present invention in addition to the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 8 to 13.

8 illustrates a PDP module according to a first embodiment of the present invention, FIG. 9 illustrates a cross-sectional structure of the PDP module illustrated in FIG. 8, and FIG. 10 illustrates a PDP illustrated in FIG. 8.

The PDP module illustrated in FIGS. 8 and 9 includes a PDP 170, a heat sink 186 provided on the rear surface of the PDP 170, a YZ integrated board 175 and a data driver board installed on the rear surface of the heat sink 186. 180 and a control board 172 and a power board (not shown) for supplying power to each of the boards (175, 180, 172).

The PDP 170 has a structure in which the upper plate 190 and the lower plate 192 are bonded while providing a gas discharge space, as shown in FIG. 10. Here, the scan electrode lines and the sustain electrode lines are formed in parallel on the upper plate 190, and the data electrode lines are formed on the lower plate 192. In addition, a second region 196 is formed at one side of the upper plate 190, which is a non-display area, to form a first common electrode line 191a connected to the sustain electrode lines in common, and the upper plate 190, which is a non-display area. The second common electrode line 191b connected to one side of the first common electrode line 191a is formed on the upper side of the upper side of the first side, and the first common electrode line 191a is disposed on the lower side of the upper plate 190 which is a non-display area. A third common electrode line 191c is formed to be connected to the other side of In addition, a first region 194 is provided at the other side of the upper plate 190, which is a non-display region, and one of the Y pad 195 and the second and third common electrode lines 191b and 191c connected to the scan electrode lines. A Z pad 197 connected with the side portion is formed. In addition, an X pad area (not shown) is formed at one side of the lower plate 192 to form an X pad (not shown) connected to the data lines. The upper plate 190 and the lower plate 192 are bonded to expose the first region 194, the second region 196, and the X pad region (not shown).

The heat sink 186 allows heat generated from the PDP 170 to be easily released to the outside. To this end, the heat sink 186 is installed so as to overlap the entire back surface of the PDP 170.

The control board 172 generates each of the X, Y, and Z timing control signals. The control board 172 transfers the Y and Z timing control signals to the YZ integrated board 200 via the first conductive path 176 and the X timing control signal via the second conductive path 178. Supply to the board 180.

The data driver board 180 generates a data pulse DP using the X timing control signal from the control board 172 and the data electrode line of the PDP 170 via the X conductive path 188 as shown in FIG. 3. Feed the fields. Here, the X conductive path 188 is connected to an X pad region (not shown) provided in the data driver board 180 and the PDP 170.

The Y-Z integration board 200 is composed of a scan driver board 173 and a Y-Z sustainer board 174, and a connector 175 for connecting the two boards 173 and 174.

The scan driver board 173 receives the reset pulse RP to be supplied to the scan electrode lines in the reset period APD as shown in FIG. 3 using the Y timing control signal from the control board 172, and the address period APD. Generates a scan pulse SP to be supplied at. The scan driver board 173 supplies the reset pulse RP and the scan pulse SP to the scan electrode lines of the PDP 170 via the Y conductive path 182.

Here, the Y conductive path 182 is connected to the scan driver board 173 and the first region 194 of the upper plate 190 of the PDP 170 as shown in FIG. 10.

The YZ sustainer board 174 uses the Y and Z timing control signals from the control board 72 to generate the Y sustain pulse SUSPy to be supplied to the scan electrode lines in the sustain period SPD as shown in FIG. Alternating with the Y sustain pulse SUSPy, a Z sustain pulse SUSPz to be supplied to the sustain electrode lines is generated. The Y-Z sustainer board 174 generates a bias pulse BP to be supplied to the sustain electrode lines in the reset period RPD and the address period APD as shown in FIG. 3. To this end, the YZ sustainer board 174 includes a Y sustain circuit (not shown) for generating a Y sustain pulse (SUSPy), and a Z sustain circuit (not shown) for generating a bias pulse (BP) and a Z sustain pulse (SUSPz). ). The YZ sustainer board 174 receives the Y sustain pulse SUSPy through the connector 175-> scan driver board 173-> Y conductive path 182, and thus the first plate of the upper plate 190 of the PDP 170. The Y pads 195 provided in the region 194 are supplied to the scan electrode lines. The YZ sustainer board 174 includes a bias pulse BP and a Z sustain pulse SUSPz in the first region 194 of the upper plate 190 of the PDP 70 via the Z conductive path 184. The pads 197 are supplied to the first to third common electrode lines 191a, 191b, and 191c connected to the sustain electrode lines in common to the sustain electrode lines.

Here, the Z conductive path 184 is connected to the Y-Z sustainer board 74 and the first region 194 of the upper plate 190 of the PDP 170 as shown in FIG. 10.

In this manner, the Y conductive path 182 is connected to the scan driver board 173, and the Z conductive path 184 is connected to the Y-Z sustainer board 174. Here, the Y conductive path 182 is connected to the front side (reference to the PDP 170) or the back side of the scan driver board 173, and the Z conductive path 182 is connected to the front side or the rear side of the YZ sustainer board 174. do.

When driving the PDP module having such a configuration, the current path in the sustain period SPD is as follows. First, when the YZ sustainer board 174 supplies the Y sustain pulse SUSPy to the scan electrode lines of the PDP 170, the first current path is YZ sustainer board 174-> connector 175->. Scan driver board 173-> Y conductive path 182-> scan electrode line-> panel capacitor-> sustain electrode line-> first common electrode line 191a-> second and third common electrode line 191b 191c)-> Z conductive path 184-> YZ sustainer board (174). In addition, the second current path through which the YZ sustainer board 174 supplies the Z sustain pulse SUSPz to the sustain electrode lines of the PDP 170 is YZ sustainer board 174-> Z conductive path 184-. > Second and third common electrode lines 191b and 191c-> first common electrode line 191a-> sustain electrode line-> panel capacitor-> scan electrode line-> Y conductive path 182-> scan driver Board 173-> connector 175-> YZ sustainer board 174.

At this time, each of the conductive paths is any one of a flexible flat cable and a flexible printed cable.

In the PDP module, the first to third common electrode lines 191a, 191b, and 191c commonly connected to the sustain electrode lines are electromagnetically connected to the control board 172 or the power board (not shown) by the heat sink 186. The interference EMI can be shielded. In addition, the assembly process can be simplified by connecting the Y conductive path 182 and the Z conductive path 184 together to one side of the PDP 170. In particular, it is possible to minimize the inductance on the path to increase the energy recovery efficiency.

FIG. 11 illustrates a PDP module according to a second embodiment of the present invention, FIG. 12 illustrates a cross-sectional structure of the PDP module illustrated in FIG. 11, and FIG. 13 illustrates a PDP illustrated in FIG. 11.

The PDP module illustrated in FIGS. 11 and 12 includes a PDP 270, a heat sink 286 provided on the rear surface of the PDP 270, a YZ integrated board 275 and a data driver board provided on the rear surface of the heat sink 286. 280, a control board 272, and a power board (not shown) for supplying power to each of the boards 275, 280, and 272.

As illustrated in FIG. 13, the PDP 270 has a structure in which the upper plate 290 and the lower plate 292 are bonded while providing a gas discharge space. Here, scan electrode lines and sustain electrode lines are formed in parallel on the upper plate 290, and data electrode lines are formed in the lower plate 292. In addition, a second region 296 is formed at one side of the upper plate 290, which is a non-display area, to form a first common electrode line 291a connected to the sustain electrode lines in common, and the lower plate 292 is a non-display area. The second common electrode line 291b is formed on the upper side of the bottom side, and the third common electrode line 291c is formed on the lower side of the lower plate 292, which is a non-display area. In other words, in the second embodiment of the present invention, the first common electrode line 291a is formed on the upper plate 290 of the PDP, and the second and third common electrode lines 291b and 291c are the lower plate 292 of the PDP. Is formed. In addition, a first region 294 is formed on the other side of the upper plate 290, which is a non-display area, to form a Y pad 295 connected to scan electrode lines, and an upper portion of the lower plate 292, which is a non-display area, and A Z pad 297 connected to one side of the second and third common electrode lines 291b and 291c formed at the lower side is formed in the non-display area of the lower plate 292. In this case, the Y and Z pads 295 and 297 may be formed on the same substrate. The Y pad 295 formed on the upper plate 290 and the Z pad 297 formed on the lower plate 292 are formed at one side of the PDP 270. In addition, an X pad region (not shown) is formed at one side of the lower plate 292 to form an X pad (not shown) connected to data lines. The upper plate 290 and the lower plate 292 are bonded to expose the first region 294, the second region 296, and the X pad region (not shown).

The heat sink 286 allows heat generated in the PDP 270 to be easily released to the outside. To this end, the heat sink 286 is installed to overlap the entire back surface of the PDP 270.

The control board 272 generates each of the X, Y, and Z timing control signals. The control board 272 transmits the Y and Z timing control signals to the YZ integrated board 300 via the first conductive path 276 and the X timing control signals through the second conductive path 278. Supply to board 280.

The data driver board 280 generates a data pulse DP using the X timing control signal from the control board 272 as shown in FIG. 3 and the data electrode line of the PDP 270 via the X conductive path 288. Feed the fields. Here, the X conductive path 288 is connected to an X pad region (not shown) provided in the data driver board 280 and the PDP 270.

The Y-Z integration board 300 includes a scan driver board 273 and a Y-Z sustainer board 274, and a connector 275 for connecting the two boards 273 and 274.

The scan driver board 273 uses the Y timing control signal from the control board 272 to generate the reset pulse RP to be supplied to the scan electrode lines in the reset period APD as shown in FIG. 3, and the address period APD. Generates a scan pulse SP to be supplied at. The scan driver board 173 supplies the reset pulse RP and the scan pulse SP to the scan electrode lines of the PDP 270 via the Y conductive path 282.

Here, the Y conductive path 282 is connected to the scan driver board 273 and the first region 294 of the upper plate 290 of the PDP 270 as shown in FIG. 12.

The YZ sustainer board 274 uses the Y and Z timing control signals from the control board 272 to generate the Y sustain pulse SUSPy to be supplied to the scan electrode lines in the sustain period SPD as shown in FIG. Alternating with the Y sustain pulse SUSPy, a Z sustain pulse SUSPz to be supplied to the sustain electrode lines is generated. The Y-Z sustainer board 274 generates a bias pulse BP to be supplied to the sustain electrode lines in the reset period RPD and the address period APD as shown in FIG. 3. To this end, the YZ sustainer board 274 includes a Y sustain circuit (not shown) for generating a Y sustain pulse (SUSPy), and a Z sustain circuit (not shown) for generating a bias pulse (BP) and a Z sustain pulse (SUSPz). ). The YZ sustainer board 274 receives the Y sustain pulse SUSPy via the connector 275-> scan driver board 273-> Y conductive path 282 to form the first surface of the top plate 290 of the PDP 270. Supply to the scan electrode lines through the Y pad 295 provided in the region (294). The YZ sustainer board 274 maintains the bias pulse BP and the Z sustain pulse SUSPz through the Z pad 297 provided on the lower plate 292 of the PDP 270 via the Z conductive path 284. The first and third common electrode lines 291a, 291b, and 291c are commonly connected to the electrode lines, and are supplied to the sustain electrode lines. In this case, the first common electrode line 291a and the second and third common electrode lines 291b and 291c are connected by the first and second connectors 297a and 297b. In this case, one of the flexible flat cable and the flexible printed cable is used for the first and second connectors 297a and 297b.

Here, the Z conductive path 284 is connected to the Z pad 297 formed on the Y-Z sustainer board 274 and the lower plate 290 of the PDP 270 as shown in FIG.

At this time, the Y conductive path 282 is connected to the scan driver board 273, and the Z conductive path 284 is connected to the Y-Z sustainer board 274. Here, the Y conductive path 282 is connected to the front side (reference to the PDP 270) or the back side of the scan driver board 273, and the Z conductive path 282 is connected to the front side or the rear side of the YZ sustainer board 274. do.

When driving the PDP module having such a configuration, the current path in the sustain period SPD is as follows. First, when the YZ sustainer board 274 supplies the Y sustain pulse SUSPy to the scan electrode lines of the PDP 270, the first current path is YZ sustainer board 274-> connector 275->. Scan driver board 273-> Y conductive path 282-> scan electrode line-> panel capacitor-> sustain electrode line-> first common electrode line 191a-> first and second connections 297a, 297b )-> Second and third common electrode lines 291b and 291c-> Z conductive path 284-> YZ sustainer board 274. In addition, the second current path through which the YZ sustainer board 274 supplies the Z sustain pulse SUSPz to the sustain electrode lines of the PDP 270 is YZ sustainer board 274-> Z conductive path 284-. > Second and third common electrode lines 191b and 191c-> First and second connection portions 297a and 297b-> First common electrode line 291a-> Sustain electrode line-> Panel capacitor-> Scan electrode Line-> Y conductive path 282-> scan driver board 273-> connector 275-> YZ sustainer board 274.

At this time, each of the conductive paths is any one of a flexible flat cable and a flexible printed cable.

In the PDP module, the second and third common electrode lines 291b and 291c formed on the lower plate 292 are electromagnetic interference (EMI) with the control board 272 or the power board (not shown) by the heat sink 286. This can have a shielding effect. In addition, the assembly process can be simplified by connecting the Y conductive path 282 and the Z conductive path 284 together to one side of the PDP 270. In particular, the inductance on the path can be minimized, thereby improving the energy recovery efficiency.

As described above, the plasma display panel and the module thereof according to the embodiment of the present invention can simplify the configuration of the circuit board by integrating the Y sustain circuit and the Z sustain circuit into one board.

In particular, the plasma display panel and the module thereof according to the embodiment of the present invention form common electrode lines commonly connected to the sustain electrode lines in a non-display area of the upper or lower plate of the plasma display panel, and are connected to the common electrode lines. By forming the Y pad and the Z pad together on one side of the plasma display panel, the workability can be improved by connecting with a short conductive path.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (25)

A first pad connected to the scan electrode lines and a first pad connected to the scan electrode lines, the first electrode connected to the scan electrode lines; A plasma display panel having two pads formed at one side thereof; An integrated driving board for driving the scan electrode lines and the sustain electrode lines; A first conductive path connected between one side of the integrated driving board and the first pad; And a second conductive path connected between one side of the integrated driving board and the second pad. The method of claim 1, And the common electrode lines are formed in a non-display area. The method of claim 2, The common electrode lines, A first common electrode line formed on the other side of the plasma display panel and commonly connected to the sustain electrode lines; A second common electrode line formed on an upper side of the plasma display panel and connected to one side of the first common electrode line; And a third common electrode line formed on a lower side of the plasma display panel and connected to the other side of the first common electrode line. The method of claim 3, wherein And the first common electrode line and the second and third common electrode lines are formed on the same substrate. The method of claim 3, wherein At least one common electrode line of the first to third common electrode lines is formed on another substrate. The method of claim 5, wherein And the first common electrode line and the second and third common electrode lines are formed on different substrates. The method of claim 6, And the second and third common electrode lines are formed on the same substrate as the sustain electrode lines. The method of claim 6, The plasma display panel module further comprises a connection unit for connecting the first common electrode line and the second and third common electrode lines. The method of claim 8, The connection unit is a plasma display panel module, characterized in that any one of a flexible flat cable (flexible flat cable) and a flexible printed cable. The method of claim 1, And the first pad and the second pad are formed on the same substrate. The method of claim 1, And the first pad and the second pad are formed on different substrates. The method of claim 1, The first and second conductive paths are any one of a flexible flat cable and a flexible printed cable. The method of claim 1, The integrated drive board, A scan driver board generating a scan pulse to be supplied to the scan electrode lines; An integrated sustainer board for generating a first sustain pulse to be supplied to the scan electrode lines and a second sustain pulse to be supplied to the sustain electrode lines; And a connector for connecting the scan driver board and the integrated sustainer board. The method of claim 1, A heat sink for dissipating heat from the plasma display panel; A data driver and a board for generating a data pulse to be supplied to the data electrode lines; A control board for supplying a corresponding control signal to each of the scan driver board, the integrated board, and the data driver board; And a power board for supplying power to each of the boards. Scan electrode lines, sustain electrode lines and data electrode lines; Common electrode lines commonly connected to the sustain electrode lines; A first pad connected to the scan electrode lines; A second pad connected to the common electrode lines; The first and second pads are formed on one side of the plasma display panel. The method of claim 15, And the common electrode lines are formed in a non-display area. The method of claim 16, The common electrode lines, A first common electrode line formed on the other side of the plasma display panel and commonly connected to the sustain electrode lines; A second common electrode line formed on an upper side of the plasma display panel and connected to one side of the first common electrode line; And a third common electrode line formed on a lower side of the plasma display panel and connected to the other side of the first common electrode line. The method of claim 17, And the first common electrode line and the second and third common electrode lines are formed on the same substrate. The method of claim 17, At least one common electrode line of the first to third common electrode lines is formed on another substrate. The method of claim 19, And the first common electrode line and the second and third common electrode lines are formed on different substrates. The method of claim 20, And the second and third common electrode lines are formed on the same substrate as the sustain electrode lines. The method of claim 19, The plasma display panel further comprises a connection unit for connecting the first common electrode line and the second and third common electrode lines. The method of claim 22, The connection unit is a plasma display panel, characterized in that any one of a flexible flat cable (flexible flat cable) and a flexible printed cable (flexible printed cable). The method of claim 15, And the first pad and the second pad are formed on the same substrate. The method of claim 15, And the first pad and the second pad are formed on different substrates.