KR100696667B1 - Plasma display device - Google Patents

Abstract

A plasma display device is provided to reduce a composition and a size of a circuit board assembly by biasing a voltage of a sustain electrode to a constant voltage and applying a driving waveform only to a scan electrode. A plasma display panel includes a plurality of first electrodes, a plurality of second electrodes, a plurality of third electrodes crossing the first and second electrodes, and a plurality of discharge cells formed by the first, second, and third electrodes. The plasma display panel is attached to one side of a chassis base(20). A plurality of circuit board assemblies(36) are coupled with the other side of the chassis base in order to generate an electrical signal. The circuit board assembly connected with the first electrodes includes a two-layer circuit board(36a) including a ground layer(36b).

Description

Plasma display device {PLASMA DISPLAY DEVICE}

1 is an exploded perspective view of a plasma display device according to a first embodiment of the present invention.

FIG. 2 is an arrangement diagram of electrodes of the plasma display panel shown in FIG. 1.

3 is a schematic plan view of the chassis base shown in FIG. 1.

4 is a driving waveform diagram of a plasma display device according to a first embodiment of the present invention.

5 is a side cross-sectional view taken along the line VV of FIG. 3.

FIG. 6 is a side sectional view of the second embodiment taken along the line VV of FIG. 3.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display device and a driving method thereof. More particularly, the present invention relates to a plasma display device and a driving method thereof capable of improving the reliability of discharge control and reducing the unit cost of a driving circuit.

The plasma display device is a display device using a plasma display panel that displays text or an image by using plasma generated by gas discharge. In the plasma display panel, a plurality of discharge cells are arranged in a matrix form.

In such a plasma display device, one frame is divided into a plurality of subfields having respective weights to be driven, and each subfield includes a reset period, an address period, and a sustain period.

The reset period is a period of initializing the state of the discharge cells in order to stably perform the next address discharge. The address period is a period for selecting cells to be turned on and cells not to be turned on among the plurality of discharge cells. The sustain period is a period in which sustain discharge is performed for a cell to be turned on to actually display an image.

In order to perform such an operation, a sustain discharge pulse is applied to the scan electrode and the sustain electrode alternately in the sustain period, and the reset waveform and the scan waveform are applied to the scan electrode in the reset period and the address period. Therefore, the scan circuit board assembly for driving the scan electrode and the sustain circuit board assembly for driving the sustain electrode should be present separately.

As such, since the scan circuit board assembly and the sustain circuit board assembly exist separately, a problem arises in the installation space for mounting them on the chassis base, and a problem of increasing the unit cost of the driving circuit board occurs.

In addition, in order to reduce the cost of the driving circuit board assembly, integrating the driving circuit formed in the holding circuit board assembly into the scanning circuit board assembly may increase the length of the wiring (or conductive pattern) formed from the scanning circuit board to the holding electrode. The parasitic component formed in this wiring may cause distortion at the voltage change point of the sustain discharge pulse applied to the sustain electrode.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and the plasma display device of the present invention is to provide a circuit board assembly that can reduce the unit cost of the circuit board assembly and realize a reliable driving operation.

In order to achieve the above object, the plasma display device of the present invention includes a plurality of first electrodes, a plurality of second electrodes, a plurality of third electrodes formed in a direction crossing the first electrode and the second electrode, and the first electrode. And a plasma display panel including a plurality of cells formed by a second electrode and a third electrode, a chassis base to which the plasma display panel is attached to and support the plasma display panel, and fastened to another surface of the chassis base. Circuit board assemblies for generating an electrical signal driving the circuit board, wherein any one of the circuit board assemblies is electrically connected to the first electrode and is in contact with and grounded to the chassis base surface.

In addition, the present invention provides a plasma display device comprising a plurality of first electrodes, a plurality of second electrodes, a plurality of third electrodes formed in a direction crossing the first electrode and the second electrode, and the first electrode, the second electrode, and And a plurality of cells formed by the third electrode, and in the address period, the first scan pulse of the first voltage and the second voltage higher than the first voltage of the first electrode and the third electrode of the cell to be selected as the light emitting cells, respectively. Applying a first address pulse, applying a fifth voltage having a level higher than the ground voltage to the first electrode, and applying a ground voltage to the first electrode in the sustain period, A plasma display panel which sustains and discharges the light emitting cells by alternately applying a third voltage and a fourth voltage lower than the ground voltage, and a chassis plate to which the plasma display panel is attached and supports the plasma display panel. And circuit board assemblies coupled to the other side of the chassis base and generating electrical signals for driving the plasma display panel, wherein any one of the circuit board assemblies is electrically connected to the first electrode, and the chassis Ground is in contact with the base surface.

The circuit board assembly may be formed of a two-layer circuit board, and the circuit board assembly may have a ground layer formed on one surface of the circuit board that is grounded to be in contact with the chassis base surface.

The circuit board assembly has a ground layer of the circuit board welded to the chassis base surface. Also, if the circuit board assembly can be fastened with screw fasteners such that the ground layer of the circuit board is in contact with the chassis base surface, the screw fastener is bolted to the chassis base, and the bolt fastener is fastened to the bolt and connects the ground layer of the circuit board to the chassis base. It may be made of a nut for pressing and fixing on the surface.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention.

In the present invention, the wall charge refers to a charge formed close to each electrode on the cell wall (eg, the dielectric layer). And the wall charge is not actually in contact with the electrode itself, but is described here as “formed”, “accumulated” or “stacked” on the electrode. In addition, the wall voltage refers to the potential difference formed in the wall of the cell by the wall charge.

Hereinafter, a plasma display panel according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings.

First, a schematic structure of a plasma display device according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 to 3.

1 is an exploded perspective view of a plasma display device according to a first embodiment of the present invention.

Referring to FIG. 1, the plasma display apparatus includes a plasma display panel 10, a chassis base 20, a circuit board assembly 30, and a front case 40 and a rear case 40 surrounding them.

The chassis base 20 is coupled to one surface of the plasma display panel 10, that is, the opposite surface on which an image is implemented, to support the plasma display panel 10, and to support the plasma display panel 10 of the chassis base 20. On the other side, circuit board assemblies 30 for driving control of the plasma display panel 10 are mounted.

The front case 40 and the rear case 50 are disposed on the front of the plasma display panel 10 and the rear of the chassis base 20, respectively, and are coupled to the plasma display panel 10 and the chassis base 20. The external appearance of the plasma display device is formed.

The plasma display panel 20 includes a plurality of third electrodes and a plurality of third electrodes formed in a direction crossing the first electrode and the plurality of second electrodes, the first electrode and the second electrode between two substrates disposed to face each other at predetermined intervals. A plurality of discharge cells formed by the first electrode, the second electrode and the third electrode.

FIG. 2 is an electrode array diagram of the plasma display panel shown in FIG. 1.

Referring to FIG. 2, the plasma display panel 10 includes a plurality of first electrodes (hereinafter referred to as “X electrodes”) X1 to Xn extending in pairs with each other in a row direction, and a second one. Electrodes (hereinafter referred to as "Y electrodes") (Y1 to Yn) and a plurality of third electrodes (hereinafter referred to as "A electrodes" as address electrodes) (A1 to Am) extending in the column direction.

In general, the X electrodes X1 to Xn are formed in pairs corresponding to the respective Y electrodes Y1 to Yn. The Y electrodes Y1 to Yn and the X electrodes X1 to Xn are arranged to be orthogonal to the A electrodes A1 to Am. At this time, the discharge space at the intersection of the A electrodes A1 to Am and the X and Y electrodes X1 to Xn and Y1 to Yn forms the cell 12.

The structure of the plasma display panel 33 is an example, and as a matter of course, any panel having any structure can be applied to the present invention as long as the driving waveform described later with reference to FIG. 4 can be applied.

3 is a schematic plan view of the chassis base shown in FIG. 1.

Referring to FIG. 3, circuit board assemblies 30 required for driving the plasma display panel 10 are mounted on the chassis base 20. These circuit board assemblies 30 may include a power supply circuit board assembly 31, an image processing and control circuit board assembly 32, a first circuit board assembly 36, a second circuit board assembly 34, and a third circuit. It is configured to include a board assembly 33.

If the power supply circuit board assembly 31 can be disposed in the center of the chassis base 20 together with the image processing and control board assembly 32, the power supply circuit board assembly 31 supplies power required for driving the plasma display device.

The image processing and control board assembly 32 receives an image signal from the outside to control signals necessary for driving the A electrodes A1 to Am, and necessary for driving the Y electrodes Y1 to Yn and the X electrodes X1 to Xn. The control signal is generated and applied to the third circuit board assembly 33, the second circuit board assembly 34, and the first circuit board assembly 36, respectively.

The third circuit board assembly 33 (hereinafter referred to as an address buffer board) is formed at any one of the upper and lower portions of the chassis base 20. In FIG. 3, a plasma driving apparatus for single driving is described as an example, but in the case of dual driving, the address buffer board 33 is disposed above and below the chassis base 20.

The address buffer board 33 receives an address driving control signal from the image processing and control board 32 and selects a voltage for selecting the discharge cells (hereinafter, referred to as "cells") to be displayed on each of the A electrodes A1 to A. Am) is applied.

The second circuit board assembly 34 (hereinafter referred to as a scanning circuit board) is disposed on the left side of the chassis base 20 and is connected to the scanning buffer board 35 through a connecting member 26 such as a conductive pattern or a cable. do. The scanning buffer board 35 is electrically connected to the Y electrodes Y1 to Yn through a flexible printed circuit (FPC) 22.

The scan circuit board 34 receives a drive signal from the image processing and control board 32 and selects a voltage Y for sequentially selecting the Y electrodes Y1 to Yn in the address period through the scan buffer board 35. It is applied to the electrodes Y1 to Yn.

In FIG. 3, the scan circuit board 34 and the scan buffer board 35 are disposed on the left side of the chassis base 20, but may be disposed on the right side of the chassis base 20. In addition, the scan buffer board 35 may be formed integrally with the scan circuit board 34.

The first circuit board assembly 36 (hereinafter referred to as a holding circuit board) is disposed on the right side of the chassis base 20 and is connected to the X electrodes X1 to Xn through a flexible printed circuit (FPC) 22. It is electrically connected.

4 is a driving waveform diagram of a plasma display device according to a first embodiment of the present invention. In the following description, only the driving waveforms applied to the Y electrode, the X electrode, and the A electrode forming one cell will be described. A cell in which sustain discharge has occurred in the sustain period is defined as a light emitting cell, and a cell in which sustain discharge does not occur in the sustain period is defined as a non-light emitting cell. In the driving waveform of FIG. 4, the voltage applied to the A electrode is supplied from the address buffer board 33, and the voltage applied to the Y electrode is supplied from the scan circuit board 34 and the scan buffer board 35. The applied voltage is supplied from the holding circuit board 36.

As shown in FIG. 4, in the rising period of the reset period, the voltage of the Y electrode is reduced from the third voltage Vs while the A and X electrodes are held at the reference voltage (the ground voltage (0 V) in FIG. 4). Incrementally increases up to 6 voltages (Vset). In FIG. 4, the voltage of the Y electrode is shown to increase in the form of a lamp. Then, while the voltage of the Y electrode is increased, a weak discharge (hereinafter referred to as “weak discharge”) occurs between the Y electrode and the X electrode and between the Y electrode and the A electrode, and a negative wall charge is applied to the Y electrode. And a positive wall charge is formed on the X and A electrodes. When the voltage of the electrode gradually changes as shown in FIG. 4, a weak discharge occurs in the cell, and the wall charge is formed so that the sum of the voltage applied from the outside and the wall voltage of the cell maintains the discharge start voltage state. This principle is disclosed in US Pat. No. 5,745,086 to Weber. In the reset period, since the states of all the cells must be initialized, the sixth voltage Vset is high enough to cause discharge in the cells under all conditions.

In the falling period of the reset period, the voltage of the Y electrode is gradually increased from the third voltage Vs to the seventh voltage Vnf while maintaining the A electrode and the X electrode at the ground voltage (0V) and the fifth voltage (Vb), respectively. To decrease. Then, while the voltage of the Y electrode decreases, a weak discharge occurs between the Y electrode and the X electrode, and between the Y electrode and the A electrode, and the negative wall charges formed on the Y electrode and the positive wall charges formed on the X electrode and the A electrode. Is erased to initialize the cell as a non-light emitting cell. In general, the voltage difference Vnf-Vb between the seventh voltage Vnf and the fifth voltage Vb is set near the discharge start voltage between the Y electrode and the X electrode. As a result, the wall voltage between the Y electrode and the X electrode becomes almost 0 V, whereby a cell that does not have an address discharge in the address period can be prevented from being misdischarged in the sustain period.

In the address period, a scan pulse having the first voltage VscL and an address pulse having the second voltage Va are applied to the Y electrode and the A electrode to select the light emitting cells. The unselected Y electrode is biased to the eighth voltage VscH higher than the first voltage VscL, and a reference voltage is applied to the A electrode of the cell to be selected as the non-light emitting cell. Then, a discharge occurs in a cell formed by the A electrode to which the second voltage Va is applied and the Y electrode to which the first voltage VscL is applied, and thus the positive (+) wall charges to the Y electrode, Wall charges are formed. In order to perform such an operation in the address period, the scan buffer board 35 selects the Y electrode to which the scan pulse of the first voltage VscL is to be applied among the Y electrodes Y1 to Yn. For example, in a single drive, the Y electrodes can be selected in the order arranged in the vertical direction. When one Y electrode is selected, the address buffer board 33 selects a light emitting cell among the cells formed by the corresponding Y electrode. That is, the address buffer board 33 selects a cell to which the address pulse of the second voltage Va is applied among the A electrodes A1 to Am. In this manner, the address period is performed by discharging a cell in a non-light emitting cell state to form a wall charge in the cell and setting it to the light emitting cell state.

Specifically, first, a scanning pulse of the first voltage VscL is applied to the Y electrode of the first row (Y1 in FIG. 2), and at the same time, a second voltage Va is applied to the A electrode located in the cell to be selected as the light emitting cell of the first row. ) Is applied. Then, a discharge occurs between the Y electrode of the first row and the A electrode to which the address pulse is applied, thereby forming positive wall charges on the Y electrode and negative wall charges on the A and X electrodes, respectively. As a result, the wall voltage Vwxy is formed between the Y electrode and the X electrode so that the potential of the Y electrode is high with respect to the potential of the X electrode. Subsequently, while the scan pulse of the first voltage VscL is applied to the Y electrode (Y2 of FIG. 2) in the second row, the address of the second voltage Va is located at the A electrode located in the cell to be selected as the light emitting cell in the second row. A pulse is applied. Then, discharge occurs in a cell formed by the A electrode to which the address pulse is applied and the Y electrode in the second row, thereby forming wall charges in the cell. Similarly, while the scan pulses of the first voltage VscL are sequentially applied to the Y electrodes of the remaining rows, an address pulse of the second voltage Va is applied to the A electrode positioned in the cell to be selected as the light emitting cell, thereby providing a wall to the corresponding cell. An electric charge is formed.

Next, in the sustain period, the sustain discharge pulse is applied to the Y electrode by applying a sustain discharge pulse having the third voltage Vs and the fourth voltage (-Vs) alternately. Specifically, in the cell selected as the light emitting cell in the address period, since the wall voltage Vwxy is formed so that the potential of the Y electrode is higher than that of the X electrode, in the sustain period, the A electrode and the X electrode are maintained at the reference voltage. A sustain discharge pulse having a third voltage Vs is first applied to the Y electrode to cause a sustain discharge between the Y electrode and the X electrode. At this time, the third voltage Vs is set to be lower than the discharge start voltage Vfxy between the Y electrode and the X electrode, and the voltage (Vs + Vwxy) is higher than the discharge start voltage Vfxy. As a result of the sustain discharge, negative wall charges are formed on the Y electrode and positive wall charges are formed on the X electrode and the A electrode, so that the wall voltage Vwyx is formed so that the potential of the X electrode is high with respect to the potential of the Y electrode. do.

Subsequently, a sustain discharge pulse having a fourth voltage (-Vs) is applied to the Y electrode to generate a sustain discharge between the Y electrode and the X electrode. As a result, a positive wall charge is formed at the Y electrode and a negative wall charge is formed at the X electrode and the A electrode, and a sustain discharge can occur when the third voltage Vs is applied to the Y electrode. . Thereafter, the sustain discharge pulses alternately having the third voltage Vs and the fourth voltage −Vs are applied to the Y electrode a number of times corresponding to the weight indicated by the corresponding subfield.

As described above, in the first embodiment of the present invention, the X electrode is biased to the fifth voltage Vb only during the falling period and the address period of the reset period, and in the remaining period, the ground voltage (0V) is applied to the X electrode. The reset operation, the address operation, and the sustain discharge operation may be performed only by the driving waveform applied to the Y electrode.

Therefore, since the switch for applying the ground voltage (0V) and the fifth voltage (Vb) to the X electrode only needs to be formed on the holding circuit board 36, the holding circuit board 36 can be configured more simply and the circuit It is possible to make the size of the substrate smaller.

As a result, as shown in FIG. 3, the area occupied by the holding circuit board 36 on the chassis base 20 is reduced, thereby solving the problem of the installation space in which the driving circuit board 30 is mounted, and the plasma display panel. (10) The cost of the driving circuit board 30 required for driving can be reduced.

The sustain circuit board is in contact with the surface of the chassis base 20 and is grounded to prevent distortion of the waveform due to parasitic inductance components as the ground voltage (0V) and the fifth voltage (Vb) are applied to the X electrode. Do it.

5 is a side cross-sectional view taken along the line VV of FIG. 3.

Referring to FIG. 5, since the holding circuit board 36 applies the ground voltage (0V) and the fifth voltage (Vb) to the X electrode, a large breakdown voltage is not required, and the conductive pattern and the component 36c are SMD on one surface. It is mounted with a surface mount device and the opposite surface is comprised by the two-layer circuit board 36a formed with the ground layer 36b.

The ground layer 36b is welded along the edge in a surface contact state with the surface of the chassis base 20 so as to reinforce the ground of the holding circuit board 36 having a smaller size.

Therefore, a ground reinforcing boss used to reinforce the clamping force and the ground between the chassis base 20 and the holding circuit board 30 may be used, or the four-layer circuit in which the holding circuit board 36 is ground reinforced may be used. It is possible to reinforce the ground of the holding circuit board 36 by using the ground layer 36b welded to the surface of the chassis base 20 without using a substrate, thereby reducing the unit cost.

In addition, as the ground of the sustain circuit board 36 is reinforced by the ground layer 36b, distortion of a waveform applied to the X electrode by parasitic inductance can be prevented to enable reliable discharge control of the plasma display panel. .

Hereinafter, a second embodiment of the present invention will be described with reference to the accompanying drawings, but the same reference numerals are used for the same parts as those of the first embodiment, and a repetitive description thereof will be omitted.

FIG. 6 is a side sectional view of the second embodiment taken along the line VV of FIG. 3.

Referring to FIG. 6, the holding circuit board 36 of the present embodiment is made of a two-layer circuit board 36a on which one side of the holding circuit board 36 is formed, as described above in the first embodiment. The ground layer 36b reinforces the ground of the holding circuit board 36, which is reduced in size, in surface contact with the surface of the chassis base 20, and is fastened to the chassis base 20 by screw fasteners.

Here, the screw fastener corresponds to the fastener 36d of the holding circuit board 36 and is fixed to the chassis base 20, and the bolt 22 is fastened to the bolt 22 and the ground layer of the holding circuit board 36. And a nut 24 for crimping and fixing 36b to the surface of the chassis base 20.

Therefore, the circuit board 36a of the holding circuit board 36 is fixed so that the ground layer 36b is in surface contact with the surface of the chassis base 20 by the screw fastener, and the ground layer 36b is fixed to the chassis. The flatness of the chassis base 20 may be prevented from being deteriorated by the deformation of the chassis base 20 due to thermal stress that may be caused by welding to the base 20.

Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

In the plasma display apparatus according to the present invention, the driving waveform is applied only to the scan electrodes while the voltage of the sustain electrode of the plasma display panel is biased to a constant voltage to drive the control, thereby reducing the cost and size of the circuit board assemblies. By reinforcing the ground of the driving circuit board, which is reduced in size, reliable discharge control is enabled.

Claims (12)

 A plurality of first electrodes and a plurality of second electrodes, a plurality of third electrodes formed in a direction crossing the first electrode and the second electrode, and a plurality of formed by the first electrode, the second electrode, and the third electrode A plasma display panel comprising discharge cells of A chassis base to which the plasma display panel is attached to one surface to support the plasma display panel; Circuit board assemblies coupled to the other surface of the chassis base and generating electrical signals for driving the plasma display panel; And a circuit board assembly electrically connected to the first electrode of the circuit board assemblies comprises a two-layer circuit board including a ground layer, wherein the ground layer is in surface contact with and grounded to the chassis base surface. delete delete The method of claim 1, The circuit board assembly connected to the first electrode, And a ground layer of the circuit board is welded to the chassis base surface. The method of claim 1, The circuit board assembly connected to the first electrode, And a screw fastener such that the ground layer of the circuit board is in contact with the chassis base surface. The method of claim 5, The screw fastener, And a bolt fixed to the chassis base and a nut fastened to the bolt to press-fix the ground layer of the circuit board to the chassis base surface. A plurality of first electrodes and a plurality of second electrodes, a plurality of third electrodes formed in a direction crossing the first electrode and the second electrode, and a plurality of formed by the first electrode, the second electrode, and the third electrode Contains cells of, In an address period, a first scan pulse of a first voltage and a first address pulse of a second voltage higher than the first voltage are respectively applied to the first electrode and the third electrode of a cell to be selected as a light emitting cell, and a first electrode Applies a fifth voltage at a level higher than the ground voltage to In the sustain period, while the ground voltage is applied to the first electrode, a third voltage higher than the ground voltage and a fourth voltage lower than the ground voltage are alternately applied to the second electrode to sustain discharge the light emitting cell. Driving plasma display panel, A chassis base to which the plasma display panel is attached to one surface to support the plasma display panel; Circuit board assemblies coupled to the other surface of the chassis base and generating electrical signals for driving the plasma display panel; And a circuit board assembly electrically connected to the first electrode of the circuit board assemblies comprises a two-layer circuit board including a ground layer, wherein the ground layer is in surface contact with and grounded to the chassis base surface. delete delete The method of claim 7, wherein The circuit board assembly connected to the first electrode, And a ground layer of the circuit board is welded to the chassis base surface. The method of claim 7, wherein The circuit board assembly connected to the first electrode, And a screw fastener such that the ground layer of the circuit board is in contact with the chassis base surface. The method of claim 11, The screw fastener, And a bolt fixed to the chassis base and a nut fastened to the bolt to press-fix the ground layer of the circuit board to the chassis base surface.

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