KR20070006056A - Method of forming dual damascene pattern in semiconductor device - Google Patents

Abstract

A method for forming a dual damascene pattern of a semiconductor device is provided to simplify a fabricating process by eliminating a process for forming a lower ARC(anti-reflective coating) used in a trench etch process. An interlayer dielectric having a via hole(308) is formed on a semiconductor substrate(301). A passivation layer is formed on the resultant structure to fill the via hole, using a photoresist layer with a thickness of 10000 angstroms. An etch-back process is performed until a predetermined thickness of the passivation layer is left on the interlayer dielectric. A baking process is performed to make the etched-back passivation layer have a flat surface. The baked passivation layer and a predetermined thickness of the interlayer dielectric are etched by an etch process using a photoresist layer pattern for forming a trench(312) as a mask so as to form a trench broader than the via hole with respect to the via hole. The passivation layer and the photoresist layer pattern for forming the trench which are left on the interlayer dielectric are eliminated.

Description

Method of forming dual damascene pattern in semiconductor device

1A to 1E are cross-sectional views illustrating processes for forming a dual damascene pattern of a semiconductor device according to the related art.

2A to 2F are cross-sectional views illustrating processes for forming a dual damascene pattern of a semiconductor device according to another conventional technology.

3A to 3H are cross-sectional views illustrating processes for forming a dual damascene pattern of a semiconductor device according to an embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

300: semiconductor substrate 301: copper wiring

302: first etch stop film 303: first interlayer insulating film

304: second etch stop film 305: second interlayer insulating film

306: lower antireflection film 307: first photoresist film pattern

308: Via Hole 309: Shield

310: baking step 311: second photosensitive film pattern

312: trench

The present invention relates to a method for forming a dual damascene pattern of a semiconductor device, and more particularly, to a method for forming a dual damascene pattern of a semiconductor device capable of simplifying a process and reducing a manufacturing cost.

BACKGROUND ART As semiconductor devices become more integrated, research on wiring technology that enables free and easy wiring design and allows setting of wiring resistance and current capacity, etc., has been actively conducted.

In particular, with the recent development of semiconductor technology, in order to increase the speed of the wiring process in the manufacturing process of a semiconductor device of 0.13 μm or less, metal wiring is formed using low resistance copper (Cu) and an insulating film is formed using a low dielectric material. A dual damascene process for forming a trench in which a via hole and a metal wiring is to be formed is introduced in the insulating layer.

There are many ways to form a dual damascene pattern, but generally the most advantageous via first scheme is used in terms of photo mask alignment.

1A through 1D are cross-sectional views illustrating processes for forming a dual damascene pattern of a semiconductor device according to the related art.

As shown in FIG. 1A, a first etch stopper 102, a first interlayer insulating film 103, and a second etch stop film (on a semiconductor substrate 100 having a copper wiring 101) are formed. 104, a second interlayer insulating film 105, and a first bottom anti-reflection coating (BARC) 106 are formed in this order. Then, after applying a photoresist (not shown) on the first lower anti-reflection film 106, the photoresist is patterned to form a first photoresist pattern 107 that exposes a portion where a via hole is to be formed.

Next, as shown in FIG. 1B, the first lower anti-reflection film 106, the second interlayer insulating film 105, and the second etch stop film 104 using the first photoresist pattern 107 as a mask. And the first interlayer insulating layer 103 is etched to form a via hole 108.

Next, as shown in FIG. 1C, after removing the first photoresist pattern 107 and the first lower antireflection film 106 remaining after etching, the second lower antireflection film 109 is formed on the surface of the resultant. To form. Subsequently, a photoresist (not shown) is applied on the second lower antireflection film 109, and then the photoresist is patterned to form a second photoresist pattern 110 that exposes a portion where a trench is to be formed.

Next, as shown in FIG. 1D, the second lower anti-reflective film 109, the second interlayer insulating film 105, and the second etch stop film 104 are formed using the second photoresist pattern 110 as a mask. ) To form a trench 111 wider than the via hole 108 with respect to the via hole 108.

Next, as shown in FIG. 1E, the second lower anti-reflection film 109 and the second photoresist pattern 110 remaining on the second interlayer insulating film 105 are removed. As a result, a dual damascene pattern including the via hole 108 and the trench 111 is formed.

However, in the conventional dual damascene pattern formation method described above, the first etch stop layer 102 on the copper wiring 101 is damaged when the trench 111 is etched due to the relatively high viscosity of the lower anti-reflective layer. There was a problem that is difficult to secure the stability of the process.

Therefore, recently, in order to solve such a problem, dual damascene patterns have been formed.

2A through 2F are cross-sectional views illustrating processes of forming a dual damascene pattern of a semiconductor device according to another conventional technology. As shown in FIG. 2A, a semiconductor substrate having a copper wiring 201 ( The first etch stop film 202, the first interlayer insulating film 203, the second etch stop film 204, the second interlayer insulating film 205, and the first lower anti-reflection film 206 are sequentially formed on the 200. . Then, after applying a photoresist film (not shown) on the first lower anti-reflection film 206, the photoresist is patterned to form a first photoresist pattern 207 exposing portions where via holes are to be formed.

Next, as shown in FIG. 2B, the first lower anti-reflection film 206, the second interlayer insulating film 205, and the second etch stop film 204 using the first photoresist pattern 207 as a mask. And via holes 208 are formed by etching the first interlayer insulating film 203.

Next, as shown in FIG. 2C, after removing the first photoresist layer pattern 207 and the first lower anti-reflective layer 206 remaining after etching, the via hole 208 is completely filled on the substrate. The photosensitive film 209 is applied.

Then, as illustrated in FIG. 2D, an etch-back process is performed such that the photoresist 209 is filled to about 2/3 of the via hole 208, and the second lower reflection on the surface of the resultant product is performed. The prevention film 210 is formed. The etch back process is performed for about 115 to 125 seconds using O ₂ gas. Here, the photoresist 209 remaining inside the via hole 208 prevents the first etch stop layer 202 from being damaged when the trench is subsequently etched. Subsequently, a photoresist (not shown) is applied on the second lower antireflection film 210, and then the photoresist is patterned to form a second photoresist pattern 211 exposing a portion where a trench is to be formed.

Next, as shown in FIG. 2E, the second lower anti-reflective film 210, the second interlayer insulating film 205 and the second etch stop film (using the second photoresist pattern 211 as a mask) are used. The 204 is etched to form a trench 212 wider than the via hole 208 about the via hole 208. In the process of forming the trench 212, the photoresist 209 in the via hole 208 is also removed.

Next, as shown in FIG. 2F, the second lower anti-reflection film 210 and the second photoresist pattern 211 remaining on the second interlayer insulating film 205 are removed.

On the other hand, the formation of the lower anti-reflection film generally involves a thermosetting process, which is difficult to secure process margins such as increased process time because the thermosetting process should be performed at a temperature several tens of degrees Celsius or higher than any other photoresist layer. Not only this, but also the lower cost of the lower anti-reflection film itself had a limit in lowering the manufacturing cost.

Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to provide a method for forming a dual damascene pattern of a semiconductor device, which can prevent manufacturing cost increase due to the use of a lower anti-reflection film and ensure process margins. To provide.

Dual damascene pattern forming method of a semiconductor device according to the present invention for achieving the above object,

Forming an interlayer insulating film having via holes on the semiconductor substrate;

Forming a protective film on the entire structure to fill the via hole;

Performing an etch back process until the passivation layer remains a predetermined thickness on the interlayer insulating layer;

Performing a baking process such that the passivation layer having the etch back process is completed has a flat surface;

Etching a predetermined thickness of the passivation layer and the interlayer insulating layer by etching the photoresist pattern for forming a trench using a mask to form a trench wider than the via hole around the via hole; And

And removing the passivation layer and the trench forming photoresist pattern remaining on the interlayer insulating layer.

Here, the protective film is characterized in that formed to a thickness of 10,000 Å or more.

A photosensitive film is used as the protective film.

In addition, the photosensitive film is characterized by using a photosensitive film sensitive to an I-line or Krf light source.

In addition, the etch back process may be performed until the passivation layer remains on the interlayer insulating layer by a thickness of 1,000 Å or less.

In addition, the etch back process may be performed by a wet etching process or a dry etching process.

In addition, the wet etching process is characterized in that performed in the cleaning equipment.

In addition, the dry etching process is characterized in that performed in the etching equipment or strip equipment.

In addition, the dry etching process is characterized in that performed for 75 to 85 seconds using O ₂ and Ar gas.

In addition, the baking process is characterized in that performed at a temperature of 150 to 250 ℃.

In addition, the baking process is characterized in that proceeds in situ in the photo equipment.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3A to 3H are cross-sectional views illustrating processes for forming a dual damascene pattern of a semiconductor device according to an exemplary embodiment of the present invention.

As shown in FIG. 3A, first, the first etch stop film 302, the first interlayer insulating film 303, the second etch stop film 304, and the like on the semiconductor substrate 300 having the copper wiring 301. The second interlayer insulating film 305 and the first lower antireflection film 306 are sequentially formed. Then, after applying a photoresist film (not shown) on the first lower antireflection film 306, the photoresist pattern is patterned to expose a portion where a via hole is to be formed, that is, a photoresist film for forming a via hole. Form a pattern.

Next, as shown in FIG. 3B, the first lower anti-reflection film 306, the second interlayer insulating film 305, and the second etch stop film 304 are formed using the first photoresist pattern 307 as a mask. And via holes 308 are formed by etching the first interlayer insulating layer 303.

3C, the first photoresist pattern 307 and the first lower anti-reflection film 306 remaining after etching are removed, and then the via holes 308 are buried in the entire structure. The protective film 309 is formed. Here, the protective film 309 is formed to a thickness of 10,000 Å or more. As the protective film 309, a photosensitive film is used. At this time, a photosensitive film sensitive to an I-line (λ = 365 nm) or KrF (λ = 248 nm) light source is used as the photosensitive film.

Next, as shown in FIG. 3D, an etch back process is performed until the passivation layer 309 remains a predetermined thickness on the second interlayer insulating layer 305. The etch back process may be performed until the passivation layer 309 remains on the second interlayer insulating layer 305 by a thickness of 1,000 Å or less. In addition, the etch back process may be performed by wet etching or dry etching. In this case, when the etchback process is performed by a wet etching process, the cleaning process is performed by a cleaning equipment. When the dry etching process is performed by a wet etching process, the etching back process is performed by an etching apparatus or a strip equipment, and O ₂ and Ar gas are used. For about 75 to 85 seconds.

As described above, in the present invention, the etch back process is performed by a target about 30% less than that of the related art, so that the passivation layer 309 remains on the upper portion of the second interlayer insulating layer 305 by a predetermined thickness. The first etch stop layer 302 under the trench is prevented from being damaged in the trench etching process in which the passivation layer 309 existing in the layer 308 is subsequently performed, and on the second interlayer insulating layer 305. The remaining protective film 309 may be performed to function as a lower anti-reflection film. Accordingly, it is possible to prevent an increase in manufacturing cost due to the use of an additional lower anti-reflection film, and to secure a process margin such as simplifying the process and saving process time.

On the other hand, the protective film 309 has been completed the etch back process as described above, as shown in Figure 3d has a rough surface of a rugged shape, when the subsequent trench etching process in this state, the trench to the desired shape It becomes difficult to form. Therefore, in order to make the passivation layer 309 have a flat surface, a baking process 310 is performed as shown in FIG. 3E. Here, the baking process 310 is performed at a temperature of 150 to 250 ℃ and proceeds in-situ in the photo equipment used for the subsequent photosensitive film pattern formation. As the baking process 310 is completed, the surface of the uneven protective film 309 flows to have a flat shape.

Next, as shown in FIG. 3F, a second photosensitive film (not shown) is applied on the protective film 309 on which the baking process 310 is completed, and then the photosensitive film is patterned to expose a portion where a trench is to be formed. The photoresist pattern 311, that is, a photoresist pattern for forming trenches is formed.

3G, the protective layer 309, the second interlayer insulating layer 305, and the second etch stop layer 304 are etched using the second photoresist pattern 311 as a mask. A trench 312 wider than the via hole 308 is formed around the via hole 308. Here, all of the passivation layer 309 existing in the via hole 308 is removed by the trench 312 etching process.

Next, as shown in FIG. 3H, the protective layer 309 and the second photosensitive layer pattern 311 remaining on the second interlayer insulating layer 305 are removed, thereby the via hole 308 and the trench 312. To form a dual damascene pattern.

The present invention is not limited to the above-described embodiments, but can be variously modified and changed by those skilled in the art, which should be regarded as included in the spirit and scope of the present invention as defined in the appended claims. something to do.

As described above, according to the method of forming a dual damascene pattern of a semiconductor device according to the present invention, after forming a protective film using a photoresist film to completely fill the via holes, the target of the etchback process is adjusted to control the protective film on the interlayer insulating film. By allowing the thickness to remain at a predetermined thickness, the protective layer may not only be used as a function for preventing damage to the lower etch stop layer during the trench etching, but may also perform a function of the lower anti-reflection film applied during the trench etching. Therefore, the present invention can prevent the increase in manufacturing cost due to the use of the lower anti-reflection film, and can secure the process margin through the simplification of the process and the saving of the process time.

Claims (11)

Forming an interlayer insulating film having via holes on the semiconductor substrate; Forming a protective film on the entire structure to fill the via hole; Performing an etch back process until the passivation layer remains a predetermined thickness on the interlayer insulating layer; Performing a baking process such that the passivation layer having the etch back process is completed has a flat surface; Etching a predetermined thickness of the passivation layer and the interlayer insulating layer by etching the photoresist pattern for forming a trench using a mask to form a trench wider than the via hole around the via hole; And And removing the passivation layer and the trench forming photoresist pattern remaining on the interlayer insulating layer. The method of claim 1, The protective film is a dual damascene pattern forming method of the semiconductor device, characterized in that formed to a thickness of 10,000 Å or more. The method of claim 1, A method of forming a dual damascene pattern of a semiconductor device, wherein a photosensitive film is used as the protective film. The method of claim 3, wherein A method for forming a dual damascene pattern of a semiconductor device, characterized by using a photosensitive film sensitive to an I-line or Krf light source as the photosensitive film. The method of claim 1, And the etch back process is performed until the passivation layer remains on the interlayer dielectric layer by a thickness of 1,000 Å or less. The method of claim 1, The etch back process is a method of forming a dual damascene of a semiconductor device, characterized in that the wet etching or dry etching process. The method of claim 6, The wet etching process is a dual damascene pattern forming method of the semiconductor device characterized in that performed in the cleaning equipment. The method of claim 6, The dry etching process is a dual damascene pattern forming method of a semiconductor device, characterized in that performed in the etching equipment or strip equipment. The method of claim 6, The dry etching process is a dual damascene pattern forming method of a semiconductor device, characterized in that performed for 75 to 85 seconds using O ₂ and Ar gas. The method of claim 1, The baking process is a dual damascene pattern forming method of a semiconductor device, characterized in that performed at a temperature of 150 to 250 ℃. The method of claim 1, The baking process is a dual damascene pattern forming method of the semiconductor device, characterized in that proceeding in situ in the photo equipment.

Images