KR20070006050A - Method of forming fine landing pad of a semiconductor device - Google Patents

Method of forming fine landing pad of a semiconductor device Download PDF

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Publication number
KR20070006050A
KR20070006050A KR1020050061037A KR20050061037A KR20070006050A KR 20070006050 A KR20070006050 A KR 20070006050A KR 1020050061037 A KR1020050061037 A KR 1020050061037A KR 20050061037 A KR20050061037 A KR 20050061037A KR 20070006050 A KR20070006050 A KR 20070006050A
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South Korea
Prior art keywords
positive photoresist
photoresist pattern
landing pad
semiconductor device
pattern
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KR1020050061037A
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Korean (ko)
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최재성
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매그나칩 반도체 유한회사
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Priority to KR1020050061037A priority Critical patent/KR20070006050A/en
Publication of KR20070006050A publication Critical patent/KR20070006050A/en

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004—Photosensitive materials
    • G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
    • G03F7/095—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers having more than one photosensitive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers

Abstract

A method for fabricating a fine landing pad of a semiconductor device is provided to improve resolution of the fine landing pad by using conventional manufacturing equipment. A positive photoresist layer pattern(12a) where a contact hole is formed on a lower structure(10). A negative photoresist layer(14) is formed on the positive photoresist layer pattern to gap-fill the positive photoresist layer pattern on which the contact hole is formed. The negative photoresist layer is planarized by an etchback or CMP(Chemical Mechanical Polishing) process to expose an upper portion of the positive photoresist pattern. An exposing process and a developing process are performed on the whole surface of the structure to remove the positive photoresist layer pattern.

Description

반도체소자의 미세 랜딩 패드 형성 방법{METHOD OF FORMING FINE LANDING PAD OF A SEMICONDUCTOR DEVICE}METHOD OF FORMING FINE LANDING PAD OF A SEMICONDUCTOR DEVICE}

도 1a 내지 도 1e는 본 발명에 의한 반도체소자의 미세 랜딩 패드 형성 방법을 설명하기 위한 공정 단면도1A to 1E are cross-sectional views illustrating a method of forming a fine landing pad of a semiconductor device according to the present invention.

<도면의 주요 부호에 대한 설명><Description of Major Symbols in Drawing>

10 : 하부구조물 12 : 포지티브 감광막10: substructure 12: positive photosensitive film

12a, 12b : 포지티브 감광막 패턴 13 : 콘택홀12a, 12b: Positive photoresist pattern 13: Contact hole

14 : 네가티브 감광막14: negative photosensitive film

14a : 네가티브 패턴 또는 랜딩 패드 패턴14a: negative pattern or landing pad pattern

본 발명은 반도체소자의 미세 랜딩 패드(Landing Pad) 형성 방법에 관한 것으로, 특히 기존의 장비를 이용하여 해상도(Resolution)를 향상시킬 수 있는 반도체소자의 미세 랜딩 패드(Landing Pad) 형성 방법에 관한 것이다.The present invention relates to a method of forming a fine landing pad of a semiconductor device, and more particularly, to a method of forming a fine landing pad of a semiconductor device capable of improving resolution using existing equipment. .

점차적으로 반도체 소자가 고 집적화됨에 따라 포토 리소그래피(Photo Lithography)에서 형성해야 하는 패턴(Pattern)의 크기(Size)가 작아지게 되고, 특히나 라인 패턴(Line Pattern)에 비해 랜딩패드 패턴(Pattern)은 낮은 이미지 콘트라스트(Image Contrast)로 인하여 그 해상도가 한계점에 다다른 상태이다.Gradually, as semiconductor devices become more integrated, the size of patterns to be formed in photolithography becomes smaller, and in particular, landing pad patterns are lower than line patterns. Due to the image contrast, the resolution has reached its limit.

이러한 랜딩패드 패턴의 해상도 한계를 극복하기 위하여 기존에는 OPC(Optical Proximity Correction) 등을 사용하고 있지만 가장 최적화된 OPC를 적용하는 경우에도 일반적인 라인 패턴(Line Pattern)에 비해 그 해상도 한계가 문제되고 있는 실정이다.In order to overcome the resolution limitation of the landing pad pattern, OPC (Optical Proximity Correction) has been used. However, even when the most optimized OPC is applied, the resolution limitation is more problematic than the general line pattern. to be.

따라서, 본 발명은 상기 문제점을 해결하기 위하여 이루어진 것으로, 본 발명의 목적은 기존의 장비를 그대로 이용하여 해상력(Resolution)이 향상된 미세 랜딩 패드(Landing Pad)를 형성할 수 있고, 소자의 신뢰성 및 생산 수율을 향상시킬 수 있는 반도체소자의 미세 랜딩 패드(Landing Pad) 형성 방법을 제공하는데 있다.Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to use a conventional equipment as it is to form a fine landing pad (Resolution) is improved, the reliability and production of the device Disclosed is a method of forming a fine landing pad of a semiconductor device capable of improving yield.

상기 목적을 달성하기 위한 본 발명에 의한 반도체소자의 미세 랜딩 패드 형성 방법은, 하부구조물 상에 콘택홀이 형성된 포지티브 감광막 패턴을 형성하는 단계; 상기 콘택홀이 형성된 포지티브 감광막 패턴이 완전히 매립되도록 상기 포지티브 감광막 패턴 상에 네가티브 감광막을 형성하는 단계; 상기 포지티브 감광막 패 턴의 상부가 노출되도록 상기 네가티브 감광막을 에치백(Etchback) 또는 화학적기계적연마(CMP) 공정으로 평탄화하는 단계; 및 상기 구조물 상에 전면노광 및 현상 공정을 실시하여 상기 포지티브 감광막 패턴을 제거하는 단계;를 포함하는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming a fine landing pad of a semiconductor device, the method including: forming a positive photoresist pattern on which a contact hole is formed; Forming a negative photoresist film on the positive photoresist pattern so as to completely fill the positive photoresist pattern having the contact hole; Planarizing the negative photoresist by an etchback or chemical mechanical polishing (CMP) process to expose the upper portion of the positive photoresist pattern; And removing the positive photoresist pattern by performing a front exposure and development process on the structure.

여기서, 상기 포지티브 감광막 패턴은 대략 1000Å 내지 20000Å의 두께로 형성하는 것을 특징으로 한다.The positive photoresist pattern may be formed to a thickness of about 1000 kPa to about 20000 kPa.

그리고, 상기 네가티브 감광막 패턴은 대략 1000Å 내지 20000Å의 두께로 형성하는 것을 특징으로 한다.And, the negative photosensitive film pattern is characterized in that it is formed to a thickness of approximately 1000kPa to 20000kPa.

또한, 상기 평탄화 공정시 상기 포지티브 감광막의 상부 또는 상부로부터 일정 깊이까지 제거하는 것을 특징으로 한다.In addition, during the planarization process, it is characterized in that the removal to the predetermined depth from the top or the top of the positive photosensitive film.

이하, 첨부된 도면을 참조하여 본 발명의 실시예에 대해 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

실시예Example

도 1a 내지 도 1e는 본 발명에 의한 반도체소자의 미세 랜딩 패드 형성 방법을 설명하기 위한 공정 단면도이다.1A to 1E are cross-sectional views illustrating a method of forming a fine landing pad of a semiconductor device according to the present invention.

본 발명에 의한 반도체소자의 미세 콘택홀 형성 방법은, 먼저 도 1a와 같이, 하부구조물(10) 상에 일정 두께의 포지티브 감광막(12)을 형성한다. 이때, 상기 포지티브 감광막(12)의 두께는 대략 1000Å 내지 20000Å의 범위로 형성한다.In the method for forming a micro contact hole of a semiconductor device according to the present invention, first, as shown in FIG. 1A, a positive photoresist film 12 having a predetermined thickness is formed on a lower structure 10. At this time, the thickness of the positive photosensitive film 12 is formed in the range of approximately 1000 kPa to 20000 kPa.

그 다음, 도 1b와 같이, 상기 포지티브 감광막(12)을 마스크 식각하여 랜딩 패드(Landing Pad)가 형성될 패턴의 위치에 콘택홀(13)을 형성한다. 이렇게 형성된 콘택홀(13)은 랜딩 패드 패턴(Landing Pad Pattern)에 비해 패턴의 충실도(Fidelity)가 우수한 편이다.Next, as shown in FIG. 1B, the positive photoresist layer 12 is mask-etched to form a contact hole 13 at a position of a pattern in which a landing pad is to be formed. The contact hole 13 formed as described above has a higher fidelity of the pattern than the landing pad pattern.

그 다음, 도 1c와 같이, 상기 콘택홀(13)이 형성된 포지티브 감광막 패턴(12a)이 완전히 매립되도록 상기 포지티브 감광막 패턴(12a) 상에 일정 두께의 네가티브 감광막(14)을 형성한다. 이때, 상기 네가티브 감광막(14)의 두께는 대략 1000Å 내지 20000Å의 범위를 갖는다.Next, as shown in FIG. 1C, a negative photoresist film 14 having a predetermined thickness is formed on the positive photoresist pattern 12a so that the positive photoresist pattern 12a on which the contact hole 13 is formed is completely embedded. At this time, the thickness of the negative photosensitive film 14 has a range of approximately 1000 kPa to 20000 kPa.

그 다음, 도 1d와 같이, 상기 포지티브 감광막 패턴(12a)의 상부가 노출되도록 상기 네가티브 감광막(14)을 에치백(Etchback) 또는 화학적기계적연마(CMP) 공정으로 평탄화한다. Next, as illustrated in FIG. 1D, the negative photoresist 14 is planarized by an etchback or chemical mechanical polishing (CMP) process so that the upper portion of the positive photoresist pattern 12a is exposed.

여기서, 상기 에치백(Etchback) 또는 화학적기계적연마(CMP) 공정시 상기 포지티브 감광막 패턴(12a)을 상부에서 소정의 깊이까지 평탄화시킬 수도 있다.In this case, the positive photoresist pattern 12a may be planarized from the top to a predetermined depth in the etching back or chemical mechanical polishing (CMP) process.

그 다음, 평탄화된 상기 구조물 상에 레티클(Reticle)없이 전면 노광을 실시한다. 이에 의해, 상기 평탄화된 포지티브 감광막 패턴(12b)은 이후에 진행될 현상(Develop) 공정에서 현상액(Developer)에 현상될 준비가 된 상태가 되고, 반면에 상기 네가티브 감광막(14)은 상기 현상액(Developer)에 의해 현상되지 않는 상태가 된다.Next, a full surface exposure is performed on the planarized structure without a reticle. As a result, the planarized positive photoresist pattern 12b is ready to be developed in a developer in a later development process, while the negative photoresist 14 is formed in the developer. It will be in the state which is not developed by.

그 다음, 현상(Develop) 공정을 실시하게 되면, 도 1e와 같이 상기 노광 공정에서 빛을 받은 상기 포지티브 감광막 패턴(12b)은 현상액에 의해 모두 현상되어 없어지고 빛을 받지 않은 상기 네가티브 감광막(14)은 현상되지 않고 그대로 남아 있게 되어 결국 랜딩 패드 패턴(14a)이 형성된다.Subsequently, when the development process is performed, the positive photoresist pattern 12b that is lighted in the exposure process as shown in FIG. Is not developed and remains as it is, and eventually the landing pad pattern 14a is formed.

이상의 본 발명은 상기에 기술된 실시예들에 의해 한정되지 않고, 당업자들에 의해 다양한 변형 및 변경을 가져올 수 있으며, 이는 첨부된 특허청구범위에서 정의되는 본 발명의 취지와 범위에 포함되는 것으로 보아야 할 것이다. The present invention is not limited to the above-described embodiments, but can be variously modified and changed by those skilled in the art, which should be regarded as included in the spirit and scope of the present invention as defined in the appended claims. something to do.

이상에서 설명한 바와 같이, 본 발명에 의한 반도체소자의 미세 랜딩 패드(Landing Pad) 형성 방법에 의하면, 기존의 장비를 이용하여 고 해상도의 미세 랜딩 패드를 구현할 수 있기 때문에 설비 투자 비용을 절감할 수 있고, 안정적인 공정 제어로 인한 소자 신뢰성 및 생산 수율을 향상시킬 수 있는 효과가 있다.As described above, according to the method of forming a fine landing pad of a semiconductor device according to the present invention, it is possible to implement a high-resolution fine landing pad using existing equipment, thereby reducing equipment investment cost. As a result, it is possible to improve device reliability and production yield due to stable process control.

Claims (4)

하부구조물 상에 콘택홀이 형성된 포지티브 감광막 패턴을 형성하는 단계;Forming a positive photoresist pattern having contact holes formed on the lower structure; 상기 콘택홀이 형성된 포지티브 감광막 패턴이 완전히 매립되도록 상기 포지티브 감광막 패턴 상에 네가티브 감광막을 형성하는 단계;Forming a negative photoresist film on the positive photoresist pattern so as to completely fill the positive photoresist pattern having the contact hole; 상기 포지티브 감광막 패턴의 상부가 노출되도록 상기 네가티브 감광막을 에치백(Etchback) 또는 화학적기계적연마(CMP) 공정으로 평탄화하는 단계; 및Planarizing the negative photoresist by an etchback or chemical mechanical polishing (CMP) process to expose the upper portion of the positive photoresist pattern; And 상기 구조물 상에 전면노광 및 현상 공정을 실시하여 상기 포지티브 감광막 패턴을 제거하는 단계;를 포함하는 것을 특징으로 하는 반도체소자의 미세 랜딩 패드 형성 방법.And removing the positive photoresist pattern by performing a front exposure and development process on the structure. 제 1 항에 있어서,The method of claim 1, 상기 포지티브 감광막 패턴은 대략 1000Å 내지 20000Å의 두께로 형성하는 것을 특징으로 하는 반도체소자의 미세 랜딩 패드 형성 방법.And the positive photoresist pattern is formed to a thickness of approximately 1000 kPa to 20000 kPa. 제 1 항에 있어서,The method of claim 1, 상기 네가티브 감광막 패턴은 대략 1000Å 내지 20000Å의 두께로 형성하는 것을 특징으로 하는 반도체소자의 미세 랜딩 패드 형성 방법.And the negative photoresist pattern is formed to a thickness of approximately 1000 kPa to 20000 kPa. 제 1 항에 있어서,The method of claim 1, 상기 평탄화 공정시 상기 포지티브 감광막패턴의 상부 또는 상부로부터 일정 깊이까지 제거하는 것을 특징으로 하는 반도체소자의 미세 랜딩 패드 형성 방법.The method of forming a fine landing pad of a semiconductor device, characterized in that to remove a predetermined depth from the top or top of the positive photoresist pattern during the planarization process.
KR1020050061037A 2005-07-07 2005-07-07 Method of forming fine landing pad of a semiconductor device KR20070006050A (en)

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