KR20100026732A - Method for fabricating the semiconductor device - Google Patents

Method for fabricating the semiconductor device Download PDF

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Publication number
KR20100026732A
KR20100026732A KR1020080085853A KR20080085853A KR20100026732A KR 20100026732 A KR20100026732 A KR 20100026732A KR 1020080085853 A KR1020080085853 A KR 1020080085853A KR 20080085853 A KR20080085853 A KR 20080085853A KR 20100026732 A KR20100026732 A KR 20100026732A
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KR
South Korea
Prior art keywords
layer
pattern
photoresist
photoresist pattern
semiconductor device
Prior art date
Application number
KR1020080085853A
Other languages
Korean (ko)
Inventor
이홍구
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020080085853A priority Critical patent/KR20100026732A/en
Publication of KR20100026732A publication Critical patent/KR20100026732A/en

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70466—Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

The present invention relates to a method of manufacturing a semiconductor device. When the DPT process is applied, a first photoresist pattern is formed, and an SOC layer is deposited on the surface of the first photoresist to control the space CD between the first photoresist patterns. Next, the second photoresist pattern is buried in the space between the first photoresist patterns, and the exposed SOC layer is etched to leave the first photoresist pattern and the second photoresist pattern, and a fine pattern is formed using the ArF process. Even if it is applied to form a fine pattern that overcomes the limitations of the resolution, by depositing the SOC layer, a technique for self-alignment during the double patterning process is disclosed.

Description

Method for manufacturing a semiconductor device {METHOD FOR FABRICATING THE SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a pattern formation method using a double patterning technology (DPT) process.

In general, a lithography process is a process of forming a desired photoresist pattern by applying a photoresist film on a wafer, followed by exposure and development, and is performed before an etching process or an ion implantation process that requires a hard mask.

As semiconductor devices are highly integrated, the size and pitch of patterns constituting a circuit are gradually decreasing.

In order to overcome the technical limitations of the semiconductor device manufacturing apparatus, the photolithography technology during the processing process refines the design of the manufacturing method of the semiconductor device, thereby appropriately adjusting the amount of light emitted through the manufacturing method of the semiconductor device, and a new photosensitive agent. And the development of a scanner using a high numerical aperture lens, a method of manufacturing a modified semiconductor device, and the like.

However, due to limitations in exposure and resolution ability that proceed with current light sources, for example, KrF, ArF, etc., it is difficult to form a width and an interval of a desired pattern.

Accordingly, various methods for forming a photoresist pattern having a size and a spacing of fine patterns have been studied. Examples of such methods include EUV and a nano-imprint method.

However, since EUV has a very small wavelength of 13 nm, there is a problem that low power and light source are absorbed by all materials, and thus a new reflectometer system to replace the transmission method is required. Because of the difficulties, many technologies must be supplemented and developed in order to use them in actual device development.

In addition, the nanoimprint method has implications for shortening the lifespan of a mask system caused by the imprint method, the problem of making a large number of masks redundant, and the development of a resist material for use. It is a state.

Meanwhile, another method for forming a photoresist pattern having a size and a gap of a fine pattern is a double patterning technology (DPT) method in which a pattern is formed by performing two photographic processes.

The DPT method uses a DE2T (Double Expose Etch Technology) method that exposes and etches a pattern having twice the period of the pattern period, and then exposes and etches a second pattern having the same double period between them, and a spacer. There is a SPT (Spacer Patterning Technology) method of forming a pattern.

The DE2T method and the SPT method may be formed by a process of negative tones and positive tones, respectively.

The negative tone DE2T method removes the pattern formed in the first mask process from the second mask process to form a desired pattern. The positive tone DE2T method combines the pattern formed in the first mask process and the second mask process to form a desired pattern. How to form.

The SPT method is a self align method that can prevent the disadvantage of mis align because the mask process is performed only once for patterning the cell region.

However, the current DPT method is considered to form a 40 nm line width due to the resolution limit of the 193 nm wavelength and the line edge roughness (hereinafter referred to as LER) of the ArF photoresist films.

In addition, the DPT method has many limitations such as poor pattern fidelity, insufficient process window margin, LER, lack of overlay margin due to dual pattern formation, complexity and difficulty of process application. There is a problem that exists.

The present invention is to improve the DPT process to form a fine pattern that can overcome the limitations of resolution even if the ArF process is applied, and to be self-aligned during the double patterning process.

Method for manufacturing a semiconductor device according to the present invention

Forming a first photoresist pattern on the etched layer;

Forming a spin on carbon (SOC) layer on a surface of the first photoresist pattern and the etched layer layer such that a space is formed between the first photoresist pattern;

Forming a second photoresist pattern filling the space;

Etching the entire SOC layer;

And etching the etched layer using the first photoresist pattern and the second photoresist pattern as masks.

Here, the carbon content of the SOC layer is characterized in that 82 to 90%.

In addition, the baking process is performed after the SOC layer is formed, and the baking process is preferably performed at 70 to 150 ° C.

The CD of the first photoresist pattern and the CD of the space are the same.

The second photoresist pattern includes norbornene or acrylate resin, which is a photoresist for ArF, and the second photoresist pattern is a polyvinyl phenol (PVP, polyvinyl phenol) photoresist for KrF. It may also contain a system resin.

In addition, the etching of the SOC layer may be performed using a CF 4 gas.

The method of manufacturing a semiconductor device according to the present invention can form a fine pattern in the form of a line / space to overcome the limit resolution of the exposure equipment, self-align (Self Align) is possible to secure the overlap and alignment margins There is an effect of improving the characteristics of the device.

Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

Referring to FIG. 1A, a hard mask layer 110 is formed on the etched layer 100. Next, a first photosensitive film (not shown) is formed on the hard mask layer 110. Here, the hard mask layer 110 is formed of an amorphous carbon layer (Amorphous-Carbon).

Next, a baking process is performed with respect to a 1st photosensitive film (not shown). At this time, the baking step is preferably baked at 70 ~ 150 ℃ possible acid diffusion (acid diffusion).

Next, an exposure and development process is performed on the first photoresist film (not shown) to form the first photoresist pattern 120 having a line / space shape. Here, the exposure process is performed using an ArF light source.

Referring to FIG. 1B, a spin on carbon (SOC) layer 130 is formed on the first photoresist pattern 120 and the hard mask layer 110. Here, after the SOC layer 130 is deposited, the CD of the second photoresist pattern subsequently formed by the space CD D2 between the first photoresist patterns 120 is determined.

Therefore, since the CD of the second photoresist pattern needs to be formed in the same manner as the CD (D1) of the first photoresist pattern 120, the space CD (D2) is formed by adjusting the deposition thickness of the SOC layer 130. 120, and the same as the CD D1.

At this time, the SOC layer 130 contains 82 to 90% of carbon.

The SOC layer 130 formed of the mixture as described above may have a large etching selectivity for the CF4 gas and excellent coating properties to have a predetermined thickness along the pattern surface.

Next, a bake process is performed on the SOC layer 130. Here, it is preferable to advance a baking process at 70-150 degreeC.

Referring to FIG. 1C, a second photoresist layer 140 is formed on the SOC layer 130.

Here, the second photoresist layer 140 may include norbornene or acrylate resin, which is an ArF photoresist film, and may include polyvinyl phenol (PVP) resin, which is a photoresist film for KrF. have.

In addition, in place of the second photoresist layer 140, a RELACS (Resoltion Enhancement Lithograhy Assist Chemical Supplies) or SAFIER (Shrink Assist Film for Enhanced Resolution) material may be formed.

Here, the use of RELACS or SAFIER materials allows for the formation of finer patterns.

Next, a bake process is performed on the second photosensitive film 140. At this time, the baking step is preferably baked at 70 ~ 150 ℃ possible acid diffusion (acid diffusion).

Referring to FIG. 1D, the second photoresist layer 140 may be exposed and developed to form a second photoresist layer pattern 140a embedded between the first photoresist layer patterns 120.

In this case, the second photoresist layer 140 on the first photoresist pattern 120 is removed to expose the SOC layer 130 on the first photoresist pattern 120.

Referring to FIG. 1E, the entire surface of the exposed SOC layer 130 is etched to expose the hard mask layer 110 between the first photoresist pattern 120 and the second photoresist pattern 140a. Here, the etching of the SOC layer 130 is preferably performed using CF4 gas.

In this case, the SOC layer 130 formed on the upper and sidewalls of the first photoresist layer pattern 120 is etched, and the second photoresist layer pattern 140a serves as a barrier in the SOC layer 130 formed under the second photoresist layer pattern 140a. It is not etched.

Referring to FIG. 1F, the hard mask layer 110 is etched using the first photoresist pattern 120 and the second photoresist pattern 140a as an etching mask to form a hard mask pattern 110a.

Next, the SOC layer 130 remaining under the first photoresist pattern 120, the second photoresist pattern 140a, and the second photoresist pattern 140a is removed.

Next, the etching target layer 100 is etched using the hard mask pattern 110a as an etching mask to form a fine pattern.

An active region, a gate, a landing plug contact, a bitline, and the like of a semiconductor device may be formed using the above-described pattern forming method.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

<Explanation of Signs of Major Parts of Drawings>

100: etching layer 110: hard mask layer

120: first photosensitive film pattern 130: SOC layer

140: second photosensitive film 150: exposure mask

140a: second photosensitive film pattern

Claims (8)

Forming a first photoresist pattern on the etched layer; Forming a spin on carbon (SOC) layer on a surface of the first photoresist pattern and the etched layer such that a space is formed between the first photoresist pattern; Forming a second photoresist pattern filling the space; Etching the SOC layer entirely; And Etching the etched layer using the first photoresist pattern and the second photoresist pattern as a mask Method of manufacturing a semiconductor device comprising a. The method of claim 1, The carbon content of the SOC layer is 82 to 90%, the manufacturing method of a semiconductor device. The method of claim 1, A method of manufacturing a semiconductor device, characterized in that to perform a bake process after forming the SOC layer. The method of claim 3, wherein The baking process is a method of manufacturing a semiconductor device, characterized in that performed at 70 ~ 150 ℃. The method of claim 1, The CD of the first photosensitive film pattern and the CD of the space is the same. The method of claim 1, The second photoresist pattern includes a norbornene or acrylate resin that is an ArF photoresist. The method of claim 1, The second photoresist pattern is a method of manufacturing a semiconductor device, characterized in that the polyvinyl phenol (PVP, polyvinyl phenol) resin that is a photosensitive film for KrF. The method of claim 1, Etching the SOC layer is performed using a CF4 gas.
KR1020080085853A 2008-09-01 2008-09-01 Method for fabricating the semiconductor device KR20100026732A (en)

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KR1020080085853A KR20100026732A (en) 2008-09-01 2008-09-01 Method for fabricating the semiconductor device

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KR1020080085853A KR20100026732A (en) 2008-09-01 2008-09-01 Method for fabricating the semiconductor device

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170059720A (en) * 2015-11-23 2017-05-31 주식회사 원익아이피에스 Method of fabricating semiconductor device and apparatus of fabricating the same
CN114446769A (en) * 2020-11-06 2022-05-06 长鑫存储技术有限公司 Method for manufacturing semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170059720A (en) * 2015-11-23 2017-05-31 주식회사 원익아이피에스 Method of fabricating semiconductor device and apparatus of fabricating the same
CN114446769A (en) * 2020-11-06 2022-05-06 长鑫存储技术有限公司 Method for manufacturing semiconductor device
WO2022095419A1 (en) * 2020-11-06 2022-05-12 长鑫存储技术有限公司 Semiconductor device preparation method
CN114446769B (en) * 2020-11-06 2024-09-13 长鑫存储技术有限公司 Method for manufacturing semiconductor device

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