KR20070002787A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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KR20070002787A
KR20070002787A KR1020050058457A KR20050058457A KR20070002787A KR 20070002787 A KR20070002787 A KR 20070002787A KR 1020050058457 A KR1020050058457 A KR 1020050058457A KR 20050058457 A KR20050058457 A KR 20050058457A KR 20070002787 A KR20070002787 A KR 20070002787A
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South Korea
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silicon
channel
degrees
substrate
oxide film
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KR1020050058457A
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Korean (ko)
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황경진
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매그나칩 반도체 유한회사
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Priority to KR1020050058457A priority Critical patent/KR20070002787A/en
Publication of KR20070002787A publication Critical patent/KR20070002787A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
    • H01L29/7854—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection with rounded corners

Abstract

A method for manufacturing a semiconductor device is provided to restrain the convergence of an electric field at a channel edge portion by forming roundly the channel edge portion using a selective silicon epitaxial growth. A nitride layer(102) and a silicon oxide layer are formed on a silicon substrate(101). An opening portion for exposing partially the substrate to the outside is formed on the resultant structure. A channel silicon(104) is grown on the exposed substrate. An ion implantation is performed on the channel silicon. A gate insulating layer is formed along the channel silicon. A gate electrode(106) is formed on the resultant structure. The channel silicon is formed by using a selective silicon epitaxial growth, so that an edge portion of the channel silicon is roundly formed.

Description

반도체 소자의 제조 방법{METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}Method for manufacturing a semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

도1은 종래의 핀 전계 효과 트랜지스터의 사시도.1 is a perspective view of a conventional fin field effect transistor.

도2 내지 도6은 도1의 핀 전계 효과 트랜지스터의 제조 공정에 따른 도면으로서, 선분 A-B를 따라 절취한 단면도.2 to 6 are cross-sectional views taken along line A-B of the fin field effect transistor of FIG.

도7 내지 도11은 본 발명에 따른 핀 전계 효과 트랜지스터의 제조 공정에 따른 단면도이다.7 to 11 are cross-sectional views of the process of manufacturing the fin field effect transistor according to the present invention.

본 발명은 반도체 소자의 제조 방법에 관한 것으로, 보다 구체적으로는 나노급(nano)의 핀 전계효과 트랜지스터(FinFET) 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a nano fin field effect transistor (FinFET).

반도체 소자, 특히 전계 효과 트랜지스터에서 고성능, 고집적화가 진행됨에 따라 여러 문제점들이 발생하고 있다. 그 중에서도, 전계효과 트랜지스터의 채널 길이가 점점 짧아짐에 따라, 게이트가 적정 전압에 도달하기 전에 소스측으로부터 드레인측으로 전류가 흘러 발생되는 쇼트 채널 효과(short channel effect)는 전계 효과 트랜지스터의 성능을 저하시키는 대표적인 문제점이라 할 수 있다.As semiconductor devices, particularly field effect transistors, are progressing in high performance and high integration, various problems are occurring. In particular, as the channel length of the field effect transistor becomes shorter and shorter, the short channel effect generated by flowing current from the source side to the drain side before the gate reaches a proper voltage causes a decrease in the performance of the field effect transistor. It is a representative problem.

이러한 문제점을 해결하기 위해, 새로운 타입의 반도체 소자가 계속 개발되고 있으며, 핀 전계효과 트랜지스터(FinFET)를 예로 들 수 있다. 핀 전계효과 트랜지스터는 채널의 양측에 게이트 전극이 존재하기 때문에, 게이트 전극의 채널 제어가 양측에서 일어나게 되어 쇼트 채널 효과를 억제할 수 있다.In order to solve this problem, new types of semiconductor devices continue to be developed, for example, a fin field effect transistor (FinFET). Since the fin field effect transistors have gate electrodes on both sides of the channel, channel control of the gate electrodes occurs on both sides, so that the short channel effect can be suppressed.

그러나, 핀 전계효과 트랜지스터의 경우, 일부 채널 부분에 전기장(electric field)이 집중되는 현상으로 인해, 소자의 특성 및 신뢰성에 문제점이 있었다. 도1 내지 도6을 참조하여, 이 문제점에 대해 보다 구체적으로 설명한다.However, in the case of the fin field effect transistor, due to a phenomenon in which electric field is concentrated in some channel portions, there is a problem in the characteristics and reliability of the device. 1 to 6, this problem will be described in more detail.

도1은 종래의 핀 전계효과 트랜지스터의 구조를 나타내는 사시도이고, 도2 내지 도6은, 도1의 선분 A-B를 따라 절단한 공정 단면도이다.1 is a perspective view showing the structure of a conventional fin field effect transistor, and FIGS. 2 to 6 are cross-sectional views taken along the line segment A-B of FIG.

도2에 도시한 바와 같이, 실리콘 기판(1) 상에 절연막(2)을 형성하고, 절연막(2) 상에 실리콘막(3)을 형성한다. 다음으로, 도3에 도시한 바와 같은 패턴으로 실리콘막(3)을 식각한다. 여기서, 식각후 남은 실리콘막(3)이 캐리어의 이동이 있는 채널용 실리콘(3')으로 된다. 다음으로, 도4에 도시한 바와 같이, 채널용 실리콘(3')을 산화시킴으로써 일정 두께의 실리콘 산화막(4)을 게이트 절연막으로서 형성한다. 이때, 형성된 게이트 절연막(4)은 식각에 의해 형성된 실리콘막(3)에 대응하여 형성되기 때문에, 식각된 에지 부분이 식각후 남은 채널용 실리콘(3')과 동일하게 각을 이루게 된다. 다음으로, 도5에 도시한 바와 같이, 게이트 전극 물질(5)을 증착한 후, 도6에 도시한 바와 같이, 식각을 이용하여 일정 모양의 게이트 전극 (5')을 형성한다. 그 다음, 소스(6)/드레인(7) 영역을 정의하고 도핑하여 정션을 형성한다.As shown in FIG. 2, the insulating film 2 is formed on the silicon substrate 1, and the silicon film 3 is formed on the insulating film 2. As shown in FIG. Next, the silicon film 3 is etched in a pattern as shown in FIG. Here, the silicon film 3 remaining after the etching becomes the channel silicon 3 'in which the carrier moves. Next, as shown in Fig. 4, a silicon oxide film 4 having a predetermined thickness is formed as a gate insulating film by oxidizing the silicon 3 'for channel. At this time, since the formed gate insulating film 4 is formed corresponding to the silicon film 3 formed by etching, the etched edge portion is angled with the channel silicon 3 'remaining after the etching. Next, as shown in FIG. 5, after the gate electrode material 5 is deposited, as shown in FIG. 6, a gate electrode 5 'having a predetermined shape is formed by etching. The region of source 6 / drain 7 is then defined and doped to form a junction.

그러나, 이러한 방식으로 형성된 종래의 핀 전계효과 트랜지스터는, 도1에 도시한 바와 같이, 채널의 에지 부분, 즉 (a)부분이 각을 이루고 있기 때문에 이 부분에서 전기장이 집중하게 되고, 그에 따라 게이트 전극의 동작 전압 이하에서 소자가 ON되는 현상이 나타나게 되어, 소자의 신뢰성에 문제가 있었다.However, in the conventional fin field effect transistor formed in this manner, as shown in Fig. 1, since the edge portion of the channel, that is, the portion (a) is angled, the electric field is concentrated at this portion, and thus the gate The phenomenon in which the device was turned on below the operating voltage of the electrode appeared, and there was a problem in the reliability of the device.

본 발명은 이러한 문제점을 해결하기 위해 이루어진 것으로, 종래 핀 전계효과 트랜지스터에서 문제를 일으키는 채널의 에지 부분에서의 전기장을 완화시킬 수 있는 방법을 제공하는 것을 목적으로 한다.SUMMARY OF THE INVENTION The present invention has been made to solve this problem, and an object thereof is to provide a method for mitigating an electric field at an edge portion of a channel causing a problem in a conventional fin field effect transistor.

이러한 목적을 달성하기 위해, 본 발명에 따른 반도체 소자의 제조 방법은,In order to achieve this object, a method of manufacturing a semiconductor device according to the present invention,

실리콘 기판 상에 질화막을 형성하는 단계; 상기 질화막 상에 실리콘 산화막을 형성하는 단계; 상기 실리콘 기판의 표면이 노출되도록 상기 실리콘 산화막과 질화막의 일부분을 제거하는 단계; 상기 노출된 실리콘 표면 상에서 채널용 실리콘을 성장시키는 단계; 상기 채널용 실리콘에 이온을 주입하는 단계; 상기 채널용 실리콘의 노출면을 따라 게이트 절연막을 형성하는 단계; 및 상기 채널용 실리콘을 포함하는 기판상에 게이트 전극을 형성하는 단계를 포함하고, 상기 채널용 실리콘의 성장은 선택적 실리콘 에피텍셜 성장에 의해 이루어지고, 상기 선택적 실리콘 에피텍셜 성장에 의해 채널용 실리콘의 에지가 라운드되는 것을 특징으로 한다.Forming a nitride film on the silicon substrate; Forming a silicon oxide film on the nitride film; Removing portions of the silicon oxide film and the nitride film to expose the surface of the silicon substrate; Growing silicon for the channel on the exposed silicon surface; Implanting ions into the silicon for the channel; Forming a gate insulating film along an exposed surface of the channel silicon; And forming a gate electrode on the substrate including the channel silicon, wherein the channel silicon is grown by selective silicon epitaxial growth, and the channel silicon is grown by selective silicon epitaxial growth. The edges are rounded.

이러한 본 발명에 따르면, 채널용 실리콘을 증착 및 식각의 방식으로 형성하지 않고, 선택적인 실리콘 에피텍셜 성장에 의해 형성하기 때문에, 채널 에지 부분이 자연스럽게 라운드되어 각진 채널 에지 부분에서 발생되던 전기장 집중 효과를 완화시킬 수 있기 때문에, 반도체 소자의 특성이 안정하게 된다.According to the present invention, since the silicon for the channel is formed by selective silicon epitaxial growth rather than by deposition and etching, the channel edge portion is naturally rounded, thereby reducing the electric field concentration effect generated at the angled channel edge portion. Since it can be relaxed, the characteristic of a semiconductor element becomes stable.

이하, 본 발명의 실시예를 도면을 참조하여 이하에 설명한다.Best Mode for Carrying Out the Invention Embodiments of the present invention will be described below with reference to the drawings.

도7 내지 도11은 본 발명에 따른 핀 전계효과 트랜지스터의 제조 공정을 도시한 단면도이다.7 to 11 are cross-sectional views showing the manufacturing process of the fin field effect transistor according to the present invention.

먼저, 도7에 도시한 바와 같이, 실리콘 기판(101) 상에 일정 두께의 질화막(102)을 절연막으로서 증착하고, 질화막(102) 상에 실리콘 산화막(103)을 형성한다. 이때, 증착되는 질화막(102)의 두께는 30~200Å인 것이 바람직하다. 또한, 실리콘 산화막(103)의 두께는 500~4000Å가 바람직하고, 이는 후술하는 채널 실리콘의 성장 두께 보다 1.5 내지 3배의 두께 범위에 있다. 그 다음으로, 도8에 도시한 바와 같이, 실리콘 에피텍셜 성장 공정을 실시하기 위해, 채널 지역의 실리콘 산화막(103)과 질화막(102)의 일부분을 실리콘 기판이 노출될 때까지 제거한다. 이 후, 노출된 실리콘 기판 부분에, 선택적 실리콘 에피텍셜 성장을 실시한다. 이러한 선택적 실리콘 에피텍셜 성장에 의하면, 도8에 도시한 바와 같이, 실리콘 산화막(103)과 경계한 부분(b)에서, 페시트(facet)라고 불리는 불균일 성장이 발생되어, 라운드된 채널용 실리콘(104)이 형성된다. 또한, 채널용 실리콘(104)의 성장은, 디 실란(SI2H6) 가스를 주로 하고, 수소(H2) 가스의 유입시에 염소(Cl2) 가스도 함께 유입함으로써 노출된 실리콘 기판 상에서만 성장이 이루어진다. 또한, SC-1 및 SPM 세정 공정을 이용하여 기판의 불순물을 제거하고 난 후, 채널용 실리콘의 성장 공정을 실시하여도 좋다. 다음으로, 도9에 도시한 바와 같이, 실리콘 산화막(103)을 제거하고 난 후, Vt 전압(소자의 턴온(turn on))을 결정하는 이온 주입을 실시한다. 이때, 채널용 실리콘(104)이 균일하게 도핑되도록, 틸트(tilt) 및 트위스트(twist)를 주어 4회전(rotation)하여 이온을 주입하고, 여기서, 틸트 각도는 10~70도(웨이퍼와 수평방향으로 평행한 경우를 0도라고 정의함)가 바람직하고, 트위스트 각도는 0~45도가 바람직하고, 4회전 각도로서는 0도, 90도, 180도, 270도가 바람직하다. 또한, 이러한 4회전 이온 주입을 대신하여 플라즈마 침식 방식(plasma immersion)을 이용해도 좋다. 이와 같이, 채널용 실리콘(104)에 대한 도핑이 완료된 후, 세정 공정을 통해 실리콘 표면의 불순물을 제거하고, 도10에 도시한 바와 같이, 채널용 실리콘(104)의 노출된 표면을 산화시켜 일정 두께의 실리콘 산화막(105)을 게이트 절연막으로서 형성한다. 그 다음에, 도11에 도시한 바와 같이, 게이트 절연막의 형성 후, 게이트 전극(106)을 형성한다. 또한, 게이트 전극(106)으로서 폴리 실리콘 전극 및 메탈 전극이 이용될 수 있다. First, as shown in FIG. 7, a nitride film 102 having a predetermined thickness is deposited as an insulating film on the silicon substrate 101, and a silicon oxide film 103 is formed on the nitride film 102. As shown in FIG. At this time, the thickness of the nitride film 102 to be deposited is preferably 30 ~ 200Å. In addition, the thickness of the silicon oxide film 103 is preferably 500 to 4000 GPa, which is in the range of 1.5 to 3 times the thickness of the growth thickness of the channel silicon described later. Next, as shown in Fig. 8, to perform the silicon epitaxial growth process, portions of the silicon oxide film 103 and the nitride film 102 in the channel region are removed until the silicon substrate is exposed. Thereafter, selective silicon epitaxial growth is performed on the exposed silicon substrate portion. According to such selective silicon epitaxial growth, as shown in Fig. 8, in the portion (b) bordered with the silicon oxide film 103, uneven growth called a facet occurs, and the round channel silicon ( 104 is formed. In addition, growth of the silicon silicon for the channel is mainly on the disilane (SI 2 H 6 ) gas, and on the exposed silicon substrate by introducing chlorine (Cl 2 ) gas together with the introduction of hydrogen (H 2 ) gas. Only growth takes place. In addition, after removing impurities from the substrate using the SC-1 and SPM cleaning processes, a growth process for silicon for the channel may be performed. Next, as shown in Fig. 9, after removing the silicon oxide film 103, ion implantation is performed to determine the Vt voltage (turn on of the device). At this time, in order to uniformly doped the silicon for the channel 104, by giving a tilt (twist) and a twist (twist) to rotate the four (rotation) implantation, the tilt angle is 10 ~ 70 degrees (wafer and horizontal direction Is defined as 0 degrees.), The twist angle is preferably 0 to 45 degrees, and the four rotation angles are preferably 0 degrees, 90 degrees, 180 degrees, and 270 degrees. Alternatively, plasma immersion may be used in place of such four-turn ion implantation. As described above, after the doping of the channel silicon 104 is completed, impurities are removed from the surface of the silicon through a cleaning process, and as shown in FIG. 10, the exposed surface of the channel silicon 104 is oxidized. A silicon oxide film 105 of thickness is formed as a gate insulating film. Next, as shown in FIG. 11, after the formation of the gate insulating film, the gate electrode 106 is formed. In addition, a polysilicon electrode and a metal electrode may be used as the gate electrode 106.

이상에서 설명한 본 발명 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge.

전술한 본 발명에 따르면, 채널의 에지 부분이 라운드되기 때문에, 에지 부분에서의 전기장의 집중 현상이 없어지게 되어, 소자의 신뢰성을 대폭 향상시킬 수 있다.According to the present invention described above, since the edge portion of the channel is rounded, the phenomenon of concentration of the electric field in the edge portion is eliminated, and the reliability of the device can be greatly improved.

Claims (5)

실리콘 기판 상에 질화막을 형성하는 단계;Forming a nitride film on the silicon substrate; 상기 질화막 상에 실리콘 산화막을 형성하는 단계;Forming a silicon oxide film on the nitride film; 상기 실리콘 기판의 표면이 노출되도록 상기 실리콘 산화막과 질화막의 일부분을 제거하는 단계;Removing portions of the silicon oxide film and the nitride film to expose the surface of the silicon substrate; 상기 노출된 실리콘 표면 상에서 채널용 실리콘을 성장시키는 단계;Growing silicon for the channel on the exposed silicon surface; 상기 채널용 실리콘에 이온을 주입하는 단계;Implanting ions into the silicon for the channel; 상기 채널용 실리콘의 노출면을 따라 게이트 절연막을 형성하는 단계; 및Forming a gate insulating film along an exposed surface of the channel silicon; And 상기 채널용 실리콘을 포함하는 기판상에 게이트 전극을 형성하는 단계;Forming a gate electrode on the substrate including the silicon for the channel; 를 포함하고,Including, 상기 채널용 실리콘의 성장은 선택적 실리콘 에피텍셜 성장에 의해 이루어지고, 상기 선택적 실리콘 에피텍셜 성장에 의해 채널용 실리콘의 에지가 라운드되는 The channel silicon is grown by selective silicon epitaxial growth, and the edge of the channel silicon is rounded by the selective silicon epitaxial growth. 반도체 소자의 제조 방법.Method of manufacturing a semiconductor device. 제1항에 있어서,The method of claim 1, 상기 채널용 실리콘의 성장 단계는, The growth step of the silicon for the channel, 디실란(SI2H6) 가스를 주로 하고, 수소(H2) 가스의 유입시 염소(Cl2) 가스도 함께 유입하는 것을 특징으로 하는 반도체 소자의 제조 방법.A method of manufacturing a semiconductor device, characterized in that the predominantly disilane (SI 2 H 6 ) gas, and also the chlorine (Cl 2 ) gas is also introduced when the hydrogen (H 2 ) gas is introduced. 제1항에 있어서,The method of claim 1, 상기 질화막의 두께는 30Å 내지 200Å의 범위에 있고, 상기 실리콘 산화막의 두께는 500Å 내지 4000Å 범위에 있는 것을 특징으로하는 반도체 소자의 제조 방법.The thickness of the nitride film is in the range of 30 kPa to 200 kPa, and the thickness of the silicon oxide film is in the range of 500 kPa to 4000 kPa. 제1항에 있어서,The method of claim 1, 상기 이온 주입 단계는, 틸트 및 트위스트를 주어 4회전(rotation) 이상 실시하고, 여기서 상기 틸트(tilt) 각도는 10°내지 70°, 트위스트(twist) 각도는 0° 내지 45°범위 내에 있으며, 회전은 0°, 90°, 180°, 270°인 것을 특징으로 하는 반도체 소자의 제조 방법.The ion implantation step is performed at least four rotations by giving a tilt and twist, wherein the tilt angle is in the range of 10 ° to 70 °, the twist angle is in the range of 0 ° to 45 °, the rotation Silver is 0 degrees, 90 degrees, 180 degrees, 270 degrees, The manufacturing method of the semiconductor element characterized by the above-mentioned. 제1항에 있어서,The method of claim 1, 상기 게이트 절연막은 채널용 실리콘의 산화에 의해 형성되는 실리콘 산화막인 것을 특징으로하는 반도체 소자의 제조 방법.And the gate insulating film is a silicon oxide film formed by oxidation of silicon for a channel.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100958798B1 (en) * 2008-04-04 2010-05-24 주식회사 하이닉스반도체 Method for fabricating semiconductor device
KR100960925B1 (en) * 2007-02-15 2010-06-04 주식회사 하이닉스반도체 Method of manufacturing semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100960925B1 (en) * 2007-02-15 2010-06-04 주식회사 하이닉스반도체 Method of manufacturing semiconductor device
KR100958798B1 (en) * 2008-04-04 2010-05-24 주식회사 하이닉스반도체 Method for fabricating semiconductor device
US8399324B2 (en) 2008-04-04 2013-03-19 Hynix Semiconductor Inc. Semiconductor device and method of fabricating the same

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