KR20070001592A - Method for forming gate of semiconductor device - Google Patents

Abstract

A method for fabricating a semiconductor device is provided to restraining generation of GIDL(Gate Induced Drain Leakage) current by forming lightly doped regions at edges of both sides of a gate poly silicon layer to reduce the electric field applied to a channel region corresponding to a gate region. A gate oxide layer(23) and a poly silicon layer(24) where a first conductive type impurity is ion-implanted are formed in turn on a semiconductor substrate(21). A hard mask pattern is formed on the poly silicon layer to form a gate(27). Second conductive type impurity is ion-implanted with a tilted angle into the poly silicon layer by using the hard mask pattern as an ion implantation barrier to form lightly doped regions at edges of both sides of the poly silicon layer part corresponding to a gate region. The poly silicon layer and the gate oxide layer are etched in turn by using the hard mask pattern as an etch barrier.

Description

METHOOD FOR FORMING GATE OF SEMICONDUCTOR DEVICE

1 is a cross-sectional view showing a semiconductor device formed according to the prior art.

2A through 2C are cross-sectional views illustrating processes for forming gates of a semiconductor device in accordance with an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

21 semiconductor substrate 22 device isolation film

23: gate oxide film 24: polysilicon film

25 metal silicide film 26 hard mask nitride film

27: gate 28: spacer

29: junction area

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a gate of a semiconductor device capable of improving a gate induced drain leakage (GIDL) current.

The channel length and junction area area of the cell transistor are decreasing with increasing integration of semiconductor devices, while the doping concentration to the channel and junction areas is increasing. As a result, a short channel effect in which the threshold voltage Vt decreases rapidly is induced, and a junction leakage current increases due to an increase in an electric field, resulting in deterioration of device characteristics.

In particular, the junction leakage current is generated very large at the point where the channel and the junction region contact each other, because a large electric field is applied at the point where the channel and the junction region contact. A representative example of the current leakage phenomenon that occurs at the overlap point of the channel and the junction region is GIDL (Gate Induced Drain Leakage) current.

The junction leakage current including the GIDL is a major factor for reducing the refresh time of the device, which is a problem that must be solved for high integration and improved reliability of the device.

1 is a cross-sectional view showing a semiconductor device formed according to the prior art, with reference to this to explain the manufacturing method and problems.

First, a gate oxide film 3, a doped polysilicon film 4, a tungsten silicide film 5, and a hard mask nitride film 6 are sequentially formed on the semiconductor substrate 1 having the device isolation film 2. Subsequently, the films 6, 5, 4 and 3 are sequentially patterned to form a gate 7.

Then, an oxide film and a nitride film are deposited on the substrate product including the gate 7, and then anisotropically etched to form a spacer 8 on the sidewall of the gate 7, and then on both sides of the gate 8. Impurity ion implantation is performed in the region to form a source / drain junction region 9 in the exposed substrate.

Thereafter, although not shown, a semiconductor device is completed by performing a well-known subsequent process.

However, in the above-described semiconductor device according to the related art, as described above, the channel region formed in the lower substrate of the gate oxide film 3 and the junction region 9 are in contact with each other as the doping concentration increases with respect to the junction area due to high integration. The field concentration at the point increases, which causes a problem that the GIDL effect is increased to degrade the refresh characteristics of the device.

Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device capable of effectively suppressing GIDL current in a highly integrated device.

A method of forming a gate of a semiconductor device of the present invention for achieving the above object comprises the steps of sequentially forming a gate oxide film and a polysilicon film implanted with a first conductivity type impurity on a semiconductor substrate; Forming a hard mask pattern for forming a gate on the polysilicon layer; Forming a lightly doped region on each of both edges of the polysilicon film portion corresponding to the gate region by obliquely implanting a second conductive impurity into the polysilicon film using the hard mask pattern as an ion implantation barrier. ; And etching the polysilicon layer and the gate oxide layer in sequence using the hard mask pattern as an etch barrier.

Here, the gradient ion implantation is performed twice while rotating the substrate 180 °.

In addition, the gate forming method of the semiconductor device of the present invention, after the step of forming a polysilicon film implanted with the first conductive type impurity, and then forming a hard mask pattern for the gate formation on the polysilicon film The method may further include forming a metal silicide film or a metal film on the polysilicon film.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A through 2C are cross-sectional views of processes for describing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 2A, the gate oxide layer 23 is formed as a gate insulating layer on the semiconductor substrate 21 on which the isolation layers 22 are formed, according to a known shallow trench isolation (STI) process.

Thereafter, a polysilicon film 24 into which the first conductivity type impurity is ion-implanted is formed on the gate oxide film 23 to a thickness of 600 to 700 Å. Subsequently, a metal silicide layer 25 such as a tungsten silicide layer is formed on the polysilicon layer 24 to realize low resistance of the gate.

In the present invention, the metal silicide film is formed for the purpose of realizing the low resistance of the gate as described above, but depending on the purpose, a laminated film of tungsten nitride film and tungsten film may be formed instead of the metal silicide film.

Thereafter, a hard mask nitride layer 26 is formed on the metal silicide layer 25, and then a photoresist pattern (not shown) for gate formation is formed on the hard mask nitride layer 26.

Referring to FIG. 2B, the hard mask nitride layer 26 is patterned using the photoresist pattern (not shown) as an etch barrier, and then a metal silicide layer is formed using the hard mask nitride layer 26 as an etch barrier. Etch (25).

Then, by using the patterned hard mask nitride layer 26 and the metal silicide layer 25 as an ion implantation barrier, a second conductive impurity is implanted into the polysilicon layer 24 while rotating the substrate by 180 °. In this manner, the doped regions are inclined twice to form lightly doped regions at both edges (region A in FIG. 2B) of the polysilicon film 24 corresponding to the gate region.

In this case, when the polysilicon layer 24 is a polysilicon layer doped with n-type impurities, the p-type impurities such as boron may be ion-implanted during the inclined ion implantation so that the edges of both sides of the polysilicon layer corresponding to the gate region may be Lower the n-type impurity concentration.

Referring to FIG. 2C, using the patterned hard mask nitride layer 26 and the metal silicide layer 25 as an etch barrier, the polysilicon layer 24 and the gate oxide layer 23 are sequentially etched to form the gate 27. Form.

Then, an oxide film and a nitride film are deposited on the substrate product including the gate 27, and then anisotropically etched to form a spacer 28 on the sidewall of the gate 27, and then the spacer 28 and the spacer 28. A source / drain junction region 29 is formed by using a gate 27 as an ion implantation barrier to ion implant a high concentration of first conductive impurities into the substrate.

In the present invention, as described above, the lightly doped region is formed at each of the edges of the gate polysilicon film 24 by the inclined ion implantation, so that the electric field applied to the channel region corresponding to the portion is reduced, thereby joining the channel. The generation of GIDL current at the overlap point between the areas 29 is effectively suppressed. As a result, the effect of improving the refresh characteristics of the device can be obtained.

Subsequently, although not shown, the semiconductor device of the present invention is completed by sequentially performing subsequent known processes.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

As described above, the present invention forms a low concentration doped region at each of both edges of the gate polysilicon film during gate formation of the semiconductor device, thereby reducing the electric field applied to the channel region corresponding to the portion, thereby reducing the gate induced drain (GIDL). Leakage) It can suppress the occurrence of current. Accordingly, according to the method of the present invention, the effect of improving the refresh characteristics of the device can be obtained.

Claims (3)

Sequentially forming a gate oxide film and a polysilicon film ion-implanted with a first conductive impurity on a semiconductor substrate; Forming a hard mask pattern for forming a gate on the polysilicon layer; Using the hard mask pattern as an ion implantation barrier to form a lightly doped region on each side edge of the polysilicon film portion corresponding to the gate region by oblique ion implantation of a second conductive impurity into the polysilicon film; And And sequentially etching the polysilicon layer and the gate oxide layer by using the hard mask pattern as an etch barrier. The polysilicon layer of claim 1, further comprising after forming the polysilicon layer into which the first conductivity type impurity is ion-implanted, and before forming the hard mask pattern for gate formation on the polysilicon layer. Forming a metal silicide film or a metal film in the gate forming method of a semiconductor device characterized in that it further comprises. The method of claim 1, wherein the inclined ion implantation is performed twice while rotating the substrate 180 °.

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