KR20060136177A - Fuse box of semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fuse box of a semiconductor device. The fuse box may be rearranged in consideration of an etching rate according to the plasma density of the semiconductor device, and a residual oxide (Rox) may be uniformly formed to prevent a fuse attack. Disclosed is a technique for enabling it. The present invention can evenly reflect the etch loading effect according to the pattern density of the fuse box during the repair etching process for opening the fuse box in the chip, so that the residual oxide film is formed in the fuses of all the fuse boxes regardless of the size of the open area. Allow for even distribution. Accordingly, the present invention prevents a fuse attack caused by excessive oxide film etching on the small fuse and prevents an attack during the blow of the fuse, thereby improving the FTA (Fixed To Attemption) yield.

Description

Fuse box of semiconductor device

1 and 2 are a plan view of a fuse box of a semiconductor device according to the prior art.

3 and 4 are plan views of the fuse box of the semiconductor device according to the present invention.

5 to 7 are plan views for explaining the configuration of the dummy fuse box in the fuse box of the semiconductor device according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fuse box of a semiconductor device. The fuse box may be rearranged in consideration of an etching rate according to the plasma density of the semiconductor device to uniformly form a residual oxide (Rox) to prevent a fuse attack. It's a technology that makes it possible.

In general, when a defect occurs in any one of a number of fine cells, semiconductor devices such as DRAM and SRAM cannot be used as a defective part and are treated as defective products. However, despite the high probability that defects may occur in only a small number of cells as the degree of integration of semiconductor memory devices increases, discarding them as defective products is an inefficient treatment method that lowers yield.

Therefore, in order to solve this problem, if a defect occurs in a cell of a specific region when manufacturing a semiconductor memory device, a column or a row line is prepared to replace a cell or a row line where a cell in which the defect occurs is replaced. The technology of replacing with column or row line is widely known.

In the circuit structure of the semiconductor device, a defective device is generated or a metal fuse is used as a means for disconnecting electrical connection of a specific device as necessary. That is, the repair process is a process for preventing the entire device from being used when a fail occurs in a part of the fuse. The repair process is a process of cutting a fuse having a fail by performing laser cutting on the fuse having the fail. At this time, the wiring broken by the irradiation of the laser is called a fuse, and the broken part and the area surrounding it are called a fuse box.

Here, the fuse box includes a redundancy fuse box for controlling the cell redundancy and an optional fuse box for controlling an option circuit for evaluating the characteristics of the product or for controlling the level of the internal voltage. .

However, the conventional redundancy fuse box has a large number of fuses for controlling a large number of redundancy fuses, so that the open area size of the fuse box is large. In contrast, since the option fuse box has a small number of fuses corresponding to each function, the size of the open area of the fuse box is small.

Therefore, hereinafter, a fuse box having a large open area size of a fuse box, such as a redundant fuse box, is called a large fuse box, and a fuse box having a small open area size of a fuse box, such as an optional fuse box, is called a small fuse box.

1 and 2 are plan views of a fuse box of a semiconductor device according to the prior art.

In the conventional fuse box, four banks 3 are provided in the die 1, and a large fuse box 4 having a large open area size is formed in the ferry region 2 between each bank 3 region. A small fuse box 5 having a small open area size is formed at a distance from the large fuse box 4.

2 shows a residual oxide film 6 formed above the fuse f1 of the large fuse box 4 and a residual oxide film 7 formed above the fuse f2 of the small fuse box 5. When the large fuse box 4 is cut to the AA 'cross-section, when the small fuse box 5 is cut to the AA' cross-section, compared to the large amount of residual oxide film 6 remaining in the fuse f1 of the large fuse box 4, It can be seen that little residual oxide film 7 remains in the fuse f2 of the small fuse box 5.

The repair etching process, which is an open process of the fuse box, is performed by dry etching using plasma. In this case, a loading effect phenomenon in which the oxide etch rate is different depending on the pattern density may appear. Due to the loading effect phenomenon, the fuse f1 of the large fuse box 4 has a thicker residual oxide film (Rox) 6 than the fuse f2 of the small fuse box 5.

Therefore, effectively controlling the residual oxide film formed on the repair fuse in the fuse box provided in the DRAM chip is a very important factor to ensure the stability of the success rate during the blowing of the fuse.

The remaining oxide film formed on the top of the fuse has a constant thickness that satisfies the optimum fuse blowing conditions. However, when the residual oxide films 6 and 7 are different according to the loading effect phenomenon of the large fuse box 4 having the large size and the small fuse box 5 having the small size, the optimum residual oxide target is placed on the upper portion of the fuse. Difficult to set up

In particular, in order to ensure stability of the FTA (Fixed To Attemption) yield indicating the success rate of the redundancy cell, when a target of the residual oxide film is set in accordance with the redundancy fuse box, and the etching is performed, the fuse is removed by the loading effect during the repair etching. No residual oxide film remains on the top. As a result, a fuse attack occurs, causing a malfunction of the option circuit, or a failure in the DRAM operation due to an abnormal shift of the internal voltage.

In addition, the residual oxide films 6 and 7 of the fuse line formed in the outermost part of the same fuse box remain less than the residual oxide films 6 and 7 of the fuse line located in the inner part, so that the fuse blowing success rate of the outermost fuse line is reduced. There is a problem falling.

Therefore, in order to solve this problem, a dummy fuse line is added to the outside of the outermost fuse line. That is, the dummy fuse lines of the fuse boxes 4 and 5 are formed in the same number, for example, two at each end. Accordingly, the conventional dummy fuse lines are four in the small fuse box 5 in the large fuse box 4 to have eight dummy fuse lines in all.

However, in this case, as the dummy fuse line is additionally formed, the layout area is increased, thereby increasing the die size and reducing the number of net dies that can be produced per wafer.

The present invention was created in order to solve the above problems, by rearranging the large fuse box and the small fuse box in consideration of the etching rate according to the plasma density of the semiconductor device and by forming a residual oxide (Rox) uniformly The purpose is to prevent a fuse attack.

The fuse box of the semiconductor device of the present invention for achieving the above object, a plurality of bank regions formed on the die; And a fuse box set having a first fuse box and a second fuse box of a different size adjacent to the first fuse box, wherein the fuse box sets are spaced apart at regular intervals from the ferry area between the plurality of bank areas. It is characterized by being formed with a uniform pattern density.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

3 is a plan view of a fuse box of a semiconductor device according to the present invention.

In the present invention, four banks 30 are positioned on the die 10, and a large fuse box 40 is arranged in a ferry region 20 between each bank 30 region, and the large fuse box 40 is disposed. Two small fuse boxes 50 and 51 are arranged at both adjacent side portions of the substrate.

Then, a pattern consisting of one large fuse box 40 and two small fuse boxes 50 and 51 is formed as one fuse box set 60. The fuse box set 60 is regularly spaced apart at regular intervals, so that all the fuse box can reflect the same loading effect regardless of the size of the fuse box.

That is, the large fuse box 40 and the small fuse box 50, 51 are present in the same pattern group by using the principle that the etching loading effect is the same at the same pattern density. As shown in FIG. 4, when the fuse box set 60 is cut in the BB ′ direction, the residual oxide film 70 formed in the fuse f3 of the large fuse box 40 and the fuses f4 and f5 of the small fuse boxes 50 and 51. It can be seen that the thicknesses of the remaining oxide films 71 and 72 formed in the substantially same thickness.

In addition, in the fuse box set 60, the edge area is relatively well etched in the open area of the same fuse box. As a result, dummy fuse lines 52 and 53 are formed in the edge regions of the respective fuses f4 and f5 in order to solve a problem in which residual oxide films remain in the open area of the fuse box.

Accordingly, since a total of four dummy fuse lines 52 and 53 are provided for one fuse box set 60, the dummy fuse line can be cut in half compared to the conventional method.

In addition, the test box fuse box 80 corresponds to a small fuse box, but because the area occupied by the circuit is large, the fuse box 80 may not be configured in the fuse box set 60 together with the large fuse box 40. Accordingly, in the case of the test box fuse box 80 in which the circuits must be independently arranged, as shown in FIG. 5, the edge region of the bank 30, in particular, the four corner regions inside the die 10. To be located at In addition, a separate dummy fuse box 90 is formed in the outer corner region of the die 10.

FIG. 6 shows that the test box fuse box 80 is provided in the corner region inside each die 10. In addition, a dummy fuse box 90 is disposed in a scribe lane C formed for die sawing in an outer region of the adjacent die 10. At this time, the size of the scribe lane (C) is set to 100㎛.

Accordingly, the test box fuse box 80 formed independently may be disposed together with the adjacent dummy fuse box 90 to increase the pattern density so that the repair etch loading effect may be reflected. Therefore, the same loading effect as the other large fuse box 40 formed inside the die 10 may be reflected.

In particular, when the dummy fuse box 80 is formed in the scribe lane C adjacent to the four corners of the die 10 in the wafer die map, each dummy in the scribe lane C of the adjacent die is formed. Since the fuse box 90 is gathered together, the area increase effect can be increased.

Here, as shown in FIG. 7, the dummy fuse box 90 formed in the scribe lane C has the test mode along the scribe lane C when the neighboring test mode fuse box 80 is opened. It is formed by opening at least 20 μm (D) larger than the fuse box 80.

That is, during the repair mask process, the photoresist of the test box fuse box 80 is selectively opened through an exposure and development process, and when the oxide film is removed by the repair etching process, the dummy fuse box 90 is the same process. It is formed as.

According to the present invention, redundancy fuses, level trimming fuses, and option fuses, which do not form a fuse box with a predetermined size, are divided into a large fuse box and a small fuse box according to the size of the fuse box open area. The box and the small fuse box are formed adjacent to each other so that the same etching loading effect can be reflected during the repair of the fuse box opening process.

In addition, another embodiment of the present invention is to form a small fuse box in the four corner areas of the wafer chip and a dummy fuse box in the scribe lane area instead of the main chip, to reduce the area of the main chip to the large fuse box Make sure to reflect the same etch loading effect as the fuse box.

As described above, the present invention allows the remaining oxide film on the upper part of the fuse to be formed on all fuse boxes in the same manner, thereby stably forming the residual oxide film during the repair etching process, and preventing the fuse attack caused by the excessive etching process. Help increase FTA success rate

In addition, a dummy fuse box is formed in four corner regions of the wafer chip and adjacent to a neighboring wafer, and a dummy fuse box is formed in four scribe lanes corresponding to the small fuse box belonging to one chip to achieve an etch loading effect. It provides an effect that can be improved.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as being in scope.

Claims (10)

A plurality of bank regions formed in the die; And A fuse box set having a first fuse box and a second fuse box of a different size adjacent to the first fuse box; The fuse box set is spaced apart at regular intervals in the ferry region between the plurality of bank regions a plurality of fuse box of the semiconductor device, characterized in that formed with a uniform pattern density. The fuse box of claim 1, wherein the ratio of the number of the first fuse box and the second fuse box in the one fuse box set is 1: 2. The fuse box of claim 1, wherein the first fuse box is a redundancy fuse box. The fuse box of claim 1, wherein the second fuse box is an optional fuse box. The fuse box of claim 1, further comprising dummy fuse lines formed at equal numbers on both edges of the fuse box set. The fuse box of claim 1, further comprising a plurality of test mode fuse boxes positioned at respective corner regions of the die. The fuse box of claim 6, further comprising a plurality of dummy fuse boxes formed at scribe lane regions adjacent to the plurality of test mode fuse boxes at outer corners of the die. The semiconductor device of claim 7, wherein each of the plurality of dummy fuse boxes is larger than the test mode fuse box along the scribe lane area when the adjacent test mode fuse box is opened during a repair etching process. Fuse box. The fuse box of claim 8, wherein each of the plurality of dummy fuse boxes is opened at least 20 μm or more in height and width than the fuse box for the test mode. The fuse box of claim 7, wherein the dummy fuse box is formed in a “b” or “a” shape.

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